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powerpc, 8xx: Move cache function into C files

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Avoid unnecessary assembly functions when they can easily be written
in C.

Also remove dc_read() as it is nowhere referenced

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
This commit is contained in:
Christophe Leroy 2017-07-13 15:10:00 +02:00 committed by Tom Rini
parent 36d3260756
commit 1e7cefef58
3 changed files with 50 additions and 56 deletions
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1
arch/powerpc/cpu/mpc8xx/Makefile
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@ -14,3 +14,4 @@ obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-y += speed.o
obj-y += cache.o

49
arch/powerpc/cpu/mpc8xx/cache.c Normal file
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@ -0,0 +1,49 @@
/*
* (C) Copyright 2017
* Christophe Leroy, CS Systemes d'Information, christophe.leroy@c-s.fr
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/ppc.h>
#include <asm/io.h>
#include <asm/mmu.h>
int icache_status(void)
{
return !!(mfspr(IC_CST) & IDC_ENABLED);
}
void icache_enable(void)
{
sync();
mtspr(IC_CST, IDC_INVALL);
mtspr(IC_CST, IDC_ENABLE);
}
void icache_disable(void)
{
sync();
mtspr(IC_CST, IDC_DISABLE);
}
int dcache_status(void)
{
return !!(mfspr(IC_CST) & IDC_ENABLED);
}
void dcache_enable(void)
{
mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */
mtspr(DC_CST, IDC_INVALL);
mtspr(DC_CST, IDC_ENABLE);
}
void dcache_disable(void)
{
sync();
mtspr(DC_CST, IDC_DISABLE);
mtspr(DC_CST, IDC_INVALL);
}

56
arch/powerpc/cpu/mpc8xx/start.S
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@ -305,62 +305,6 @@ int_return:
SYNC
rfi
/* Cache functions.
*/
.globl icache_enable
icache_enable:
SYNC
lis r3, IDC_INVALL@h
mtspr IC_CST, r3
lis r3, IDC_ENABLE@h
mtspr IC_CST, r3
blr
.globl icache_disable
icache_disable:
SYNC
lis r3, IDC_DISABLE@h
mtspr IC_CST, r3
blr
.globl icache_status
icache_status:
mfspr r3, IC_CST
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
.globl dcache_enable
dcache_enable:
lis r3, 0x0400 /* Set cache mode with MMU off */
mtspr MD_CTR, r3
lis r3, IDC_INVALL@h
mtspr DC_CST, r3
lis r3, IDC_ENABLE@h
mtspr DC_CST, r3
blr
.globl dcache_disable
dcache_disable:
SYNC
lis r3, IDC_DISABLE@h
mtspr DC_CST, r3
lis r3, IDC_INVALL@h
mtspr DC_CST, r3
blr
.globl dcache_status
dcache_status:
mfspr r3, DC_CST
srwi r3, r3, 31 /* >>31 => select bit 0 */
blr
.globl dc_read
dc_read:
mtspr DC_ADR, r3
mfspr r3, DC_DAT
blr
/*
* unsigned int get_immr (unsigned int mask)
*