- use OPP information in device tree for 800MHz/650MHz support
- ram: inprovments of test command
- solve boot on closed chip when access to DBGMCU_IDC is protected
- stm32prog command: Add "device anme" during USB enumeration
- update configs: activate WATCHDOG and 'env erase' command,
increase teed partition, support SD card after NOR boot by default and
use env info in env_check
- some sboard cleanups: gpio hog in dh board, specific driver for
type-c stusb1600 controller code in a driver move part of code in spl.c
and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
drivers
- vrefbuf: fix a possible overshoot when re-enabling
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Merge tag 'u-boot-stm32-20200707' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- arch and board update for stm32mp15:
- use OPP information in device tree for 800MHz/650MHz support
- ram: inprovments of test command
- solve boot on closed chip when access to DBGMCU_IDC is protected
- stm32prog command: Add "device anme" during USB enumeration
- update configs: activate WATCHDOG and 'env erase' command,
increase teed partition, support SD card after NOR boot by default and
use env info in env_check
- some sboard cleanups: gpio hog in dh board, specific driver for
type-c stusb1600 controller code in a driver move part of code in spl.c
and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
drivers
- vrefbuf: fix a possible overshoot when re-enabling
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Merge tag 'u-boot-atmel-2020.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2020.10 cycle
ARM Architecture reference manual clearly states that PE pipeline
should be flushed after changes to some system registers. Refer to
paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture
Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI
0487B.a).
Failing to issue instruction synchronization barrier can lead to
spurious errors, like synchronous exception when accessing FPU
registers. This is very prominent on CPUs with long instruction
pipeline, like ARM Cortex A72.
This change fixes the following U-Boot panic:
"Synchronous Abort" handler, esr 0x1fe00000
elr: 00000000800948cc lr : 0000000080091e04
x0 : 00000000801ffdc8 x1 : 00000000000000c8
x2 : 00000000800979d4 x3 : 00000000801ffc60
x4 : 00000000801ffd40 x5 : ffffff80ffffffd8
x6 : 00000000801ffd70 x7 : 00000000801ffd70
x8 : 000000000000000a x9 : 0000000000000000
x10: 0000000000000044 x11: 0000000000000000
x12: 0000000000000000 x13: 0000000000000000
x14: 0000000000000000 x15: 0000000000000000
x16: 000000008008b2e0 x17: 0000000000000000
x18: 00000000801ffec0 x19: 00000000800957b0
x20: 00000000000000c8 x21: 00000000801ffdc8
x22: 000000008009909e x23: 0000000000000000
x24: 0000000000000000 x25: 0000000000000000
x26: 0000000000000000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000801ffc50
Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0)
While executing instruction
str q0, [sp, #112]
in vsnprintf() prologue. This panic was observed only on Cortex A72 so
far.
This patch places ISBs on other strategic places as well.
Also, this probably is the right fix for the issue workarounded in the
commit 45f41c134b ("ARM: uniphier: add weird workaround code for LD20")
Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Suggested-by: Julien Grall <julien.grall.oss@gmail.com>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
CC: Tom Rini <trini@konsulko.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <julien@xen.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Activate CMD_NVEDIT_INFO and use the new command "env info -d -p -q"
to automatically save the environment on first boot.
This patch allows to remove the env_default variable.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
As debugger must be totally closed on Sec closed chip,
the DBGMCU_IDC register is no more accessible (self
hosted debug is disabled with OTP).
This patch adds a function bsec_dbgswenable() to check
if the DBGMCU registers are available before to access them:
BSEC_DENABLE.DBGSWENABLE = self hosted debug status.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add "Device Name" in iproduct during DFU USB enumeration
to have this information in STM32CubeProgrammer trace
(this tools is compatible with @Name since v2.3)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add a function stmpic_init to early initialize the PMIC STPMIC1
- keep vdd on during the reset cycle (to avoid issue when backup battery
is absent)
- Check if debug is enabled to program PMIC according to the bit
This patch allows to remove the compilation of spl.c file from stm32mp1
board in dh_stm32mp1.
CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier
in SPL, in the function board_early_init_f.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Add the bsec driver in SPL, as it is needed by SOC part number detection
to found the supported OPP.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
- Minor updates to some platforms I am the listed maintainer of.
Notably this removes the ti814x_evm which stopped building with the PXA
MMC migration series (oops) but hasn't been functional in some time.
The TI814x (DM814x) platform is rather old and in need of a lot of
migration work. As much of that work is well past the deadline, remove
this platform.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Makefile: add rule to build an endian-swapped U-Boot image
used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
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Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next
- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
This patch moves the CONFIG_DM_SPI_FLASH and CONFIG_SPI_FLASH_DATAFLASH
to be defined in Kconfig, not in board specific header file
(include/configs/<board>.h).
Before this change the CONFIG_DM_SPI_FLASH was not set in .config (so it
was not possible to use CONFIG_IS_ENABLED(DM_SPI_FLASH) in SPI DM/DTS
converted drivers), but it was set in u-boot.cfg file.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This patch fixes issue with defining the DM_SPI_FLASH in the
configs/include/<board.h> instead of enabling this option in Kconfig.
The problem is that CONFIG_IS_ENABLED(DM_SPI_FLASH) shows false as there
is no DM_SPI_FLASH=y in .config (but the define is set in u-boot.cfg).
As a result conversion of DM_SPI_FLASH to using CONFIG_IS_ENABLED() is not
working properly.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This change allows more fine tuning of driver model based SPI support in
SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
support in SPL and TPL via Kconfig option.
Before this change it was necessary to use:
/* SPI Flash Configs */
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#undef CONFIG_SPI_FLASH_MTD
#endif
in the ./include/configs/<board>.h, which is error prone and shall be
avoided when we strive to switch to Kconfig.
The goal of this patch:
Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
still support non DM driver.
Another use case is the conversion of non DM/DTS SPI driver to support
DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
distinction is needed in Kconfig (also if SPL version of the driver
supports OF_PLATDATA).
In the end of the day one would have to support following use cases (in
single driver file - e.g. mxs_spi.c):
- U-Boot proper driver supporting DT/DTS
- U-Boot proper driver without DT/DTS support (deprecated)
- SPL driver without DT/DTS support
- SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
run full blown DT/DTS)
- SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
environment with no fitImage and OF_LIBFDT support).
Some boards do require SPI support (with DM) in SPL (TPL) and some only
have DM_SPI{_FLASH} defined to allow compiling SPL.
This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
and provides corresponding defines in Kconfig.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[trini: Fixup a few platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e1 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
While in most cases CSF_SIZE is handled via Kconfig we have some i.MX8M
platforms that set the size based on the now-renamed CONFIG_SECURE_BOOT
symbol. Update things so that CSF_SIZE itself depends on IMX_HAB being
enabled and provide the default value for i.MX8M family of parts.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ye Li <ye.li@nxp.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ye Li <ye.li@nxp.com>
There are a few remaining places where we say CONFIG_SECURE_BOOT rather
than CONFIG_IMX HAB. Update these instances.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Eddy Petrișor <eddy.petrisor@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.
This fixes write to invalid address.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
We don't really want to have ARM-specific code in a generic file. Create
a new arch-specific function to hold it, and move it into that.
Make the function weak so that any arch can implement it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since commit:
commit 6333cbb381
Author: Michael Walle <michael@walle.cc>
Date: Thu May 7 00:11:58 2020 +0200
phy: atheros: ar8035: remove static clock config
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
, the clock output setting for the AR803x driver is removed from being
hardcoded in the PHY driver and should be passed via device tree instead.
Update the device tree with the "qca,clk-out-frequency" property so that
Ethernet can work again.
Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
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Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
XDP - Xilinx Drone Platform is a board for drones or other UAV.
Pinmux the SD card by default, and if the SD card detect line is high
(inactive) then pinmux the SD1 interface to EMIO instead. SD is placed on
extension card and shares connection with on board wife. That means that
when SD card is present in the board wifi can't be used.
There seems to be an issue with DDR access from PL at 2400MT/s, after
updating the PMU and ATF firmware this is causing extremely slow DDR
access. Reducing the DDR speed from 2400 to 2133 appears to solve that
issue, even though the hardware has proven to be 2400 capable.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change mini u-boot qspi spi-max-frequency to 108Mhz, make the
frequency similar to full u-boot qspi flash spi-max-frequency.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Current aliases missed gpio0 node, and this node shoud be
aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we
will get below message when running "gpio status" command, and
see the reason by "dm uclass".
=> gpio status
Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000'
Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000'
Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000'
=> dm uclass
uclass 36: gpio
0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1)
1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0)
2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1)
3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2)
4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3)
5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4)
6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5)
7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6)
Signed-off-by: Ye Li <ye.li@nxp.com>
Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot
text base is picked as the one used by various MX7 boards. The SPL
text base however is different.
The SPL text base is set to 0x912000 instead of the usual 0x911000,
that is because the 0x911000 value cannot work. Using 0x911000 as a
SPL text base will result in the DCD header being placed below the
0x911000 address, which is a reserved SRAM area which must not be
used. This will actually trigger eMMC boot failure on MX7D at least.
Hence the increment.
Update all boards affected by this SPL problem to the new SPL_TEXT_BASE.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
There are systems where board_early_init_f() is plain empty. Switch
the config option from "select" to "imply", to permit user to unset
the BOARD_EARLY_INIT_F if it were to be empty.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.
This problem has been exposed by commit:
commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu May 7 00:11:51 2020 +0200
phy: atheros: Explicitly disable RGMII delays
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix the phy-mode accordingly to fix the regression.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Sync the device tree with 5.8-rc1.
It basically contains the following extra kernel commit:
commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date: Wed Apr 15 16:44:17 2020 +0100
ARM: dts: imx6-sr-som: add ethernet PHY configuration
Add ethernet PHY configuration ahead of removing the quirk that
configures the clocking mode for the PHY. The RGMII delay is
already set correctly.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This avoid potential issue for SDCard boot:
the card detect fails with floating gpio.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
- use 'vidconsole' stdout in nitrogen6x upgrade script
- add option for selection of the vidconsole commands
lcdputs and setcurs
- allow building ipuv3 driver with disabled CONFIG_PANEL
- make backlight and panel drivers optional
- remove useless code from ipuv3 driver
- extend existing DM_VIDEO work-around for console name
to support 'vga'
- remove non-DM code in ipuv3
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Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into next
- migrate remaining imx5/imx6qd boards to DM_VIDEO
- use 'vidconsole' stdout in nitrogen6x upgrade script
- add option for selection of the vidconsole commands
lcdputs and setcurs
- allow building ipuv3 driver with disabled CONFIG_PANEL
- make backlight and panel drivers optional
- remove useless code from ipuv3 driver
- extend existing DM_VIDEO work-around for console name
to support 'vga'
- remove non-DM code in ipuv3
The PSCI nodes are currently not populated for the Tegra210 and Tegra186
devices. This prevents the PSCI driver from being able to identify the
PSCI method used by these devices and causes the probe of the PSCI
driver to fail.
Since commit 81ea00838c ("efi_loader: PSCI reset and shutdown") was
added, which moves the PSCI EFI system reset handler into the PSCI
driver, this has prevented the EFI system reset from working for
Tegra210 and Tegra186. Therefore, populating these nodes is necessary
to fix the EFI system reset for Tegra210 and Tegra186.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
cfb_console driver uses 'vga' console name and we still have board
environments defining this name. Re-use existing DM_VIDEO work-
around for console name to support 'vga' name in stdout environment.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Soeren Moch <smoch@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
According to the linker script for both armv7 and arm926ejs based SoC,
BSS section was all the time separated for SPL but this symbol was
only enabled on some boards. However, it is necessary to have it
enabled for OF_SEPARATE configuration where DTB is appended to u-boot
with DTB.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
