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- net: pcnet: cleanup and add DM support

Browse Source 
- Makefile: add rule to build an endian-swapped U-Boot image
   used by MIPS Malta EL variants
 - CI: add Qemu tests for MIPS Malta
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Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next

- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
  used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
This commit is contained in:
Tom Rini 2020-06-30 11:43:18 -04:00
commit 5fdb3c0e7e
35 changed files with 292 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
.azure-pipelines.yml
View File

@ -226,6 +226,22 @@ jobs:
qemu_mips64el:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_maltael:
TEST_PY_BD: "maltael"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64:
TEST_PY_BD: "malta64"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64el:
TEST_PY_BD: "malta64el"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_ppce500:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"

32
.gitlab-ci.yml
View File

@ -276,6 +276,38 @@ qemu_mips64el test.py:
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_malta test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_maltael test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "maltael"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64 test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta64"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64el test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta64el"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu-ppce500 test.py:
tags: [ 'all' ]
variables:

28
.travis.yml
View File

@ -573,6 +573,34 @@ matrix:
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips64el-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta"
env:
- TEST_PY_BD="malta"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-maltael"
env:
- TEST_PY_BD="maltael"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mipsel-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta64"
env:
- TEST_PY_BD="malta64"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips64-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta64el"
env:
- TEST_PY_BD="malta64el"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips64el-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-ppce500"
env:
- TEST_PY_BD="qemu-ppce500"

6
Makefile
View File

@ -1733,6 +1733,12 @@ u-boot-mtk.bin: u-boot.bin FORCE
$(call if_changed,mkimage)
endif
quiet_cmd_endian_swap = SWAP $@
cmd_endian_swap = $(srctree)/tools/endian-swap.py $< $@
u-boot-swap.bin: u-boot.bin FORCE
$(call if_changed,endian_swap)
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot

11
arch/arm/dts/imx6q-tbs2910.dts
View File

@ -107,7 +107,18 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
};
};
};
&hdmi {

21
arch/arm/mach-rockchip/rk3188/rk3188.c
View File

@ -77,15 +77,32 @@ int arch_cpu_init(void)
BYPASSSEL_MASK | BYPASSDMEN_MASK,
1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
#endif
return 0;
}
#endif
__weak int rk3188_board_late_init(void)
{
return 0;
}
int rk_board_late_init(void)
{
struct rk3188_grf *grf;
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(grf)) {
pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
return 0;
}
/* enable noc remap to mimic legacy loaders */
rk_clrsetreg(&grf->soc_con0,
NOC_REMAP_MASK << NOC_REMAP_SHIFT,
NOC_REMAP_MASK << NOC_REMAP_SHIFT);
return 0;
return rk3188_board_late_init();
}
#endif
#ifdef CONFIG_SPL_BUILD
static int setup_led(void)

2
arch/arm/mach-socfpga/misc_s10.c
View File

@ -68,7 +68,7 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
return -EINVAL;
clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0 +
gmac_index,
(gmac_index * sizeof(u32)),
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
return 0;

3
cmd/bootefi.c
View File

@ -189,7 +189,8 @@ static void efi_carve_out_dt_rsv(void *fdt)
if (nodeoffset >= 0) {
subnode = fdt_first_subnode(fdt, nodeoffset);
while (subnode >= 0) {
fdt_addr_t fdt_addr, fdt_size;
fdt_addr_t fdt_addr;
fdt_size_t fdt_size;
/* check if this subnode has a reg property */
fdt_addr = fdtdec_get_addr_size_auto_parent(

2
cmd/booti.c
View File

@ -141,7 +141,7 @@ static char booti_help_text[] =
"\tspecifying the size of a RAW initrd.\n"
"\tCurrently only booting from gz, bz2, lzma and lz4 compression\n"
"\ttypes are supported. In order to boot from any of these compressed\n"
"\timages, user have to set kernel_comp_addr_r and kernel_comp_size enviornment\n"
"\timages, user have to set kernel_comp_addr_r and kernel_comp_size environment\n"
"\tvariables beforehand.\n"
#if defined(CONFIG_OF_LIBFDT)
"\tSince booting a Linux kernel requires a flat device-tree, a\n"

4
cmd/mmc.c
View File

@ -8,6 +8,7 @@
#include <blk.h>
#include <command.h>
#include <console.h>
#include <memalign.h>
#include <mmc.h>
#include <part.h>
#include <sparse_format.h>
@ -56,7 +57,8 @@ static void print_mmcinfo(struct mmc *mmc)
if (!IS_SD(mmc) && mmc->version >= MMC_VERSION_4_41) {
bool has_enh = (mmc->part_support & ENHNCD_SUPPORT) != 0;
bool usr_enh = has_enh && (mmc->part_attr & EXT_CSD_ENH_USR);
u8 wp, ext_csd[MMC_MAX_BLOCK_LEN];
ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
u8 wp;
int ret;
#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)

2
common/splash.c
View File

@ -59,7 +59,7 @@ static struct splash_location default_splash_locations[] = {
static int splash_video_logo_load(void)
{
char *splashimage;
u32 bmp_load_addr;
ulong bmp_load_addr;
splashimage = env_get("splashimage");
if (!splashimage)

1
configs/malta64el_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_CPU_MIPS64_R2=y
CONFIG_MISC_INIT_R=y

1
configs/maltael_defconfig
View File

@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xBE000000
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_MALTA=y
CONFIG_BUILD_TARGET="u-boot-swap.bin"
CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_MISC_INIT_R=y
CONFIG_BOARD_EARLY_INIT_F=y

4
doc/board/sifive/fu540.rst
View File

@ -27,7 +27,7 @@ Building
--------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation enviornment variable:
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
@ -217,7 +217,7 @@ Or if you want to use a compressed kernel image file such as Image.gz
=>setenv kernel_comp_addr_r 0x90000000
=>setenv kernel_comp_size 0x500000
By this time, correct kernel image is loaded and required enviornment variables
By this time, correct kernel image is loaded and required environment variables
are set. You can proceed to load the ramdisk and device tree from the tftp server
as well.

2
doc/device-tree-bindings/net/phy/atheros.txt
View File

@ -23,7 +23,7 @@ Example:
ethernet-phy@0 {
reg = <0>;
qca-clk-out-frequency = <125000000>;
qca,clk-out-frequency = <125000000>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;

3
drivers/clk/rockchip/clk_rk3188.c
View File

@ -569,7 +569,8 @@ static int rk3188_clk_probe(struct udevice *dev)
rkclk_init(priv->cru, priv->grf, priv->has_bwadj);
/* Init CPU frequency */
rkclk_configure_cpu(priv->cru, priv->grf, APLL_HZ, priv->has_bwadj);
rkclk_configure_cpu(priv->cru, priv->grf, APLL_SAFE_HZ,
priv->has_bwadj);
#endif
return 0;

22
drivers/mmc/fsl_esdhc_imx.c
View File

@ -907,19 +907,9 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
ctrl = readl(&regs->autoc12err);
if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
(ctrl & MIX_CTRL_SMPCLK_SEL)) {
/*
* need to wait some time, make sure sd/mmc fininsh
* send out tuning data, otherwise, the sd/mmc can't
* response to any command when the card still out
* put the tuning data.
*/
mdelay(1);
ret = 0;
break;
}
/* Add 1ms delay for SD and eMMC */
mdelay(1);
}
writel(irqstaten, &regs->irqstaten);
@ -1267,6 +1257,18 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
val |= priv->tuning_start_tap;
val &= ~ESDHC_TUNING_STEP_MASK;
val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
/* Disable the CMD CRC check for tuning, if not, need to
* add some delay after every tuning command, because
* hardware standard tuning logic will directly go to next
* step once it detect the CMD CRC error, will not wait for
* the card side to finally send out the tuning data, trigger
* the buffer read ready interrupt immediately. If usdhc send
* the next tuning command some eMMC card will stuck, can't
* response, block the tuning procedure or the first command
* after the whole tuning procedure always can't get any response.
*/
val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
writel(val, &regs->tuning_ctrl);
}
}

9
drivers/mmc/mmc.c
View File

@ -669,12 +669,15 @@ static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
static int mmc_send_op_cond(struct mmc *mmc)
{
int err, i;
int timeout = 1000;
uint start;
/* Some cards seem to need this */
mmc_go_idle(mmc);
start = get_timer(0);
/* Asking to the card its capabilities */
for (i = 0; i < 2; i++) {
for (i = 0; ; i++) {
err = mmc_send_op_cond_iter(mmc, i != 0);
if (err)
return err;
@ -682,6 +685,10 @@ static int mmc_send_op_cond(struct mmc *mmc)
/* exit if not busy (flag seems to be inverted) */
if (mmc->ocr & OCR_BUSY)
break;
if (get_timer(start) > timeout)
return -ETIMEDOUT;
udelay(100);
}
mmc->op_cond_pending = 1;
return 0;

25
drivers/mmc/sdhci.c
View File

@ -567,6 +567,7 @@ static int sdhci_set_ios(struct mmc *mmc)
#endif
u32 ctrl;
struct sdhci_host *host = mmc->priv;
bool no_hispd_bit = false;
if (host->ops && host->ops->set_control_reg)
host->ops->set_control_reg(host);
@ -594,14 +595,26 @@ static int sdhci_set_ios(struct mmc *mmc)
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
ctrl &= ~SDHCI_CTRL_HISPD;
no_hispd_bit = true;
}
if (!no_hispd_bit) {
if (mmc->selected_mode == MMC_HS ||
mmc->selected_mode == SD_HS ||
mmc->selected_mode == MMC_DDR_52 ||
mmc->selected_mode == MMC_HS_200 ||
mmc->selected_mode == MMC_HS_400 ||
mmc->selected_mode == UHS_SDR25 ||
mmc->selected_mode == UHS_SDR50 ||
mmc->selected_mode == UHS_SDR104 ||
mmc->selected_mode == UHS_DDR50)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
}
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);

1
drivers/net/pcnet.c
View File

@ -8,6 +8,7 @@
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <log.h>
#include <dm.h>
#include <malloc.h>

3
drivers/nvme/nvme.c
View File

@ -466,6 +466,9 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,
c.identify.cns = cpu_to_le32(cns);
invalidate_dcache_range(dma_addr,
dma_addr + sizeof(struct nvme_id_ctrl));
ret = nvme_submit_admin_cmd(dev, &c, NULL);
if (!ret)
invalidate_dcache_range(dma_addr,

20
drivers/video/orisetech_otm8009a.c
View File

@ -62,9 +62,6 @@
struct otm8009a_panel_priv {
struct udevice *reg;
struct gpio_desc reset;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
unsigned long mode_flags;
};
static const struct display_timing default_timing = {
@ -293,17 +290,8 @@ static int otm8009a_panel_enable_backlight(struct udevice *dev)
static int otm8009a_panel_get_display_timing(struct udevice *dev,
struct display_timing *timings)
{
struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
struct mipi_dsi_device *device = plat->device;
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
memcpy(timings, &default_timing, sizeof(*timings));
/* fill characteristics of DSI data link */
device->lanes = priv->lanes;
device->format = priv->format;
device->mode_flags = priv->mode_flags;
return 0;
}
@ -335,6 +323,7 @@ static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
static int otm8009a_panel_probe(struct udevice *dev)
{
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
int ret;
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
@ -350,9 +339,10 @@ static int otm8009a_panel_probe(struct udevice *dev)
dm_gpio_set_value(&priv->reset, false);
mdelay(10); /* >5ms */
priv->lanes = 2;
priv->format = MIPI_DSI_FMT_RGB888;
priv->mode_flags = MIPI_DSI_MODE_VIDEO |
/* fill characteristics of DSI data link */
plat->lanes = 2;
plat->format = MIPI_DSI_FMT_RGB888;
plat->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM;

20
drivers/video/raydium-rm68200.c
View File

@ -75,9 +75,6 @@ struct rm68200_panel_priv {
struct udevice *reg;
struct udevice *backlight;
struct gpio_desc reset;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
unsigned long mode_flags;
};
static const struct display_timing default_timing = {
@ -259,17 +256,8 @@ static int rm68200_panel_enable_backlight(struct udevice *dev)
static int rm68200_panel_get_display_timing(struct udevice *dev,
struct display_timing *timings)
{
struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
struct mipi_dsi_device *device = plat->device;
struct rm68200_panel_priv *priv = dev_get_priv(dev);
memcpy(timings, &default_timing, sizeof(*timings));
/* fill characteristics of DSI data link */
device->lanes = priv->lanes;
device->format = priv->format;
device->mode_flags = priv->mode_flags;
return 0;
}
@ -308,6 +296,7 @@ static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
static int rm68200_panel_probe(struct udevice *dev)
{
struct rm68200_panel_priv *priv = dev_get_priv(dev);
struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
int ret;
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
@ -322,9 +311,10 @@ static int rm68200_panel_probe(struct udevice *dev)
dm_gpio_set_value(&priv->reset, false);
mdelay(10);
priv->lanes = 2;
priv->format = MIPI_DSI_FMT_RGB888;
priv->mode_flags = MIPI_DSI_MODE_VIDEO |
/* fill characteristics of DSI data link */
plat->lanes = 2;
plat->format = MIPI_DSI_FMT_RGB888;
plat->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM;

2
drivers/video/rockchip/Kconfig
View File

@ -22,7 +22,7 @@ menuconfig VIDEO_ROCKCHIP
config VIDEO_ROCKCHIP_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_ROCKCHIP
default 3480 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
default 3840 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI
default 1920
help
The maximum horizontal resolution to support for the framebuffer.

3
drivers/video/rockchip/rk_edp.c
View File

@ -1062,7 +1062,8 @@ static int rk_edp_probe(struct udevice *dev)
rk_setreg(&priv->grf->soc_con12, 1 << 4);
/* select epd signal from vop0 or vop1 */
rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
rk_clrsetreg(&priv->grf->soc_con6, (1 << 5),
(vop_id == 1) ? (1 << 5) : (0 << 5));
rockchip_edp_wait_hpd(priv);

13
drivers/video/stm32/stm32_dsi.c
View File

@ -271,7 +271,6 @@ static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
u32 val;
/* Update lane capabilities according to hw version */
dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
dsi->lane_min_kbps = LANE_MIN_KBPS;
dsi->lane_max_kbps = LANE_MAX_KBPS;
if (dsi->hw_version == HWVER_131) {
@ -354,6 +353,9 @@ static int stm32_dsi_attach(struct udevice *dev)
mplat = dev_get_platdata(priv->panel);
mplat->device = &priv->device;
device->lanes = mplat->lanes;
device->format = mplat->format;
device->mode_flags = mplat->mode_flags;
ret = panel_get_display_timing(priv->panel, &timings);
if (ret) {
@ -475,6 +477,15 @@ static int stm32_dsi_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
/* check hardware version */
priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION;
if (priv->hw_version != HWVER_130 &&
priv->hw_version != HWVER_131) {
dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version);
ret = -ENODEV;
goto err_clk;
}
return 0;
err_clk:
clk_disable(&clk);

1
drivers/video/vidconsole-uclass.c
View File

@ -623,6 +623,7 @@ void vidconsole_position_cursor(struct udevice *dev, unsigned col, unsigned row)
col *= priv->x_charsize;
row *= priv->y_charsize;
priv->xcur_frac = VID_TO_POS(min_t(short, col, vid_priv->xsize - 1));
priv->xstart_frac = priv->xcur_frac;
priv->ycur = min_t(short, row, vid_priv->ysize - 1);
}

27
drivers/video/video_bmp.c
View File

@ -233,6 +233,8 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
*/
if (bpix != bmp_bpix &&
!(bmp_bpix == 8 && bpix == 16) &&
!(bmp_bpix == 8 && bpix == 24) &&
!(bmp_bpix == 8 && bpix == 32) &&
!(bmp_bpix == 24 && bpix == 16) &&
!(bmp_bpix == 24 && bpix == 32)) {
printf("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
@ -265,6 +267,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
switch (bmp_bpix) {
case 1:
case 8: {
struct bmp_color_table_entry *cte;
cmap_base = priv->cmap;
#ifdef CONFIG_VIDEO_BMP_RLE8
u32 compression = get_unaligned_le32(&bmp->header.compression);
@ -280,21 +283,33 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
break;
}
#endif
if (bpix != 16)
byte_width = width * (bpix / 8);
if (!byte_width)
byte_width = width;
else
byte_width = width * 2;
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
for (j = 0; j < width; j++) {
if (bpix != 16) {
if (bpix == 8) {
fb_put_byte(&fb, &bmap);
} else {
} else if (bpix == 16) {
*(uint16_t *)fb = cmap_base[*bmap];
bmap++;
fb += sizeof(uint16_t) / sizeof(*fb);
} else {
/* Only support big endian */
cte = &palette[*bmap];
bmap++;
if (bpix == 24) {
*(fb++) = cte->red;
*(fb++) = cte->green;
*(fb++) = cte->blue;
} else {
*(fb++) = cte->blue;
*(fb++) = cte->green;
*(fb++) = cte->red;
*(fb++) = 0;
}
}
}
bmap += (padded_width - width);

1
include/configs/rk3399_common.h
View File

@ -67,6 +67,7 @@
"partitions=" PARTS_DEFAULT \
ROCKCHIP_DEVICE_SETTINGS \
BOOTENV \
BOOTENV_SF \
"altbootcmd=" \
"setenv boot_syslinux_conf extlinux/extlinux-rollback.conf;" \
"run distro_bootcmd\0"

3
include/fsl_esdhc_imx.h
View File

@ -203,7 +203,8 @@
#define ESDHC_STD_TUNING_EN BIT(24)
/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
#define ESDHC_TUNING_START_TAP_MASK 0xff
#define ESDHC_TUNING_START_TAP_MASK 0x7f
#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE BIT(7)
#define ESDHC_TUNING_STEP_MASK 0x00070000
#define ESDHC_TUNING_STEP_SHIFT 16

4
include/linux/psci.h
View File

@ -91,8 +91,8 @@
unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3);
#else
unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3)
static inline unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3)
{
return PSCI_RET_DISABLED;
}

6
include/mipi_dsi.h
View File

@ -221,9 +221,15 @@ static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt)
/**
* struct mipi_dsi_panel_plat - DSI panel platform data
* @device: DSI peripheral device
* @lanes: number of active data lanes
* @format: pixel format for video mode
* @mode_flags: DSI operation mode related flags
*/
struct mipi_dsi_panel_plat {
struct mipi_dsi_device *device;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
unsigned long mode_flags;
};
/**

2
include/zfs_common.h
View File

@ -22,6 +22,8 @@
#ifndef __ZFS_COMMON__
#define __ZFS_COMMON__
#include <part.h>
#define SECTOR_SIZE 0x200
#define SECTOR_BITS 9

14
lib/efi_loader/efi_variable.c
View File

@ -27,7 +27,7 @@ enum efi_secure_mode {
};
static bool efi_secure_boot;
static int efi_secure_mode;
static enum efi_secure_mode efi_secure_mode;
static u8 efi_vendor_keys;
#define READ_ONLY BIT(31)
@ -185,17 +185,17 @@ static const char *parse_attr(const char *str, u32 *attrp, u64 *timep)
/**
* efi_set_secure_state - modify secure boot state variables
* @sec_boot: value of SecureBoot
* @secure_boot: value of SecureBoot
* @setup_mode: value of SetupMode
* @audit_mode: value of AuditMode
* @deployed_mode: value of DeployedMode
*
* Modify secure boot stat-related variables as indicated.
* Modify secure boot status related variables as indicated.
*
* Return: status code
*/
static efi_status_t efi_set_secure_state(int sec_boot, int setup_mode,
int audit_mode, int deployed_mode)
static efi_status_t efi_set_secure_state(u8 secure_boot, u8 setup_mode,
u8 audit_mode, u8 deployed_mode)
{
u32 attributes;
efi_status_t ret;
@ -204,8 +204,8 @@ static efi_status_t efi_set_secure_state(int sec_boot, int setup_mode,
EFI_VARIABLE_RUNTIME_ACCESS |
READ_ONLY;
ret = efi_set_variable_common(L"SecureBoot", &efi_global_variable_guid,
attributes, sizeof(sec_boot), &sec_boot,
false);
attributes, sizeof(secure_boot),
&secure_boot, false);
if (ret != EFI_SUCCESS)
goto err;

55
tools/endian-swap.py Executable file
View File

@ -0,0 +1,55 @@
#!/usr/bin/env python3
# SPDX-License-Identifier: GPL-2.0+
"""
Simple tool to swap the byte endianness of a binary file.
"""
import argparse
import io
def parse_args():
"""Parse command line arguments."""
description = "Swap endianness of given input binary and write to output binary."
parser = argparse.ArgumentParser(description=description)
parser.add_argument("input_bin", type=str, help="input binary")
parser.add_argument("output_bin", type=str, help="output binary")
parser.add_argument("-c", action="store", dest="chunk_size", type=int,
default=io.DEFAULT_BUFFER_SIZE, help="chunk size for reading")
return parser.parse_args()
def swap_chunk(chunk_orig):
"""Swap byte endianness of the given chunk.
Returns:
swapped chunk
"""
chunk = bytearray(chunk_orig)
# align to 4 bytes and pad with 0x0
chunk_len = len(chunk)
pad_len = chunk_len % 4
if pad_len > 0:
chunk += b'\x00' * (4 - pad_len)
chunk[0::4], chunk[1::4], chunk[2::4], chunk[3::4] =\
chunk[3::4], chunk[2::4], chunk[1::4], chunk[0::4]
return chunk
def main():
args = parse_args()
with open(args.input_bin, "rb") as input_bin:
with open(args.output_bin, "wb") as output_bin:
while True:
chunk = bytearray(input_bin.read(args.chunk_size))
if not chunk:
break
output_bin.write(swap_chunk(chunk))
if __name__ == '__main__':
main()