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u-boot-brain
mirror of https://github.com/brain-hackers/u-boot-brain
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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi into next 

- Convert fsl_espi to driver model (Chuanhua)
- Enable am335x baltos to DM_SPI (Jagan)
- Drop few powerpc board which doesn't have DM enabled (Jagan)
This commit is contained in:
Tom Rini 2020-06-19 16:25:50 -04:00
parent 04909251fd 2a2b94a9d9
commit 5575f79bda
264 changed files with 893 additions and 26575 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Kconfig
View File

@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
ARCH_LS1046A)
ARCH_LS1046A || ARCH_QEMU)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,

1
MAINTAINERS
View File

@ -878,6 +878,7 @@ M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
F: cmd/rng.c
F: doc/api/rng.rst
F: drivers/rng/
F: drivers/virtio/virtio_rng.c
F: include/rng.h

1
arch/arm/Kconfig
View File

@ -1905,7 +1905,6 @@ source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/phytec/pcm051/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"

4
arch/arm/dts/ca-presidio-engboard.dts
View File

@ -10,11 +10,9 @@
#size-cells = <1>;
mmc0: mmc@f4400000 {
compatible = "snps,dw-cortina";
compatible = "cortina,ca-mmc";
reg = <0x0 0xf4400000 0x1000>;
bus-width = <4>;
io_ds = <0x77>;
fifo-mode;
sd_dll_ctrl = <0xf43200e8>;
io_drv_ctrl = <0xf432004c>;
};

4
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
View File

@ -68,3 +68,7 @@
&portc {
bank-name = "portc";
};
&i2c0 {
i2c-scl-falling-time-ns = <300>;
};

15
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
View File

@ -20,6 +20,21 @@
st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
};
};
led {
red {
label = "error";

14
arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
View File

@ -21,6 +21,20 @@
st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
reserved-memory {
optee@fe000000 {
reg = <0xfe000000 0x02000000>;
no-map;
};
};
led {
red {
label = "error";

5
arch/arm/dts/stm32mp157c-ed1.dts
View File

@ -70,11 +70,6 @@
reg = <0xe8000000 0x8000000>;
no-map;
};
optee@fe000000 {
reg = <0xfe000000 0x02000000>;
no-map;
};
};
aliases {

5
arch/arm/dts/stm32mp15xx-dkx.dtsi
View File

@ -58,11 +58,6 @@
reg = <0xd4000000 0x4000000>;
no-map;
};
optee@de000000 {
reg = <0xde000000 0x02000000>;
no-map;
};
};
led {

1
arch/arm/mach-omap2/omap3/Kconfig
View File

@ -181,7 +181,6 @@ source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"

14
arch/arm/mach-stm32mp/fdt.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
@ -224,19 +224,23 @@ static void stm32_fdt_disable_optee(void *blob)
{
int off, node;
/* Delete "optee" firmware node */
off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz");
if (off >= 0 && fdtdec_get_is_enabled(blob, off))
fdt_status_disabled(blob, off);
fdt_del_node(blob, off);
/* Disabled "optee@..." reserved-memory node */
/* Delete "optee@..." reserved-memory node */
off = fdt_path_offset(blob, "/reserved-memory/");
if (off < 0)
return;
for (node = fdt_first_subnode(blob, off);
node >= 0;
node = fdt_next_subnode(blob, node)) {
if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
fdt_status_disabled(blob, node);
if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6))
continue;
if (fdt_del_node(blob, node))
printf("Failed to remove optee reserved-memory node\n");
}
}

108
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -24,45 +24,6 @@ config TARGET_SOCRATES
bool "Support socrates"
select ARCH_MPC8544
config TARGET_B4420QDS
bool "Support B4420QDS"
select ARCH_B4420
select SUPPORT_SPL
select PHYS_64BIT
imply PANIC_HANG
config TARGET_B4860QDS
bool "Support B4860QDS"
select ARCH_B4860
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE if !SPL_BUILD
imply PANIC_HANG
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
select ARCH_BSC9131
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
select ARCH_BSC9132
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select FSL_DDR_INTERACTIVE
config TARGET_C29XPCIE
bool "Support C29XPCIE"
select ARCH_C29X
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
select PHYS_64BIT
imply PANIC_HANG
config TARGET_P3041DS
bool "Support P3041DS"
select PHYS_64BIT
@ -95,14 +56,6 @@ config TARGET_P5040DS
imply CMD_SATA
imply PANIC_HANG
config TARGET_MPC8536DS
bool "Support MPC8536DS"
select ARCH_MPC8536
# Use DDR3 controller with DDR2 DIMMs on this board
select SYS_FSL_DDRC_GEN3
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select ARCH_MPC8541
@ -156,14 +109,6 @@ config TARGET_P1010RDB_PB
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1022DS
bool "Support P1022DS"
select ARCH_P1022
select SUPPORT_SPL
select SUPPORT_TPL
imply CMD_SATA
imply FSL_SATA
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
@ -243,10 +188,6 @@ config TARGET_P2020RDB
imply CMD_SATA
imply SATA_SIL
config TARGET_P1_TWR
bool "Support p1_twr"
select ARCH_P1025
config TARGET_P2041RDB
bool "Support P2041RDB"
select ARCH_P2041
@ -260,16 +201,6 @@ config TARGET_QEMU_PPCE500
select ARCH_QEMU_E500
select PHYS_64BIT
config TARGET_T1024QDS
bool "Support T1024QDS"
select ARCH_T1024
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_EEPROM
imply CMD_SATA
imply FSL_SATA
config TARGET_T1023RDB
bool "Support T1023RDB"
select ARCH_T1023
@ -290,16 +221,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_T1040QDS
bool "Support T1040QDS"
select ARCH_T1040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_T1040RDB
bool "Support T1040RDB"
select ARCH_T1040
@ -371,15 +292,6 @@ config TARGET_T2081QDS
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
config TARGET_T4160QDS
bool "Support T4160QDS"
select ARCH_T4160
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
imply PANIC_HANG
config TARGET_T4160RDB
bool "Support T4160RDB"
select ARCH_T4160
@ -387,16 +299,6 @@ config TARGET_T4160RDB
select PHYS_64BIT
imply PANIC_HANG
config TARGET_T4240QDS
bool "Support T4240QDS"
select ARCH_T4240
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
imply CMD_SATA
imply PANIC_HANG
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
@ -1595,12 +1497,7 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8536ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
@ -1609,19 +1506,14 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"

14
board/freescale/b4860qds/Kconfig
View File

@ -1,14 +0,0 @@
if TARGET_B4860QDS || TARGET_B4420QDS
config SYS_BOARD
default "b4860qds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "B4860QDS"
source "board/freescale/common/Kconfig"
endif

17
board/freescale/b4860qds/MAINTAINERS
View File

@ -1,17 +0,0 @@
B4860QDS BOARD
M: Ashish Kumar <ashish.kumar@nxp.com>
S: Maintained
F: board/freescale/b4860qds/
F: include/configs/B4860QDS.h
F: configs/B4420QDS_defconfig
F: configs/B4420QDS_NAND_defconfig
F: configs/B4420QDS_SPIFLASH_defconfig
F: configs/B4860QDS_defconfig
F: configs/B4860QDS_NAND_defconfig
F: configs/B4860QDS_SPIFLASH_defconfig
F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
B4860QDS_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/B4860QDS_SECURE_BOOT_defconfig

16
board/freescale/b4860qds/Makefile
View File

@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2012 Freescale Semiconductor, Inc.
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += b4860qds.o
obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

1276
board/freescale/b4860qds/b4860qds.c
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File diff suppressed because it is too large Load Diff

12
board/freescale/b4860qds/b4860qds.h
View File

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#endif

72
board/freescale/b4860qds/b4860qds_crossbar_con.h
View File

@ -1,72 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*/
#ifndef __CROSSBAR_CONNECTIONS_H__
#define __CROSSBAR_CONNECTIONS_H__
#define NUM_CON_VSC3316 8
#define NUM_CON_VSC3308 4
static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {5, 14}, {4, 15},
{-1, -1}, {-1, -1} };
static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {5, 14},
{4, 15}, {2, 12}, {12, 13} };
#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 11}, {15, 10},
{-1, -1}, {-1, -1} };
static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 11},
{15, 10}, {13, 3}, {12, 12} };
#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
#endif

28
board/freescale/b4860qds/b4860qds_qixis.h
View File

@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*/
#ifndef __B4860QDS_QIXIS_H__
#define __B4860QDS_QIXIS_H__
/* Definitions of QIXIS Registers for B4860QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
/* CLK */
#define QIXIS_CLK_66 0x0
#define QIXIS_CLK_100 0x1
#define QIXIS_CLK_125 0x2
#define QIXIS_CLK_133 0x3
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
/* SGMII */
#define PHY_BASE_ADDR 0x18
#define PORT_NUM 0x04
#define REGNUM 0x00
#endif

30
board/freescale/b4860qds/b4_pbi.cfg
View File

@ -1,30 +0,0 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 512KB SRAM
09010100 00000000
09010104 fff80009
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#slowing down the MDC clock to make it <= 2.5 MHZ
094fc030 00008148
094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000

7
board/freescale/b4860qds/b4_rcw.cfg
View File

@ -1,7 +0,0 @@
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x2A_0x98
140e0018 0f001218 00000000 00000000
54980000 9000a000 e8104000 a9000000
01000000 00000000 00000000 0001b1f8
00000000 14000020 00000000 00000011

267
board/freescale/b4860qds/ddr.c
View File

@ -1,267 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <fsl_ddr.h>
#include <init.h>
#include <log.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
.rank_density = 2147483648u,
.capacity = 4294967296u,
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.registered_dimm = 0,
.mirrored_dimm = 1,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2, /* ECC */
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1071,
.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
.taa_ps = 13910,
.twr_ps = 15000,
.trcd_ps = 13910,
.trrd_ps = 6000,
.trp_ps = 13910,
.tras_ps = 34000,
.trc_ps = 48910,
.trfc_ps = 260000,
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 7800000,
.tfaw_ps = 35000,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "RAW timing DDR";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
{2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
{2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
{1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
{1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
{1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x3e;
}
int dram_init(void)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
gd->ram_size = dram_size;
return 0;
}
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
unsigned int dbw_cap_adj[])
{
int i, j;
unsigned long long total_mem, current_mem_base, total_ctlr_mem;
unsigned long long rank_density, ctlr_density = 0;
current_mem_base = 0ull;
total_mem = 0;
/*
* This board has soldered DDR chips. DDRC1 has two rank.
* DDRC2 has only one rank.
* Assigning DDRC2 to lower address and DDRC1 to higher address.
*/
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
dbw_cap_adj[0];
ctlr_density = rank_density;
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
total_ctlr_mem = 2 * ctlr_density;
break;
default:
panic("Unknown interleaving mode");
}
pinfo->common_timing_params[i].base_address =
current_mem_base;
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem = current_mem_base + total_ctlr_mem;
debug("ctrl %d base 0x%llx\n", i, current_mem_base);
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
}
} else {
/*
* Simple linear assignment if memory
* controllers are not interleaved.
*/
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* Compute DIMM base addresses. */
unsigned long long cap =
pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address =
current_mem_base;
debug("ctrl %d dimm %d base 0x%llx\n",
i, j, current_mem_base);
current_mem_base += cap;
total_ctlr_mem += cap;
}
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem += total_ctlr_mem;
}
}
debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
return total_mem;
}

454
board/freescale/b4860qds/eth_b4860qds.c
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@ -1,454 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Author: Sandeep Kumar Singh <sandeep@freescale.com>
*/
/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
/*
* This file handles the board muxing between the Fman Ethernet MACs and
* the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
* PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
* The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
* one Fman device on B4860. The SERDES configuration is used to determine
* where the SGMII and XAUI cards exist, and also which Fman MACs are routed
* to which PHYs. So for a given Fman MAC, there is one and only PHY it
* connects to. MACs cannot be routed to PHYs dynamically. This configuration
* is done at boot time by reading SERDES protocol from RCW.
*/
#include <common.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#include "../common/qixis.h"
#include "b4860qds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#ifdef CONFIG_FMAN_ENET
/*
* Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
* lane at index is mapped to slot number n. A value of '0' will mean
* that the mapping must be determined dynamically, or that the lane maps to
* something other than a board slot
*/
static u8 lane_to_slot[] = {
0, 0, 0, 0,
0, 0, 0, 0,
1, 1, 1, 1,
0, 0, 0, 0
};
/*
* This function initializes the lane_to_slot[] array. It reads RCW to check
* if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
* lane_to_slot[] accordingly
*/
static void initialize_lane_to_slot(void)
{
unsigned int serdes2_prtcl;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
debug("Initializing lane to slot: Serdes2 protocol: %x\n",
serdes2_prtcl);
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: SGMII
* Lanes: E,F: Aur
* Lanes: G,H: SRIO
*/
case 0x91:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: SGMII
* Lanes: C,D: SRIO2
* Lanes: E,F,G,H: XAUI2
*/
case 0x93:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: SGMII
* Lanes: E,F,G,H: XAUI2
*/
case 0x98:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: XAUI2
* Lanes: E,F,G,H: XAUI2
*/
case 0x9a:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: PCI
* Lanes: C,D: SGMII
* Lanes: E,F,G,H: XAUI2
*/
case 0x9e:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: PCI
* Lanes: E,F: SGMII 3&4
* Lanes: G,H: XFI
*/
case 0xc2:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: SGMII
* Lanes: C,D: SRIO2
* Lanes: E,F,G,H: XAUI2
*/
lane_to_slot[12] = 2;
lane_to_slot[13] = lane_to_slot[12];
lane_to_slot[14] = lane_to_slot[12];
lane_to_slot[15] = lane_to_slot[12];
break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
return;
}
#endif /* #ifdef CONFIG_FMAN_ENET */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
struct memac_mdio_info tg_memac_mdio_info;
unsigned int i;
unsigned int serdes1_prtcl, serdes2_prtcl;
int qsgmii;
struct mii_dev *bus;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
if (!serdes1_prtcl) {
printf("SERDES1 is not enabled\n");
return 0;
}
serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
if (!serdes2_prtcl) {
printf("SERDES2 is not enabled\n");
return 0;
}
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
printf("Initializing Fman\n");
initialize_lane_to_slot();
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
tg_memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_memac_mdio_init(bis, &tg_memac_mdio_info);
/*
* Program the two on board DTSEC PHY addresses assuming that they are
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_ARCH_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
break;
case 0x48:
case 0x49:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
/*
* XFI does not need a PHY to work, but to make U-Boot
* happy, assign a fake PHY address for a XFI port.
*/
fm_info_set_phy_address(FM1_10GEC1, 0);
fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
/*set PHY address for QSGMII Riser Card on slot2*/
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
if (qsgmii) {
switch (serdes2_prtcl) {
case 0xb2:
case 0x8d:
fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
break;
default:
break;
}
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name
(DEFAULT_FM_TGEC_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
int phy;
char alias[32];
struct fixed_link f_link;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, alias);
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* check if it's XFI interface for 10g */
switch (prtcl2) {
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
break;
case 0x98: /* XAUI interface */
strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x9e: /* XAUI interface */
case 0x9a:
case 0x93:
case 0x91:
strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x97: /* XAUI interface */
case 0xc3:
strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
default:
break;
}
}
}
/*
* Set status to disabled for unused ethernet node
*/
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);
fdt_status_disabled_by_alias(fdt, alias);
break;
default:
break;
}
}
}

28
board/freescale/b4860qds/law.c
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@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

23
board/freescale/b4860qds/pci.c
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@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

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board/freescale/b4860qds/spl.c
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// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <console.h>
#include <env.h>
#include <env_internal.h>
#include <init.h>
#include <asm/spl.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include "../common/qixis.h"
#include "b4860qds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch ((sysclk_conf & 0x0C) >> 2) {
case QIXIS_CLK_100:
return 100000000;
case QIXIS_CLK_125:
return 125000000;
case QIXIS_CLK_133:
return 133333333;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch (ddrclk_conf & 0x03) {
case QIXIS_CLK_100:
return 100000000;
case QIXIS_CLK_125:
return 125000000;
case QIXIS_CLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, uart_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("" : : : "memory");
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
uart_clk / 16 / CONFIG_BAUDRATE);
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
env_relocate();
#else
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
gd->env_addr = (ulong)(SPL_ENV_ADDR);
gd->env_valid = ENV_VALID;
#endif
i2c_init_all();
puts("\n\n");
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
nand_boot();
#endif
}

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
/* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_32M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/*
* *I*G - NAND
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_64K, 1),
#endif
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 12, BOOKE_PAGESZ_4K, 1),
/*
* *I*G - SRIO
* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so we use entry 16 for SRIO2.
*/
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
/* *I*G* - SRIO1 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 13, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
/* *I*G* - SRIO2 */
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 16, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/*
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 17, BOOKE_PAGESZ_2G, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

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board/freescale/bsc9131rdb/Kconfig
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@ -1,12 +0,0 @@
if TARGET_BSC9131RDB
config SYS_BOARD
default "bsc9131rdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "BSC9131RDB"
endif

9
board/freescale/bsc9131rdb/MAINTAINERS
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@ -1,9 +0,0 @@
BSC9131RDB BOARD
M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
S: Maintained
F: board/freescale/bsc9131rdb/
F: include/configs/BSC9131RDB.h
F: configs/BSC9131RDB_NAND_defconfig
F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig
F: configs/BSC9131RDB_SPIFLASH_defconfig
F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig

21
board/freescale/bsc9131rdb/Makefile
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@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2011-2012 Freescale Semiconductor, Inc.
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o
else
obj-y += bsc9131rdb.o
obj-y += ddr.o
endif
obj-y += law.o
obj-y += tlb.o

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Overview
--------
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- It's MAPLE disabled personality is called 9231.
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The e500 core subsystem within the Power Architecture consists of the following:
. 32-Kbyte L1 instruction cache
. 32-Kbyte L1 data cache
. 256-Kbyte L2 cache/L2 memory/L2 stash
. programmable interrupt controller (PIC)
. Debug support
. Timers
The SC3850 core subsystem consists of the following:
. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
. 32 Kbyte 8-way level 1 data cache (L1 DCache)
. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
. Memory management unit (MMU)
. Enhanced programmable interrupt controller (EPIC)
. Debug and profiling unit (DPU)
. Two 32-bit timers
BSC9131RDB board Overview
-------------------------
1Gbyte DDR3 (on board DDR)
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
USB-ULPI
eTSEC1: Connected to RGMII PHY
eTSEC2: Connected to RGMII PHY
DUART interface: supports one UARTs up to 115200 bps for console display
USIM connector
Frequency Combinations Supported
--------------------------------
Core MHz/CCB MHz/DDR(MT/s)
1. 1000/500/800
2. 800/400/667
Boot Methods Supported
-----------------------
1. NAND Flash
2. SPI Flash
Default Boot Method
--------------------
NAND boot
Building U-Boot
--------------
To build the U-Boot for BSC9131RDB:
1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
make BSC9131RDB_NAND
2. NAND Flash with sysclk 100MHz(J16 on RDB open)
make BSC9131RDB_NAND_SYSCLK100
3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
make BSC9131RDB_SPIFLASH
4. SPI Flash with sysclk 100MHz(J16 on RDB open)
make BSC9131RDB_SPIFLASH_SYSCLK100
Memory map
-----------
0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
DDR Memory map
---------------
0x0000_0000 0x36FF_FFFF Memory passed onto Linux
0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
0x3800_0000 0x4FFF_FFFF DSP Private area
Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
data communcation between PowerPC and DSP core.
Rest is PowerPC private area.
Flashing Images
---------------
To place a new U-Boot image in the NAND flash and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot-nand.bin
nand erase 0 100000
nand write 1000000 0 100000
reset
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 bsc9131rdb.dtb
bootm 1000000 2000000 c00000

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <image.h>
#include <init.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <flash.h>
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
MPC85xx_PMUXCR_IFC_AD_GPIO |
MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
return 0;
}
int checkboard(void)
{
struct cpu_type *cpu;
cpu = gd->arch.cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static const struct node_info nodes[] = {
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
#endif

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <vsprintf.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{0, 0, NULL}
};
unsigned long get_sdram_size(void)
{
return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
}
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0) {
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
}
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
return ddr_size;
}
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/* Micron MT41J256M8HX-15E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 1073741824u,
.capacity = 1073741824u,
.primary_sdram_width = 32,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1870,
.caslat_x = 0x1e << 4, /* 5,6,7,8 */
.taa_ps = 13125,
.twr_ps = 15000,
.trcd_ps = 13125,
.trrd_ps = 7500,
.trp_ps = 13125,
.tras_ps = 37500,
.trc_ps = 50625,
.trfc_ps = 160000,
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */

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board/freescale/bsc9131rdb/law.c
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@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_DSP_CCSR),
SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
LAW_TRGT_IF_OCN_DSP),
};
int num_law_entries = ARRAY_SIZE(law_table);

105
board/freescale/bsc9131rdb/spl_minimal.c
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@ -1,105 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
static void sdram_init(void)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
#endif
__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
/* Set, but do not enable the memory */
__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
asm volatile("sync;isync");
udelay(500);
/* Let the controller go */
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* Initialize the DDR3 */
sdram_init();
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

61
board/freescale/bsc9131rdb/tlb.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* CCSRBAR (DSP) */
SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1M, 1)
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

14
board/freescale/bsc9132qds/Kconfig
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@ -1,14 +0,0 @@
if TARGET_BSC9132QDS
config SYS_BOARD
default "bsc9132qds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "BSC9132QDS"
source "board/freescale/common/Kconfig"
endif

25
board/freescale/bsc9132qds/MAINTAINERS
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@ -1,25 +0,0 @@
BSC9132QDS BOARD
M: Naveen Burmi <naveen.burmi@nxp.com>
S: Maintained
F: board/freescale/bsc9132qds/
F: include/configs/BSC9132QDS.h
F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig
F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig
F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig
F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig
F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
BSC9132QDS_NAND_DDRCLK100_SECURE BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig

21
board/freescale/bsc9132qds/Makefile
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@ -1,21 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Freescale Semiconductor, Inc.
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o
else
obj-y += bsc9132qds.o
obj-y += ddr.o
endif
obj-y += law.o
obj-y += tlb.o

150
board/freescale/bsc9132qds/README
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@ -1,150 +0,0 @@
Overview
--------
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
The SC3850 core subsystem consists of the following:
- 32 KB, 8-way, level 1 instruction cache (L1 ICache)
- 32 KB, 8-way, level 1 data cache (L1 DCache)
- 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
- Memory management unit (MMU)
- Global interrupt controller ( GIC)
- Debug and profiling unit (DPU)
- Two 32-bit quad timers
BSC9132QDS board Overview
-------------------------
2Gbyte DDR3 (on board DDR), Dual Ranki
32Mbyte 16bit NOR flash
128Mbyte 2K page size NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
SD slot
USB-ULPI
eTSEC1: Connected to SGMII PHY
eTSEC2: Connected to SGMII PHY
PCIe
CPRI
SerDes
I2C RTC
DUART interface: supports one UARTs up to 115200 bps for console display
Frequency Combinations Supported
--------------------------------
Core MHz/CCB MHz/DDR(MT/s)
1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
(SYSCLK = 100MHz, DDRCLK = 100MHz)
2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
(SYSCLK = 100MHz, DDRCLK = 133MHz)
Boot Methods Supported
-----------------------
1. NOR Flash
2. NAND Flash
3. SD Card
4. SPI flash
Default Boot Method
--------------------
NOR boot
Building U-Boot
--------------
To build the U-Boot for BSC9132QDS:
1. NOR Flash
make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
2. NAND Flash : It is currently not supported
3. SPI Flash
make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
4. SD Card
make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
Memory map
-----------
0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
0x8000_0000 0x8FFF_FFFF NOR Flash 256M
0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
0xC000_0000 0xC000_7FFF M3 Memory 32K
0xC001_0000 0xC001_FFFF PCI Express I/O 64K
0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
Flashing Images
---------------
To place a new U-Boot image in the NAND flash and then boot
with that new image temporarily, use this:
tftp 1000000 u-boot-nand.bin
nand erase 0 100000
nand write 1000000 0 100000
reset
Using the Device Tree Source File
---------------------------------
To create the DTB (Device Tree Binary) image file,
use a command similar to this:
dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
Likely, that .dts file will come from here;
linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
Booting Linux
-------------
Place a linux uImage in the TFTP disk area.
tftp 1000000 uImage
tftp 2000000 rootfs.ext2.gz.uboot
tftp c00000 bsc9132qds.dtb
bootm 1000000 2000000 c00000

432
board/freescale/bsc9132qds/bsc9132qds.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <fsl_ddr_sdram.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <flash.h>
#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/fsl_pci.h>
#endif
#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
return 0;
}
void board_config_serdes_mux(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
switch (srds_cfg) {
/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
case 1:
case 2:
case 3:
case 4:
case 5:
case 22:
case 23:
case 24:
case 25:
case 26:
QIXIS_WRITE_I2C(brdcfg[4], 0x03);
break;
/* PEX(1) PEX(2) SGMII1 CPRI 1 */
case 6:
case 7:
case 8:
case 9:
case 10:
case 27:
case 28:
case 29:
case 30:
case 31:
QIXIS_WRITE_I2C(brdcfg[4], 0x01);
break;
/* PEX(1) PEX(2) SGMII1 SGMII2 */
case 11:
case 32:
QIXIS_WRITE_I2C(brdcfg[4], 0x00);
break;
/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
case 12:
case 13:
case 14:
case 15:
case 16:
case 33:
case 34:
case 35:
case 36:
case 37:
QIXIS_WRITE_I2C(brdcfg[4], 0x07);
break;
/* PEX(1) SGMII2 SGMII1 CPRI 1 */
case 17:
case 18:
case 19:
case 20:
case 21:
case 38:
case 39:
case 40:
case 41:
case 42:
QIXIS_WRITE_I2C(brdcfg[4], 0x05);
break;
/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
case 43:
case 44:
case 45:
case 46:
case 47:
QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
break;
default:
break;
}
}
/* Configure DSP DDR controller */
void dsp_ddr_configure(void)
{
/*
*There are separate DDR-controllers for DSP and PowerPC side DDR.
*copy the ddr controller settings from PowerPC side DDR controller
*to the DSP DDR controller as connected DDR memories are similar.
*/
struct ccsr_ddr __iomem *pa_ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr temp_ddr;
struct ccsr_ddr __iomem *dsp_ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}
int board_early_init_r(void)
{
#ifdef CONFIG_MTD_NOR_FLASH
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_64M, 1);
set_tlb(1, flashbase + 0x4000000,
CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
#endif
board_config_serdes_mux();
dsp_ddr_configure();
return 0;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */
int checkboard(void)
{
struct cpu_type *cpu;
u8 sw;
cpu = gd->arch.cpu;
printf("Board: %sQDS\n", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
printf("IFC chip select:");
switch (sw) {
case 0:
printf("NOR\n");
break;
case 2:
printf("Promjet\n");
break;
case 4:
printf("NAND\n");
break;
default:
printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
break;
}
return 0;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
#ifdef CONFIG_PCI
pci_eth_init(bis);
#endif
return 0;
}
#define USBMUX_SEL_MASK 0xc0
#define USBMUX_SEL_UART2 0xc0
#define USBMUX_SEL_USB 0x40
#define SPIMUX_SEL_UART3 0x80
#define GPS_MUX_SEL_GPS 0x40
#define TSEC_1588_CLKIN_MASK 0x03
#define CON_XCVR_REF_CLK 0x00
int misc_init_r(void)
{
u8 val;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 porbmsr = in_be32(&gur->porbmsr);
u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
/*Configure 1588 clock-in source from RF Card*/
val = QIXIS_READ_I2C(brdcfg[5]);
QIXIS_WRITE_I2C(brdcfg[5],
(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
if (hwconfig("uart2") && hwconfig("usb1")) {
printf("UART2 and USB cannot work together on the board\n");
printf("Remove one from hwconfig and reset\n");
} else {
if (hwconfig("uart2")) {
val = QIXIS_READ_I2C(brdcfg[5]);
QIXIS_WRITE_I2C(brdcfg[5],
(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
clrbits_be32(&gur->pmuxcr3,
MPC85xx_PMUXCR3_USB_SEL_MASK);
setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
} else {
/* By default USB should be selected.
* Programming FPGA to select USB. */
val = QIXIS_READ_I2C(brdcfg[5]);
QIXIS_WRITE_I2C(brdcfg[5],
(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
}
}
if (hwconfig("sim")) {
if (romloc == PORBMSR_ROMLOC_NAND_2K ||
romloc == PORBMSR_ROMLOC_NOR ||
romloc == PORBMSR_ROMLOC_SPI) {
val = QIXIS_READ_I2C(brdcfg[3]);
QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
clrbits_be32(&gur->pmuxcr,
MPC85xx_PMUXCR0_SIM_SEL_MASK);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
}
}
if (hwconfig("uart3")) {
if (romloc == PORBMSR_ROMLOC_NAND_2K ||
romloc == PORBMSR_ROMLOC_NOR ||
romloc == PORBMSR_ROMLOC_SDHC) {
/* UART3 and SPI1 (Flashes) are muxed together */
val = QIXIS_READ_I2C(brdcfg[3]);
QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
clrbits_be32(&gur->pmuxcr3,
MPC85xx_PMUXCR3_UART3_SEL_MASK);
setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
/* MUX to select UART3 connection to J24 header
* or to GPS */
val = QIXIS_READ_I2C(brdcfg[6]);
if (hwconfig("gps"))
QIXIS_WRITE_I2C(brdcfg[6],
(val | GPS_MUX_SEL_GPS));
else
QIXIS_WRITE_I2C(brdcfg[6],
(val & ~(GPS_MUX_SEL_GPS)));
}
}
return 0;
}
void fdt_del_node_compat(void *blob, const char *compatible)
{
int err;
int off = fdt_node_offset_by_compatible(blob, -1, compatible);
if (off < 0) {
printf("WARNING: could not find compatible node %s: %s.\n",
compatible, fdt_strerror(off));
return;
}
err = fdt_del_node(blob, off);
if (err < 0) {
printf("WARNING: could not remove %s: %s.\n",
compatible, fdt_strerror(err));
}
}
#if defined(CONFIG_OF_BOARD_SETUP)
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static const struct node_info nodes[] = {
{ "cfi-flash", MTD_DEV_TYPE_NOR, },
{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
};
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
#if defined(CONFIG_PCI)
FT_FSL_PCI_SETUP;
#endif
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 porbmsr = in_be32(&gur->porbmsr);
u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
if (!(hwconfig("uart2") && hwconfig("usb1"))) {
/* If uart2 is there in hwconfig remove usb node from
* device tree */
if (hwconfig("uart2")) {
/* remove dts usb node */
fdt_del_node_compat(blob, "fsl-usb2-dr");
} else {
fsl_fdt_fixup_dr_usb(blob, bd);
fdt_del_node_and_alias(blob, "serial2");
}
}
if (hwconfig("uart3")) {
if (romloc == PORBMSR_ROMLOC_NAND_2K ||
romloc == PORBMSR_ROMLOC_NOR ||
romloc == PORBMSR_ROMLOC_SDHC)
/* Delete SPI node from the device tree */
fdt_del_node_and_alias(blob, "spi1");
} else
fdt_del_node_and_alias(blob, "serial3");
if (hwconfig("sim")) {
if (romloc == PORBMSR_ROMLOC_NAND_2K ||
romloc == PORBMSR_ROMLOC_NOR ||
romloc == PORBMSR_ROMLOC_SPI) {
/* remove dts sdhc node */
fdt_del_node_compat(blob, "fsl,esdhc");
} else if (romloc == PORBMSR_ROMLOC_SDHC) {
/* remove dts sim node */
fdt_del_node_compat(blob, "fsl,sim-v1.0");
printf("SIM & SDHC can't work together on the board");
printf("\nRemove sim from hwconfig and reset\n");
}
}
return 0;
}
#endif

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board/freescale/bsc9132qds/ddr.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <vsprintf.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#ifndef CONFIG_SYS_DDR_RAW_TIMING
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
.ddr_data_init = CONFIG_MEM_INIT_VALUE,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{750, 850, &ddr_cfg_regs_800},
{1060, 1333, &ddr_cfg_regs_1333},
{0, 0, NULL}
};
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram(void)
{
int i;
char buf[32];
fsl_ddr_cfg_regs_t ddr_cfg_regs;
phys_size_t ddr_size;
ulong ddr_freq, ddr_freq_mhz;
ddr_freq = get_ddr_freq(0);
ddr_freq_mhz = ddr_freq / 1000000;
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, ddr_freq));
for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
sizeof(ddr_cfg_regs));
break;
}
}
if (fixed_ddr_parm_0[i].max_freq == 0)
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
}
return ddr_size;
}
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/* Micron MT41J512M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 1073741824u,
.capacity = 1073741824u,
.primary_sdram_width = 32,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1870,
.caslat_x = 0x1e << 4, /* 5,6,7,8 */
.taa_ps = 13125,
.twr_ps = 15000,
.trcd_ps = 13125,
.trrd_ps = 7500,
.trp_ps = 13125,
.tras_ps = 37500,
.trc_ps = 50625,
.trfc_ps = 160000,
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */

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board/freescale/bsc9132qds/law.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_FPGA_BASE_PHYS
SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
#endif
SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_DSP_CCSR),
SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
LAW_TRGT_IF_OCN_DSP),
SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
LAW_TRGT_IF_CLASS_DSP),
SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
LAW_TRGT_IF_CLASS_DSP)
};
int num_law_entries = ARRAY_SIZE(law_table);

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board/freescale/bsc9132qds/spl_minimal.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
struct ccsr_ddr __iomem *ddr =
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
__raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
__raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
#elif CONFIG_DDR_CLK_FREQ == 133000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
__raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg);
__raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2);
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
__raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3);
__raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0);
__raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1);
__raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2);
__raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode);
__raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2);
__raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval);
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl);
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl);
__raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4);
__raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5);
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
#else
puts("Not a valid DDR Freq Found! Please Reset\n");
#endif
asm volatile("sync;isync");
udelay(500);
/* Let the controller go */
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* Initialize the DDR3 */
sdram_init();
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

91
board/freescale/bsc9132qds/tlb.c
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@ -1,91 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR (PA) */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* CCSRBAR (DSP) */
SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 3, BOOKE_PAGESZ_64M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
#ifdef CONFIG_PCI
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_64K, 1),
#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_SYS_FPGA_BASE
/* *I*G - Board FPGA */
SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_256K, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

14
board/freescale/c29xpcie/Kconfig
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@ -1,14 +0,0 @@
if TARGET_C29XPCIE
config SYS_BOARD
default "c29xpcie"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "C29XPCIE"
source "board/freescale/common/Kconfig"
endif

10
board/freescale/c29xpcie/MAINTAINERS
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@ -1,10 +0,0 @@
C29XPCIE BOARD
M: Po Liu <po.liu@nxp.com>
S: Maintained
F: board/freescale/c29xpcie/
F: include/configs/C29XPCIE.h
F: configs/C29XPCIE_defconfig
F: configs/C29XPCIE_NAND_defconfig
F: configs/C29XPCIE_SPIFLASH_defconfig
F: configs/C29XPCIE_NOR_SECBOOT_defconfig
F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig

25
board/freescale/c29xpcie/Makefile
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@ -1,25 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Freescale Semiconductor, Inc.
#
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
obj-y += c29xpcie.o
obj-y += cpld.o
obj-y += ddr.o
endif
obj-y += law.o
obj-y += tlb.o

99
board/freescale/c29xpcie/README
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@ -1,99 +0,0 @@
Overview
=========
C29XPCIE board is a series of Freescale PCIe add-in cards to perform
as public key crypto accelerator or secure key management module.
It includes C293PCIE board, C293PCIE board and C291PCIE board.
The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engines.
(maximum core frequency 1000/1200 MHz).
The C29xPCIE board features are as follows:
Memory subsystem:
- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
- 64 Mbyte NOR flash single-chip memory
- 4 Gbyte NAND flash memory
- 1 Mbit AT24C1024 I2C EEPROM
- 16 Mbyte SPI memory
Interfaces:
- 10/100/1000 BaseT Ethernet ports:
- eTSEC1, RGMII: one 10/100/1000 port
- eTSEC2, RGMII: one 10/100/1000 port
- DUART interface:
- DUART interface: supports two UARTs up to 115200 bps for
console display
Board connectors:
- Mini-ITX power supply connector
- JTAG/COP for debugging
Physical Memory Map on C29xPCIE
===============================
Address Start Address End Memory type
0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
Serial Port Configuration on C29xPCIE
=====================================
Configure the serial port of the attached computer with the following values:
-Data rate: 115200 bps
-Number of data bits: 8
-Parity: None
-Number of Stop bits: 1
-Flow Control: Hardware/None
Settings of DIP-switch
======================
SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
Note: 1 stands for 'off', 0 stands for 'on'
Build and program U-Boot to NOR flash
==================================
1. Build u-boot.bin image example:
export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
make C293PCIE
2. Program u-boot.bin into NOR flash
=> tftp $loadaddr $uboot
=> protect off eff40000 +$filesize
=> erase eff40000 +$filesize
=> cp.b $loadaddr eff40000 $filesize
3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
Alternate NOR bank
==================
There are four banks in C29XPCIE board, example to change bank booting:
1. Program u-boot.bin into alternate NOR bank
=> tftp $loadaddr $uboot
=> protect off e9f40000 +$filesize
=> erase e9f40000 +$filesize
=> cp.b $loadaddr e9f40000 $filesize
2. Switch to alternate NOR bank
=> cpld_cmd reset altbank [bank]
- [bank] bank value select 1-4
- bank 1 on the flash 0x0000000~0x0ffffff
- bank 2 on the flash 0x1000000~0x1ffffff
- bank 3 on the flash 0x2000000~0x2ffffff
- bank 4 on the flash 0x3000000~0x3ffffff
or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
Build and program U-Boot to SPI flash
==================================
1. Build u-boot-spi.bin image
make C29xPCIE_SPIFLASH_config; make
Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
2. Program u-boot-spi.bin into SPI flash
=> tftp $loadaddr $uboot-spi
=> sf erase 0 100000
=> sf write $loadaddr 0 $filesize
3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.

159
board/freescale/c29xpcie/c29xpcie.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <env.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
printf("Board: %sPCIe, ", cpu->name);
printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
return 0;
}
int board_early_init_f(void)
{
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Clock configuration to access CPLD using IFC(GPCM) */
setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
return 0;
}
int board_early_init_r(void)
{
const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_64M, 1);
return 0;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
/* Register 1G MDIO bus */
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_sec(void *blob, int offset)
{
int nodeoff = 0;
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
struct cpu_type *cpu;
cpu = gd->arch.cpu;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
#if defined(CONFIG_PCI)
FT_FSL_PCI_SETUP;
#endif
fdt_fixup_memory(blob, (u64)base, (u64)size);
if (cpu->soc_ver == SVR_C291)
fdt_del_sec(blob, 1);
else if (cpu->soc_ver == SVR_C292)
fdt_del_sec(blob, 2);
return 0;
}
#endif

133
board/freescale/c29xpcie/cpld.c
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// SPDX-License-Identifier: GPL-2.0+
/**
* Copyright 2013 Freescale Semiconductor
* Author: Mingkai Hu <Mingkai.hu@freescale.com>
* Po Liu <Po.Liu@freescale.com>
*
* This file provides support for the board-specific CPLD used on some Freescale
* reference boards.
*
* The following macros need to be defined:
*
* CONFIG_SYS_CPLD_BASE - The virtual address of the base of the
* CPLD register map
*
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "cpld.h"
/**
* Set the boot bank to the alternate bank
*/
void cpld_set_altbank(u8 banksel)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
u8 reg11;
reg11 = in_8(&cpld_data->flhcsr);
switch (banksel) {
case 1:
out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);
break;
case 2:
out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);
break;
case 3:
out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);
break;
case 4:
out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK)
| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);
break;
default:
printf("Invalid value! [1-4]\n");
return;
}
udelay(100);
do_reset(NULL, 0, 0, NULL);
}
/**
* Set the boot bank to the default bank
*/
void cpld_set_defbank(void)
{
cpld_set_altbank(4);
}
#ifdef DEBUG
static void cpld_dump_regs(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1));
printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2));
printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver));
printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver));
printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon));
printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr));
printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr));
printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick));
printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr));
printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr));
printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr));
printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor));
printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1));
printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2));
printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3));
printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4));
putc('\n');
}
#endif
#ifndef CONFIG_SPL_BUILD
int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int rc = 0;
unsigned char value;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (!strcmp(argv[2], "altbank") && argv[3]) {
value = (u8)simple_strtoul(argv[3], NULL, 16);
cpld_set_altbank(value);
} else if (!argv[2])
cpld_set_defbank();
else
cmd_usage(cmdtp);
#ifdef DEBUG
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
#endif
} else
rc = cmd_usage(cmdtp);
return rc;
}
U_BOOT_CMD(
cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
"Reset the board using the CPLD sequencer",
"reset - hard reset to default bank 4\n"
"cpld_cmd reset altbank [bank]- reset to alternate bank\n"
" - [bank] bank value select 1-4\n"
" - bank 1 on the flash 0x0000000~0x0ffffff\n"
" - bank 2 on the flash 0x1000000~0x1ffffff\n"
" - bank 3 on the flash 0x2000000~0x2ffffff\n"
" - bank 4 on the flash 0x3000000~0x3ffffff\n"
#ifdef DEBUG
"cpld_cmd dump - display the CPLD registers\n"
#endif
);
#endif

39
board/freescale/c29xpcie/cpld.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/**
* Copyright 2013 Freescale Semiconductor
* Author: Mingkai Hu <Mingkai.Hu@freescale.com>
* Po Liu <Po.Liu@freescale.com>
*
* This file provides support for the ngPIXIS, a board-specific FPGA used on
* some Freescale reference boards.
*/
/*
* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
*/
struct cpld_data {
u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
u8 hwver; /* 0x2 - Hardware Version Register */
u8 cpldver; /* 0x3 - Software Version Register */
u8 res[12];
u8 rstcon; /* 0x10 - Reset control register */
u8 flhcsr; /* 0x11 - Flash control and status Register */
u8 wdcsr; /* 0x12 - Watchdog control and status Register */
u8 wdkick; /* 0x13 - Watchdog kick Register */
u8 fancsr; /* 0x14 - Fan control and status Register */
u8 ledcsr; /* 0x15 - LED control and status Register */
u8 misccsr; /* 0x16 - Misc control and status Register */
u8 bootor; /* 0x17 - Boot configure override Register */
u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
};
#define CPLD_BANKSEL_EN 0x02
#define CPLD_BANKSEL_MASK 0x3f
#define CPLD_SELECT_BANK1 0xc0
#define CPLD_SELECT_BANK2 0x80
#define CPLD_SELECT_BANK3 0x40
#define CPLD_SELECT_BANK4 0x00

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board/freescale/c29xpcie/ddr.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include "cpld.h"
#define C29XPCIE_HARDWARE_REVA 0x40
/*
* Micron MT41J128M16HA-15E
* */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 536870912u,
.capacity = 536870912u,
.primary_sdram_width = 32,
.ec_sdram_width = 8,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 14,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1650,
.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
.taa_ps = 14050,
.twr_ps = 15000,
.trcd_ps = 13500,
.trrd_ps = 75000,
.trp_ps = 13500,
.tras_ps = 40000,
.trc_ps = 49500,
.trfc_ps = 160000,
.twtr_ps = 75000,
.trtp_ps = 75000,
.refresh_rate_ps = 7800000,
.tfaw_ps = 30000,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
int i;
popts->clk_adjust = 4;
popts->cpo_override = 0x1f;
popts->write_data_delay = 4;
popts->half_strength_driver_enable = 1;
popts->bstopre = 0x3cf;
popts->quad_rank_present = 1;
popts->rtt_override = 1;
popts->rtt_override_value = 1;
popts->dynamic_power = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x4;
popts->trwt_override = 1;
popts->trwt = 0;
if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
popts->ecc_mode = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}
void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
{
int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
sizeof(generic_spd_eeprom_t));
if (ret) {
printf("DDR: failed to read SPD from address %u\n",
i2c_address);
memset(spd, 0, sizeof(generic_spd_eeprom_t));
}
}

18
board/freescale/c29xpcie/law.c
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@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K,
LAW_TRGT_IF_PLATFORM_SRAM),
};
int num_law_entries = ARRAY_SIZE(law_table);

81
board/freescale/c29xpcie/spl.c
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@ -1,81 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <console.h>
#include <env_internal.h>
#include <init.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
#include <nand.h>
#include <i2c.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
console_init_f();
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
/* relocate environment function pointers etc. */
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
gd->env_addr = (ulong)(SPL_ENV_ADDR);
gd->env_valid = ENV_VALID;
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("TPL\n");
#else
puts("SPL\n");
#endif
nand_boot();
}

63
board/freescale/c29xpcie/spl_minimal.c
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@ -1,63 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <mpc85xx.h>
#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
void board_init_f(ulong bootflag)
{
u32 plat_ratio;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#endif
/* initialize selected port with appropriate baud rate */
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot...\n");
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("SPL\n");
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

84
board/freescale/c29xpcie/tlb.c
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@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_64M, 1),
#ifdef CONFIG_PCI
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
#endif
#endif
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_64K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 6, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_256K, 1),
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_SYS_INIT_L2_ADDR
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 12, BOOKE_PAGESZ_256K, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

12
board/freescale/mpc8536ds/Kconfig
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@ -1,12 +0,0 @@
if TARGET_MPC8536DS
config SYS_BOARD
default "mpc8536ds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8536DS"
endif

9
board/freescale/mpc8536ds/MAINTAINERS
View File

@ -1,9 +0,0 @@
MPC8536DS BOARD
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
F: board/freescale/mpc8536ds/
F: include/configs/MPC8536DS.h
F: configs/MPC8536DS_defconfig
F: configs/MPC8536DS_36BIT_defconfig
F: configs/MPC8536DS_SDCARD_defconfig
F: configs/MPC8536DS_SPIFLASH_defconfig

10
board/freescale/mpc8536ds/Makefile
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@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2008 Freescale Semiconductor.
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mpc8536ds.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

127
board/freescale/mpc8536ds/README
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@ -1,127 +0,0 @@
Overview:
=========
The MPC8536E integrates a PowerPC processor core with system logic
required for imaging, networking, and communications applications.
Boot from NAND:
===============
The MPC8536E is capable of booting from NAND flash which uses the image
u-boot-nand.bin. This image contains two parts: a first stage image(also
call 4K NAND loader and a second stage image. The former is appended to
the latter to produce u-boot-nand.bin.
The bootup process can be divided into two stages: the first stage will
configure the L2SRAM, then copy the second stage image to L2SRAM and jump
to it. The second stage image is to configure all the hardware and boot up
to U-Boot command line.
The 4K NAND loader's code comes from the corresponding nand_spl directory,
along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
is mainly used to shrink the code size to the 4K size limitation.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image. It's set in the board config file when boot from NAND
is selected.
Build and boot steps
--------------------
1. Building image
make MPC8536DS_NAND_config
make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
2. Change dip-switch
SW2[5-8] = 1011
SW9[1-3] = 101
Note: 1 stands for 'on', 0 stands for 'off'
3. Flash image
tftp 1000000 u-boot-nand.bin
nand erase 0 a0000
nand write 1000000 0 a0000
Boot from On-chip ROM:
======================
The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
and boot from eSPI. When power on, the porcessor excutes the ROM code to
initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
the memory device that interfaced to the controller, such as the SDCard or
SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
The memory device should contain a specific data structure with control word
and config word at the fixed address. The config word direct the process how
to config the memory device, and the control word direct the processor where
to find the image on the memory device, or where copy the main image to. The
user can use any method to store the data structure to the memory device, only
if store it on the assigned address.
Build and boot steps
--------------------
For boot from eSDHC:
1. Build image
make MPC8536DS_SDCARD_config
make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
2. Change dip-switch
SW2[5-8] = 0111
SW3[1] = 0
SW8[7] = 0 - The on-board SD/MMC slot is active
SW8[7] = 1 - The externel SD/MMC slot is active
3. Put image to SDCard
Put the follwing info at the assigned address on the SDCard:
Offset | Data | Description
--------------------------------------------------------
| 0x40-0x43 | 0x424F4F54 | BOOT signature |
--------------------------------------------------------
| 0x48-0x4B | 0x00080000 | u-boot.bin's size |
--------------------------------------------------------
| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
--------------------------------------------------------
| 0x58-0x5B | 0xF8F80000 | Target Address |
-------------------------------------------------------
| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
--------------------------------------------------------
| 0x68-0x6B | 0x6 | Number of Config Addr/Data |
--------------------------------------------------------
| 0x80-0x83 | 0xFF720100 | Config Addr 1 |
| 0x84-0x87 | 0xF8F80000 | Config Data 1 |
--------------------------------------------------------
| 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
| 0x8c-0x8f | 0x0000000C | Config Data 2 |
--------------------------------------------------------
| 0x90-0x93 | 0xFF720000 | Config Addr 3 |
| 0x94-0x97 | 0x80010000 | Config Data 3 |
--------------------------------------------------------
| 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
| 0x9c-0x9f | 0x00000040 | Config Data 4 |
--------------------------------------------------------
| 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
| 0xa4-0xa7 | 0x00000100 | Config Data 5 |
--------------------------------------------------------
| 0xa8-0xab | 0x80000001 | Config Addr 6 |
| 0xac-0xaf | 0x80000001 | Config Data 6 |
--------------------------------------------------------
| ...... |
--------------------------------------------------------
| 0x???????? | u-boot.bin |
--------------------------------------------------------
then insert the SDCard to the active slot to boot up.
For boot from eSPI:
1. Build image
make MPC8536DS_SPIFLASH_config
make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
2. Change dip-switch
SW2[5-8] = 0110
3. Put image to SPI flash
Put the info in the above table onto the SPI flash, then
boot up.

59
board/freescale/mpc8536ds/ddr.c
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@ -1,59 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
/*
* Factors to consider for clock adjust:
* - number of chips on bus
* - position of slot
* - DDR1 vs. DDR2?
* - ???
*
* This needs to be determined on a board-by-board basis.
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
popts->clk_adjust = 7;
/*
* Factors to consider for CPO:
* - frequency
* - ddr1 vs. ddr2
*/
popts->cpo_override = 10;
/*
* Factors to consider for write data delay:
* - number of DIMMs
*
* 1 = 1/4 clock delay
* 2 = 1/2 clock delay
* 3 = 3/4 clock delay
* 4 = 1 clock delay
* 5 = 5/4 clock delay
* 6 = 3/2 clock delay
*/
popts->write_data_delay = 3;
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* For wake up arp feature, we need enable auto self refresh
*/
popts->auto_self_refresh_en = 1;
popts->sr_it = 0x6;
}

19
board/freescale/mpc8536ds/law.c
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@ -1,19 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

293
board/freescale/mpc8536ds/mpc8536ds.c
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@ -1,293 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
#include <miiphy.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <spd_sdram.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
#include <sata.h>
#include "../common/sgmii_riser.h"
int board_early_init_f (void)
{
#ifdef CONFIG_MMC
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD |
MPC85xx_PMUXCR_SDHC_WP));
/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
* however, this erratum only applies to MPC8536 Rev1.0.
* So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
(SVR_MIN(get_svr()) >= 0x1))
|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
#endif
return 0;
}
int checkboard (void)
{
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
printf("Board: MPC8536DS Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
case PIXIS_VBOOT_LBMAP_NOR0:
puts ("vBank: 0\n");
break;
case PIXIS_VBOOT_LBMAP_NOR1:
puts ("vBank: 1\n");
break;
case PIXIS_VBOOT_LBMAP_NOR2:
puts ("vBank: 2\n");
break;
case PIXIS_VBOOT_LBMAP_NOR3:
puts ("vBank: 3\n");
break;
case PIXIS_VBOOT_LBMAP_PJET:
puts ("Promjet\n");
break;
case PIXIS_VBOOT_LBMAP_NAND:
puts ("NAND\n");
break;
}
return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
#if defined (CONFIG_DDR_ECC)
ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
ddr->err_sbe = CONFIG_SYS_DDR_SBE;
#endif
asm("sync;isync");
udelay(500);
ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
d_init = 1;
debug("DDR - 1st controller: memory initializing\n");
/*
* Poll until memory is initialized.
* 512 Meg at 400 might hit this 200 times or so.
*/
while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
udelay(1000);
}
debug("DDR: memory initialized\n\n");
asm("sync; isync");
udelay(500);
#endif
return 512 * 1024 * 1024;
}
#endif
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
#ifdef CONFIG_PCI
void pci_init_board(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info;
u32 devdisr, pordevsr;
u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
int first_free_busno;
first_free_busno = fsl_pcie_init_board(0);
#ifdef CONFIG_PCI1
devdisr = in_be32(&gur->devdisr);
pordevsr = in_be32(&gur->pordevsr);
porpllsr = in_be32(&gur->porpllsr);
pci_speed = 66666000;
pci_32 = 1;
pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info, 1);
set_next_law(pci_info.mem_phys,
law_size_bits(pci_info.mem_size), pci_info.law);
set_next_law(pci_info.io_phys,
law_size_bits(pci_info.io_size), pci_info.law);
pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
pci_info.regs);
first_free_busno = fsl_pci_init_port(&pci_info,
&pci1_hose, first_free_busno);
} else {
printf("PCI: disabled\n");
}
puts("\n");
#else
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 1; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
return 0;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
if (is_serdes_configured(SGMII_TSEC1)) {
puts("eTSEC1 is in sgmii mode.\n");
tsec_info[num].phyaddr = 0;
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
if (is_serdes_configured(SGMII_TSEC3)) {
puts("eTSEC3 is in sgmii mode.\n");
tsec_info[num].phyaddr = 1;
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
#ifdef CONFIG_FSL_SGMII_RISER
if (is_serdes_configured(SGMII_TSEC1) ||
is_serdes_configured(SGMII_TSEC3)) {
fsl_sgmii_riser_init(tsec_info, num);
}
#endif
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
#ifdef CONFIG_HAS_FSL_MPH_USB
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
return 0;
}
#endif

70
board/freescale/mpc8536ds/tlb.c
View File

@ -1,70 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256K, 1),
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

2
board/freescale/p1010rdb/README.P1010RDB-PA
View File

@ -88,7 +88,7 @@ Note: 1 stands for 'on', 0 stands for 'off'
Setting of hwconfig
===================
If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example:
"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example:
setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM

12
board/freescale/p1022ds/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_P1022DS
config SYS_BOARD
default "p1022ds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "P1022DS"
endif

13
board/freescale/p1022ds/MAINTAINERS
View File

@ -1,13 +0,0 @@
P1022DS BOARD
M: Timur Tabi <timur@tabi.org>
S: Maintained
F: board/freescale/p1022ds/
F: include/configs/P1022DS.h
F: configs/P1022DS_defconfig
F: configs/P1022DS_36BIT_defconfig
F: configs/P1022DS_36BIT_NAND_defconfig
F: configs/P1022DS_36BIT_SDCARD_defconfig
F: configs/P1022DS_36BIT_SPIFLASH_defconfig
F: configs/P1022DS_NAND_defconfig
F: configs/P1022DS_SDCARD_defconfig
F: configs/P1022DS_SPIFLASH_defconfig

25
board/freescale/p1022ds/Makefile
View File

@ -1,25 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2010 Freescale Semiconductor, Inc.
MINIMAL=
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
endif
endif
ifdef MINIMAL
obj-y += spl_minimal.o
else
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
obj-y += p1022ds.o
obj-y += ddr.o
obj-$(CONFIG_FSL_DIU_FB) += diu.o
endif
obj-y += law.o
obj-y += tlb.o

23
board/freescale/p1022ds/README
View File

@ -1,23 +0,0 @@
Overview
--------
P1022ds is a Low End Dual core platform supporting the P1022 processor
of QorIQ series. P1022 is an e500 based dual core SOC.
Pin Multiplex(hwconfig setting)
-------------------------------
Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex
via hwconfig, i.e:
'setenv hwconfig usb2' to enable USB2 and disable eTsec2
'setenv hwconfig tdm' to enable TDM and disable Audio
'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz)
and disable TDM
'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio
'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources
is 11MHz), disable eTsec2 and TDM
Warning: TDM and AUDIO can not enable simultaneous !
and AUDIO codec clock sources only setting as 11MHz or 12MHz !
'setenv hwconfig 'audclk:12;tdm' --- error !
'setenv hwconfig 'audclk:11;tdm' --- error !
'setenv hwconfig 'audclk:10' --- error !

106
board/freescale/p1022ds/ddr.c
View File

@ -1,106 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust; /* Range: 0-8 */
u32 cpo; /* Range: 2-31 */
u32 write_data_delay; /* Range: 0-6 */
u32 force_2t;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters dimm0[] = {
/*
* memory controller 0
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{1, 549, 5, 31, 3, 0},
{1, 850, 5, 31, 5, 0},
{2, 549, 5, 31, 3, 0},
{2, 850, 5, 31, 5, 0},
{}
};
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
unsigned long ddr_freq;
unsigned int i;
if (ctrl_num) {
printf("Wrong parameter for controller number %d", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
/* set odt_rd_cfg and odt_wr_cfg. */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 1;
}
pbsp = dimm0;
/*
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->write_data_delay = pbsp->write_data_delay;
popts->twot_en = pbsp->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
popts->half_strength_driver_enable = 1;
/* Per AN4039, enable ZQ calibration. */
popts->zq_en = 1;
/*
* For wake-up on ARP, we need auto self refresh enabled
*/
popts->auto_self_refresh_en = 1;
popts->sr_it = 0xb;
}

478
board/freescale/p1022ds/diu.c
View File

@ -1,478 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* Authors: Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <log.h>
#include <linux/ctype.h>
#include <asm/io.h>
#include <stdio_dev.h>
#include <video_fb.h>
#include "../common/ngpixis.h"
#include <fsl_diu_fb.h>
/* The CTL register is called 'csr' in the ngpixis_t structure */
#define PX_CTL_ALTACC 0x80
#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
#define PX_BRDCFG0_ELBC_DIU 0x02
#define PX_BRDCFG1_DVIEN 0x80
#define PX_BRDCFG1_DFPEN 0x40
#define PX_BRDCFG1_BACKLIGHT 0x20
#define PMUXCR_ELBCDIU_MASK 0xc0000000
#define PMUXCR_ELBCDIU_NOR16 0x80000000
#define PMUXCR_ELBCDIU_DIU 0x40000000
/*
* DIU Area Descriptor
*
* Note that we need to byte-swap the value before it's written to the AD
* register. So even though the registers don't look like they're in the same
* bit positions as they are on the MPC8610, the same value is written to the
* AD register on the MPC8610 and on the P1022.
*/
#define AD_BYTE_F 0x10000000
#define AD_ALPHA_C_SHIFT 25
#define AD_BLUE_C_SHIFT 23
#define AD_GREEN_C_SHIFT 21
#define AD_RED_C_SHIFT 19
#define AD_PIXEL_S_SHIFT 16
#define AD_COMP_3_SHIFT 12
#define AD_COMP_2_SHIFT 8
#define AD_COMP_1_SHIFT 4
#define AD_COMP_0_SHIFT 0
/*
* Variables used by the DIU/LBC switching code. It's safe to makes these
* global, because the DIU requires DDR, so we'll only run this code after
* relocation.
*/
static u8 px_brdcfg0;
static u32 pmuxcr;
static void *lbc_lcs0_ba;
static void *lbc_lcs1_ba;
static u32 old_br0, old_or0, old_br1, old_or1;
static u32 new_br0, new_or0, new_br1, new_or1;
void diu_set_pixel_clock(unsigned int pixclock)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
unsigned long speed_ccb, temp;
u32 pixval;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
debug("DIU pixval = %u\n", pixval);
/* Modify PXCLK in GUTS CLKDVDR */
temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
out_be32(&gur->clkdvdr, temp); /* turn off clock */
out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
}
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
const char *name;
u32 pixel_format;
u8 temp;
phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
/*
* Indirect mode requires both BR0 and BR1 to be set to "GPCM",
* otherwise writes to these addresses won't actually appear on the
* local bus, and so the PIXIS won't see them.
*
* In FCM mode, writes go to the NAND controller, which does not pass
* them to the localbus directly. So we force BR0 and BR1 into GPCM
* mode, since we don't care about what's behind the localbus any
* more. However, we save those registers first, so that we can
* restore them when necessary.
*/
new_br0 = old_br0 = get_lbc_br(0);
new_br1 = old_br1 = get_lbc_br(1);
new_or0 = old_or0 = get_lbc_or(0);
new_or1 = old_or1 = get_lbc_or(1);
/*
* Use the existing BRx/ORx values if it's already GPCM. Otherwise,
* force the values to simple 32KB GPCM windows with the most
* conservative timing.
*/
if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
new_or0 = OR_AM_32KB | 0xFF7;
set_lbc_br(0, new_br0);
set_lbc_or(0, new_or0);
}
if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
new_or1 = OR_AM_32KB | 0xFF7;
set_lbc_br(1, new_br1);
set_lbc_or(1, new_or1);
}
/*
* Determine the physical addresses for Chip Selects 0 and 1. The
* BR0/BR1 registers contain the truncated physical addresses for the
* chip selects, mapped via the localbus LAW. Since the BRx registers
* only contain the lower 32 bits of the address, we have to determine
* the upper 4 bits some other way. The proper way is to scan the LAW
* table looking for a matching localbus address. Instead, we cheat.
* We know that the upper bits are 0 for 32-bit addressing, or 0xF for
* 36-bit addressing.
*/
#ifdef CONFIG_PHYS_64BIT
phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
#else
phys0 = old_br0 & old_or0 & BR_BA;
phys1 = old_br1 & old_or1 & BR_BA;
#endif
/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
lbc_lcs0_ba = map_physmem(phys0, 1, 0);
lbc_lcs1_ba = map_physmem(phys1, 1, 0);
pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
temp = in_8(&pixis->brdcfg1);
if (strncmp(port, "lvds", 4) == 0) {
/* Single link LVDS */
temp &= ~PX_BRDCFG1_DVIEN;
/*
* LVDS also needs backlight enabled, otherwise the display
* will be blank.
*/
temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
name = "Single-Link LVDS";
} else { /* DVI */
/* Enable the DVI port, disable the DFP and the backlight */
temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
temp |= PX_BRDCFG1_DVIEN;
name = "DVI";
}
printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
out_8(&pixis->brdcfg1, temp);
/*
* Enable PIXIS indirect access mode. This is a hack that allows us to
* access PIXIS registers even when the LBC pins have been muxed to the
* DIU.
*/
setbits_8(&pixis->csr, PX_CTL_ALTACC);
/*
* Route the LAD pins to the DIU. This will disable access to the eLBC,
* which means we won't be able to read/write any NOR flash addresses!
*/
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
px_brdcfg0 = in_8(lbc_lcs1_ba);
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
in_8(lbc_lcs1_ba);
/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
pmuxcr = in_be32(&gur->pmuxcr);
return fsl_diu_init(xres, yres, pixel_format, 0);
}
/*
* set_mux_to_lbc - disable the DIU so that we can read/write to elbc
*
* On the Freescale P1022, the DIU video signal and the LBC address/data lines
* share the same pins, which means that when the DIU is active (e.g. the
* console is on the DVI display), NOR flash cannot be accessed. So we use the
* weak accessor feature of the CFI flash code to temporarily switch the pin
* mux from DIU to LBC whenever we want to read or write flash. This has a
* significant performance penalty, but it's the only way to make it work.
*
* There are two muxes: one on the chip, and one on the board. The chip mux
* controls whether the pins are used for the DIU or the LBC, and it is
* set via PMUXCR. The board mux controls whether those signals go to
* the video connector or the NOR flash chips, and it is set via the ngPIXIS.
*/
static int set_mux_to_lbc(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Switch the muxes only if they're currently set to DIU mode */
if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
PMUXCR_ELBCDIU_NOR16) {
/*
* In DIU mode, the PIXIS can only be accessed indirectly
* since we can't read/write the LBC directly.
*/
/* Set the board mux to LBC. This will disable the display. */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
out_8(lbc_lcs1_ba, px_brdcfg0);
in_8(lbc_lcs1_ba);
/* Disable indirect PIXIS mode */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC);
/* Set the chip mux to LBC mode, so that writes go to flash. */
out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) |
PMUXCR_ELBCDIU_NOR16);
in_be32(&gur->pmuxcr);
/* Restore the BR0 and BR1 settings */
set_lbc_br(0, old_br0);
set_lbc_or(0, old_or0);
set_lbc_br(1, old_br1);
set_lbc_or(1, old_or1);
return 1;
}
return 0;
}
/*
* set_mux_to_diu - re-enable the DIU muxing
*
* This function restores the chip and board muxing to point to the DIU.
*/
static void set_mux_to_diu(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Set BR0 and BR1 to GPCM mode */
set_lbc_br(0, new_br0);
set_lbc_or(0, new_or0);
set_lbc_br(1, new_br1);
set_lbc_or(1, new_or1);
/* Enable indirect PIXIS mode */
setbits_8(&pixis->csr, PX_CTL_ALTACC);
/* Set the board mux to DIU. This will enable the display. */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
in_8(lbc_lcs1_ba);
/* Set the chip mux to DIU mode. */
out_be32(&gur->pmuxcr, pmuxcr);
in_be32(&gur->pmuxcr);
}
/*
* pixis_read - board-specific function to read from the PIXIS
*
* This function overrides the generic pixis_read() function, so that it can
* use PIXIS indirect mode if necessary.
*/
u8 pixis_read(unsigned int reg)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Use indirect mode if the mux is currently set to DIU mode */
if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
PMUXCR_ELBCDIU_NOR16) {
out_8(lbc_lcs0_ba, reg);
return in_8(lbc_lcs1_ba);
} else {
void *p = (void *)PIXIS_BASE;
return in_8(p + reg);
}
}
/*
* pixis_write - board-specific function to write to the PIXIS
*
* This function overrides the generic pixis_write() function, so that it can
* use PIXIS indirect mode if necessary.
*/
void pixis_write(unsigned int reg, u8 value)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Use indirect mode if the mux is currently set to DIU mode */
if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
PMUXCR_ELBCDIU_NOR16) {
out_8(lbc_lcs0_ba, reg);
out_8(lbc_lcs1_ba, value);
/* Do a read-back to ensure the write completed */
in_8(lbc_lcs1_ba);
} else {
void *p = (void *)PIXIS_BASE;
out_8(p + reg, value);
}
}
void pixis_bank_reset(void)
{
/*
* For some reason, a PIXIS bank reset does not work if the PIXIS is
* in indirect mode, so switch to direct mode first.
*/
set_mux_to_lbc();
out_8(&pixis->vctl, 0);
out_8(&pixis->vctl, 1);
while (1);
}
#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
void flash_write8(u8 value, void *addr)
{
int sw = set_mux_to_lbc();
__raw_writeb(value, addr);
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write16(u16 value, void *addr)
{
int sw = set_mux_to_lbc();
__raw_writew(value, addr);
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write32(u32 value, void *addr)
{
int sw = set_mux_to_lbc();
__raw_writel(value, addr);
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode.
* set_mux_to_diu() includes a sync that will ensure the
* __raw_readb() completes before it switches the mux.
*/
__raw_readb(addr);
set_mux_to_diu();
}
}
void flash_write64(u64 value, void *addr)
{
int sw = set_mux_to_lbc();
uint32_t *p = addr;
/*
* There is no __raw_writeq(), so do the write manually. We don't trust
* the compiler, so we use inline assembly.
*/
__asm__ __volatile__(
"stw%U0%X0 %2,%0;\n"
"stw%U1%X1 %3,%1;\n"
: "=m" (*p), "=m" (*(p + 1))
: "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value)));
if (sw) {
/*
* To ensure the post-write is completed to eLBC, software must
* perform a dummy read from one valid address from eLBC space
* before changing the eLBC_DIU from NOR mode to DIU mode. We
* read addr+4 because we just wrote to addr+4, so that's how we
* maintain execution order. set_mux_to_diu() includes a sync
* that will ensure the __raw_readb() completes before it
* switches the mux.
*/
__raw_readb(addr + 4);
set_mux_to_diu();
}
}
u8 flash_read8(void *addr)
{
u8 ret;
int sw = set_mux_to_lbc();
ret = __raw_readb(addr);
if (sw)
set_mux_to_diu();
return ret;
}
u16 flash_read16(void *addr)
{
u16 ret;
int sw = set_mux_to_lbc();
ret = __raw_readw(addr);
if (sw)
set_mux_to_diu();
return ret;
}
u32 flash_read32(void *addr)
{
u32 ret;
int sw = set_mux_to_lbc();
ret = __raw_readl(addr);
if (sw)
set_mux_to_diu();
return ret;
}
u64 flash_read64(void *addr)
{
u64 ret;
int sw = set_mux_to_lbc();
/* There is no __raw_readq(), so do the read manually */
ret = *(volatile u64 *)addr;
if (sw)
set_mux_to_diu();
return ret;
}
#endif

18
board/freescale/p1022ds/law.c
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@ -1,18 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

364
board/freescale/p1022ds/p1022ds.c
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@ -1,364 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <net.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <asm/fsl_law.h>
#include <netdev.h>
#include <i2c.h>
#include <hwconfig.h>
#include "../common/ngpixis.h"
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, 0x1000);
#ifdef CONFIG_SYS_RAMBOOT
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
#endif
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
/* Set the pin muxing to enable ETSEC2. */
clrbits_be32(&gur->pmuxcr2, 0x001F8000);
/* Enable the SPI */
clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
return 0;
}
int checkboard(void)
{
u8 sw;
printf("Board: P1022DS Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
switch ((sw & PIXIS_LBMAP_MASK) >> 6) {
case 0:
printf ("vBank: %u\n", ((sw & 0x30) >> 4));
break;
case 1:
printf ("NAND\n");
break;
case 2:
case 3:
puts ("Promjet\n");
break;
}
return 0;
}
#define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */
#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03
/* Route the I2C1 pins to the SSI port instead. */
#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08
/* Choose the 12.288Mhz codec reference clock */
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02
/* Choose the 11.2896Mhz codec reference clock */
#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01
/* Connect to USB2 */
#define CONFIG_PIXIS_BRDCFG0_USB2 0x10
/* Connect to TFM bus */
#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c
/* Connect to SPI */
#define CONFIG_PIXIS_BRDCFG0_SPI 0x80
int misc_init_r(void)
{
u8 temp;
const char *audclk;
size_t arglen;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* For DVI, enable the TFP410 Encoder. */
temp = 0xBF;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0)
return -1;
debug("DVI Encoder Read: 0x%02x\n", temp);
temp = 0x10;
if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0)
return -1;
debug("DVI Encoder Read: 0x%02x\n",temp);
/* Enable the USB2 in PMUXCR2 and FGPA */
if (hwconfig("usb2")) {
clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK,
MPC85xx_PMUXCR2_USB);
setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2);
}
/* tdm and audio can not enable simultaneous*/
if (hwconfig("tdm") && hwconfig("audclk")){
printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n");
return -1;
}
/* Enable the TDM in PMUXCR and FGPA */
if (hwconfig("tdm")) {
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK,
MPC85xx_PMUXCR_TDM);
setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM);
/* TDM need some configration option by SPI */
clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK,
MPC85xx_PMUXCR_SPI);
setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI);
}
/*
* Enable the reference clock for the WM8776 codec, and route the MUX
* pins for SSI. The default is the 12.288 MHz clock
*/
if (hwconfig("audclk")) {
temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK |
CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK);
temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI;
audclk = hwconfig_arg("audclk", &arglen);
/* Check the first two chars only */
if (audclk && (strncmp(audclk, "11", 2) == 0))
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11;
else
temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12;
setbits_8(&pixis->brdcfg1, temp);
}
return 0;
}
/*
* A list of PCI and SATA slots
*/
enum slot_id {
SLOT_PCIE1 = 1,
SLOT_PCIE2,
SLOT_PCIE3,
SLOT_PCIE4,
SLOT_PCIE5,
SLOT_SATA1,
SLOT_SATA2
};
/*
* This array maps the slot identifiers to their names on the P1022DS board.
*/
static const char *slot_names[] = {
[SLOT_PCIE1] = "Slot 1",
[SLOT_PCIE2] = "Slot 2",
[SLOT_PCIE3] = "Slot 3",
[SLOT_PCIE4] = "Slot 4",
[SLOT_PCIE5] = "Mini-PCIe",
[SLOT_SATA1] = "SATA 1",
[SLOT_SATA2] = "SATA 2",
};
/*
* This array maps a given SERDES configuration and SERDES device to the PCI or
* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
*/
static u8 serdes_dev_slot[][SATA2 + 1] = {
[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
[PCIE2] = SLOT_PCIE5 },
[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
[PCIE2] = SLOT_PCIE3,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
[PCIE2] = SLOT_PCIE3 },
[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
[PCIE2] = SLOT_PCIE3,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x1c] = { [PCIE1] = SLOT_PCIE1,
[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
[0x1f] = { [PCIE1] = SLOT_PCIE1 },
};
/*
* Returns the name of the slot to which the PCIe or SATA controller is
* connected
*/
const char *board_serdes_name(enum srds_prtcl device)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr);
unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
enum slot_id slot = serdes_dev_slot[srds_cfg][device];
const char *name = slot_names[slot];
if (name)
return name;
else
return "Nothing";
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
return 0;
}
/*
* Initialize on-board and/or PCI Ethernet devices
*
* Returns:
* <0, error
* 0, no ethernet devices found
* >0, number of ethernet devices initialized
*/
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
unsigned int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
}
#ifdef CONFIG_OF_BOARD_SETUP
/**
* ft_codec_setup - fix up the clock-frequency property of the codec node
*
* Update the clock-frequency property based on the value of the 'audclk'
* hwconfig option. If audclk is not specified, then don't write anything
* to the device tree, because it means that the codec clock is disabled.
*/
static void ft_codec_setup(void *blob, const char *compatible)
{
const char *audclk;
size_t arglen;
u32 freq;
audclk = hwconfig_arg("audclk", &arglen);
if (audclk) {
if (strncmp(audclk, "11", 2) == 0)
freq = 11289600;
else
freq = 12288000;
do_fixup_by_compat_u32(blob, compatible, "clock-frequency",
freq, 1);
}
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
FT_FSL_PCI_SETUP;
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
#endif
/* Update the WM8776 node's clock frequency property */
ft_codec_setup(blob, "wlf,wm8776");
return 0;
}
#endif

131
board/freescale/p1022ds/spl.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <console.h>
#include <env.h>
#include <env_internal.h>
#include <init.h>
#include <ns16550.h>
#include <malloc.h>
#include <mmc.h>
#include <nand.h>
#include <i2c.h>
#include "../common/ngpixis.h"
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
static const u32 sysclk_tbl[] = {
66666000, 7499900, 83332500, 8999900,
99999000, 11111000, 12499800, 13333200
};
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L2_SIZE;
}
void board_init_f(ulong bootflag)
{
int px_spd;
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
console_init_f();
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
#ifdef CONFIG_SPL_SPI_BOOT
/* Enable the SPI */
clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
#endif
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
/* initialize selected port with appropriate baud rate */
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
bus_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI Flash boot...\n");
#endif
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
bd_t *bd;
memset(gd, 0, sizeof(gd_t));
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifndef CONFIG_SPL_NAND_BOOT
env_init();
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
gd->env_addr = (ulong)(SPL_ENV_ADDR);
gd->env_valid = ENV_VALID;
#else
env_relocate();
#endif
#ifdef CONFIG_SYS_I2C
i2c_init_all();
#else
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
dram_init();
#ifdef CONFIG_SPL_NAND_BOOT
puts("Tertiary program loader running in sram...");
#else
puts("Second program loader running in sram...\n");
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

71
board/freescale/p1022ds/spl_minimal.c
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@ -1,71 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
#include <fsl_ddr_sdram.h>
const static u32 sysclk_tbl[] = {
66666000, 7499900, 83332500, 8999900,
99999000, 11111000, 12499800, 13333200
};
void board_init_f(ulong bootflag)
{
int px_spd;
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
#endif
/* for FPGA */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
/* initialize selected port with appropriate baud rate */
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
bus_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
* other blocks can be read.
*/
relocate_code(CONFIG_SPL_RELOC_STACK, 0,
CONFIG_SPL_RELOC_TEXT_BASE);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
puts("\nSecond program loader running in sram...");
nand_boot();
}
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)
{
while (*str)
putc(*str++);
}

101
board/freescale/p1022ds/tlb.c
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@ -1,101 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2010 Freescale Semiconductor, Inc.
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
* Timur Tabi <timur@freescale.com>
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
#endif
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
/* **** - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
/* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_16K, 1),
#endif
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1)
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

12
board/freescale/p1_twr/Kconfig
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@ -1,12 +0,0 @@
if TARGET_P1_TWR
config SYS_BOARD
default "p1_twr"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "p1_twr"
endif

6
board/freescale/p1_twr/MAINTAINERS
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@ -1,6 +0,0 @@
P1_TWR BOARD
M: Xiaobo Xie <xiaobo.xie@nxp.com>
S: Maintained
F: board/freescale/p1_twr/
F: include/configs/p1_twr.h
F: configs/TWR-P1025_defconfig

9
board/freescale/p1_twr/Makefile
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@ -1,9 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Freescale Semiconductor, Inc.
#
obj-y += p1_twr.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

69
board/freescale/p1_twr/ddr.c
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@ -1,69 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <vsprintf.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
sys_info_t sysinfo;
char buf[32];
size_t ddr_size;
fsl_ddr_cfg_regs_t ddr_cfg_regs = {
.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
#endif
.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
};
get_sys_info(&sysinfo);
printf("Configuring DDR for %s MT/s data rate\n",
strmhz(buf, sysinfo.freq_ddrbus));
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
printf("ERROR setting Local Access Windows for DDR\n");
return 0;
};
return ddr_size;
}

15
board/freescale/p1_twr/law.c
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@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC)
};
int num_law_entries = ARRAY_SIZE(law_table);

292
board/freescale/p1_twr/p1_twr.c
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@ -1,292 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <hwconfig.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <i2c.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <asm/mp.h>
#include <miiphy.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <ioports.h>
#include <asm/fsl_serdes.h>
#include <netdev.h>
#define SYSCLK_64 64000000
#define SYSCLK_66 66666666
unsigned long get_board_sys_clk(ulong dummy)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
unsigned int cpdat_val = 0;
/* Set-up up pin muxing based on board switch settings */
cpdat_val = par_io[1].cpdat;
/* Check switch setting for SYSCLK select (PB3) */
if (cpdat_val & 0x10000000)
return SYSCLK_64;
else
return SYSCLK_66;
return 0;
}
#ifdef CONFIG_QE
#define PCA_IOPORT_I2C_ADDR 0x23
#define PCA_IOPORT_OUTPUT_CMD 0x2
#define PCA_IOPORT_CFG_CMD 0x6
const qe_iop_conf_t qe_iop_conf_tab[] = {
#ifdef CONFIG_TWR_P1025
/* GPIO */
{1, 0, 1, 0, 0},
{1, 18, 1, 0, 0},
/* GPIO for switch options */
{1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
{1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
{1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
{1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
/* QE_MUX_MDC */
{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
/* QE_MUX_MDIO */
{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
/* UCC_1_MII */
{0, 23, 2, 0, 2}, /* CLK12 */
{0, 24, 2, 0, 1}, /* CLK9 */
{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
{0, 17, 2, 0, 2}, /* ENET1_CRS */
{0, 16, 2, 0, 2}, /* ENET1_COL */
/* UCC_5_RMII */
{1, 11, 2, 0, 1}, /* CLK13 */
{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
/* TDMA - clock option is configured in OS based on board setting */
{1, 23, 2, 0, 2}, /* TDMA_TXD */
{1, 25, 2, 0, 2}, /* TDMA_RXD */
{1, 26, 1, 0, 2}, /* TDMA_SYNC */
#endif
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
#endif
int board_early_init_f(void)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr,
(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
/* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
return 0;
}
int checkboard(void)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u8 boot_status;
printf("Board: %s\n", CONFIG_BOARDNAME);
boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
puts("rom_loc: ");
if (boot_status == PORBMSR_ROMLOC_NOR)
puts("nor flash");
else if (boot_status == PORBMSR_ROMLOC_SDHC)
puts("sd");
else
puts("unknown");
puts("\n");
return 0;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
return 0;
}
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
printf("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#if defined(CONFIG_UEC_ETH)
/* QE0 and QE3 need to be exposed for UCC1
* and UCC5 Eth mode (in PMUXCR register).
* Currently QE/LBC muxed pins assumed to be
* LBC for U-Boot and PMUXCR updated by OS if required */
uec_standard_init(bis);
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_QE)
static void fdt_board_fixup_qe_pins(void *blob)
{
int node;
if (!hwconfig("qe")) {
/* For QE and eLBC pins multiplexing,
* When don't use QE function, remove
* qe node from dt blob.
*/
node = fdt_path_offset(blob, "/qe");
if (node >= 0)
fdt_del_node(blob, node);
} else {
/* For TWR Peripheral Modules - TWR-SER2
* board only can support Signal Port MII,
* so delete one UEC node when use MII port.
*/
if (hwconfig("mii"))
node = fdt_path_offset(blob, "/qe/ucc@2400");
else
node = fdt_path_offset(blob, "/qe/ucc@2000");
if (node >= 0)
fdt_del_node(blob, node);
}
return;
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
FT_FSL_PCI_SETUP;
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
#endif
#if defined(CONFIG_TWR_P1025)
fdt_board_fixup_qe_pins(blob);
#endif
fsl_fdt_fixup_dr_usb(blob, bd);
return 0;
}
#endif

75
board/freescale/p1_twr/tlb.c
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@ -1,75 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
/* W**G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_1M, 1),
#ifdef CONFIG_PCI
/* *I*G* - PCI memory 1.5G */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O effective: 192K */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
#endif
#endif
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

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board/freescale/t102xqds/Kconfig
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if TARGET_T1024QDS
config SYS_BOARD
default "t102xqds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "T102xQDS"
source "board/freescale/common/Kconfig"
endif

12
board/freescale/t102xqds/MAINTAINERS
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T102XQDS BOARD
#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Orphan (since 2018-05)
F: board/freescale/t102xqds/
F: include/configs/T102xQDS.h
F: configs/T1024QDS_defconfig
F: configs/T1024QDS_NAND_defconfig
F: configs/T1024QDS_SDCARD_defconfig
F: configs/T1024QDS_SPIFLASH_defconfig
F: configs/T1024QDS_DDR4_defconfig
F: configs/T1024QDS_SECURE_BOOT_defconfig
F: configs/T1024QDS_DDR4_SECURE_BOOT_defconfig

15
board/freescale/t102xqds/Makefile
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@ -1,15 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2014 Freescale Semiconductor, Inc.
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += t102xqds.o
obj-y += eth_t102xqds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

328
board/freescale/t102xqds/README
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@ -1,328 +0,0 @@
T1024 SoC Overview
------------------
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
combines two or one 64-bit Power Architecture e5500 core respectively with high
performance datapath acceleration logic, and network peripheral bus interfaces
required for networking and telecommunications. This processor can be used in
applications such as enterprise WLAN access points, routers, switches, firewall
and other packet processing intensive small enterprise and branch office appliances,
and general-purpose embedded computing. Its high level of integration offers
significant performance benefits and greatly helps to simplify board design.
The T1024 SoC includes the following function and features:
- two e5500 cores, each with a private 256 KB L2 cache
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- Three levels of instructions: User, supervisor, and hypervisor
- Independent boot and reset
- Secure boot capability
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- CoreNet coherency manager supporting coherent and noncoherent transactions
with prioritization and bandwidth allocation amongst CoreNet endpoints
- 150 Gbps coherent read bandwidth
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Cryptography Acceleration (SEC 5.x)
- IEEE 1588 support
- Hardware buffer management for buffer allocation and deallocation
- MACSEC on DPAA-based Ethernet ports
- Ethernet interfaces
- Four 1 Gbps Ethernet controllers
- Parallel Ethernet interfaces
- Two RGMII interfaces
- High speed peripheral interfaces
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- One SATA controller supporting 1.5 and 3.0 Gb/s operation
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- 10GbE XFI or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD interface (DIU) with 12 bit dual data rate
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
T1023 Personality
------------------
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
unavailable deep sleep. Rest of the blocks are almost same as T1024.
Differences between T1024 and T1023
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
T1024QDS board Overview
-----------------------
- SERDES Connections
4 lanes supporting the following:
- PCI Express: supports Gen 1 and Gen 2
- SGMII 1G and SGMII 2.5G
- QSGMII
- XFI
- SATA 2.0
- High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
- Aurora debug with dedicated connectors.
- DDR Controller
- Supports up to 1600 MTPS data-rate.
- Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
- Supports Single-, dual- or quad-rank DIMMs
- DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
- IFC/Local Bus
- NAND Flash: 8-bit, async, up to 2GB
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- NOR devices support 8 virtual banks
- Socketed to allow alternate devices
- GASIC: Simple (minimal) target within QIXIS FPGA
- PromJET rapid memory download support
- IFC Debug/Development card
- Ethernet
- Two on-board RGMII 10M/100M/1G ethernet ports.
- One QSGMII interface
- Four SGMII interface supporting 1Gbps
- Three SGMII interfaces supporting 2.5Gbps
- one 10Gbps XFI or 10Base-KR interface
- QIXIS System Logic FPGA
- Manages system power and reset sequencing.
- Manages the configurations of DUT, board, and clock for dynamic shmoo.
- Collects V-I-T data in background for code/power profiling.
- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
- General fault monitoring and logging.
- Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
- Clocks
- System and DDR clock (SYSCLK, DDRCLK).
- Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
- Software programmable in 1 MHz increments from 1-200 MHz.
- SERDES clocks
- Provides clocks to SerDes blocks and slots.
- 100 MHz, 125 MHz and 156.25 MHz options.
- Spread-spectrum option for 100 MHz.
- Power Supplies
- Dedicated PMBus regulator for VDD and VDDC.
- Adjustable from 0.7V to 1.3V at 35A
- VDD can be disabled independanty from VDDC for “deep sleep”.
- DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
- VTT/MVREF automatically track operating voltage.
- Dedicated 2.5V VPP supply.
- Dedicated regulators/filters for AVDD supplies.
- Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
- Video
- DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- USB
- Supports two USB 2.0 ports with integrated PHYs.
- Two type A ports with 5V@1.5A per port.
- Second port can be converted to OTG mini-AB.
- SDHC
For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
- upport for optional clock feedback paths.
- Support for optional high-speed voltage translation direction controls.
- Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
- Support for eMMC memory devices.
- SPI
-On-board support of 3 different devices and sizes.
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Memory map on T1024QDS
----------------------
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
128MB NOR Flash memory Map
--------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
SerDes clock vs DIP-switch settings
-----------------------------------
SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
0x6F 100MHz 125MHz 1101
0xD6 100MHz 100MHz 1111
0x99 156.25MHz 100MHz 1011
T1024 Clock frequency
----------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
Bin3: 1000MHz 1600MT/s 400MHz 500MHz
Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T1024QDS_defconfig (For DDR3L, by default)
or make T1024QDS_D4_defconfig (For DDR4)
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
via software: run command 'qixis_reset altbank' in U-Boot.
via DIP-switch: set SW6[1:4] = '0100'
To change boot source to vbank0:
via software: run command 'qixis_reset' in U-Boot.
via DIP-Switch: set SW6[1:4] = '0000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T1024QDS_NAND_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T1024QDS_SPIFLASH_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 f0000
=> sf write 1000000 0 $filesize
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
a. build PBL image for SD boot
$ make T1024QDS_SDCARD_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x800
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
DIU/QE-TDM/SDXC settings
-------------------
a) For TDM Riser: set pin_mux=tdm in hwconfig
b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
d) For LCD(DFP): set pin_mux=lcd in hwconfig
e) For SDXC: set adaptor=sdxc in hwconfig
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to U-Boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (30KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-Boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T1024QDS
-------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot 1MB
0x100000 0x15FFFF U-Boot env 8KB
0x160000 0x17FFFF FMAN Ucode 128KB
0x180000 0x19FFFF QE Firmware 128KB
SD Card memory Map on T1024QDS
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 U-Boot img 1MB
0x800 0016 U-Boot env 8KB
0x820 0256 FMAN Ucode 128KB
0x920 0256 QE Firmware 128KB
SPI Flash memory Map on T1024QDS
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot img 1MB
0x100000 0x101FFF U-Boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
0x130000 0x14FFFF QE Firmware 128KB
For more details, please refer to T1024QDS Reference Manual and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.

195
board/freescale/t102xqds/ddr.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <init.h>
#include <log.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include <asm/mpc85xx_gpio.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* datarate_mhz_high values need to be in ascending order
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
struct cpu_type *cpu = gd->arch.cpu;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust according to the board ddr freqency and n_banks
* specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found\n");
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* rtt and rtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
#ifdef CONFIG_SYS_FSL_DDR4
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x5f;
#endif
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
* set DDR bus width to 32bit for T1023
*/
if (cpu->soc_ver == SVR_T1023)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
}
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
void __iomem *qixis_base = (void *)QIXIS_BASE;
/* does not provide HW signals for power management */
clrbits_8(qixis_base + 0x21, 0x2);
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif
int dram_init(void)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
gd->ram_size = dram_size;
return 0;
}

445
board/freescale/t102xqds/eth_t102xqds.c
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@ -1,445 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*/
#include <common.h>
#include <command.h>
#include <fdt_support.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t102xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT4 5
#define EMI1_SLOT5 6
#define EMI2 7
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
"T1024QDS_MDIO_RGMII1",
"T1024QDS_MDIO_RGMII2",
"T1024QDS_MDIO_SLOT1",
"T1024QDS_MDIO_SLOT2",
"T1024QDS_MDIO_SLOT3",
"T1024QDS_MDIO_SLOT4",
"T1024QDS_MDIO_SLOT5",
"T1024QDS_MDIO_10GC",
"NULL",
};
/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
static u8 lane_to_slot[] = {2, 3, 4, 5};
static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name;
if (muxval > EMI2)
return NULL;
name = t1024qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
struct t1024qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static void t1024qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if (muxval < 7) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct t1024qds_mdio *priv = bus->priv;
t1024qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct t1024qds_mdio *priv = bus->priv;
t1024qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int t1024qds_mdio_reset(struct mii_dev *bus)
{
struct t1024qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int t1024qds_mdio_init(char *realbusname, u8 muxval)
{
struct t1024qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate t1024qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate t1024qds private data\n");
free(bus);
return -1;
}
bus->read = t1024qds_mdio_read;
bus->write = t1024qds_mdio_write;
bus->reset = t1024qds_mdio_reset;
strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
struct fixed_link f_link;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
fdt_setprop_string(fdt, offset, "phy-connection-type",
"rgmii");
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
if (port == FM1_DTSEC1) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_vsc8234_phy_s5");
} else if (port == FM1_DTSEC2) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_vsc8234_phy_s4");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_aqr105_phy_s3");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
break;
case FM1_DTSEC2:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
break;
case FM1_DTSEC3:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
break;
case FM1_DTSEC4:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
break;
default:
break;
}
fdt_delprop(fdt, offset, "phy-connection-type");
fdt_setprop_string(fdt, offset, "phy-connection-type",
"qsgmii");
fdt_status_okay_by_alias(fdt, "emi1_slot2");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* XFI interface */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
}
}
void fdt_fixup_board_enet(void *fdt)
{
}
/*
* This function reads RCW to check if Serdes1{A:D} is configured
* to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
*/
static void initialize_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
case 0x46:
case 0x47:
lane_to_slot[1] = 2;
break;
default:
break;
}
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0xd5:
case 0xd6:
/* QSGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, 0x8);
fm_info_set_phy_address(FM1_DTSEC2, 0x9);
fm_info_set_phy_address(FM1_DTSEC3, 0xa);
fm_info_set_phy_address(FM1_DTSEC4, 0xb);
break;
case 0x95:
case 0x99:
/*
* XFI does not need a PHY to work, but to avoid U-Boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks the
* XAUI card is used for the XFI MAC, which will cause error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6f:
/* SGMII in Slot3, Slot4, Slot5 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x7f:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x47:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x77:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x5a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x5b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
default:
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
}
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII2;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII1;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
XFI_FM1_MAC1 + idx);
if (lane < 0)
break;
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

31
board/freescale/t102xqds/law.c
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@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifdef CONFIG_MTD_NOR_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

23
board/freescale/t102xqds/pci.c
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@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

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board/freescale/t102xqds/spl.c
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@ -1,156 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2014 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <console.h>
#include <env_internal.h>
#include <init.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/qixis.h"
#include "t102xqds_qixis.h"
#include "../common/spl.h"
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT)
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
u32 porsr1, pinctl;
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
arch_cpu_init();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
gd->flags |= GD_FLG_FULL_MALLOC_INIT;
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)SPL_ENV_ADDR);
#endif
gd->env_addr = (ulong)(SPL_ENV_ADDR);
gd->env_valid = ENV_VALID;
i2c_init_all();
dram_init();
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
fsl_spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

10
board/freescale/t102xqds/t1024_nand_rcw.cfg
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@ -1,10 +0,0 @@
# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
# PBL preamble and RCW header for T1024QDS
aa55aa55 010e0100
# Serdes protocol 0x6F
0810000e 00000000 00000000 00000000
37800001 00000012 e8104000 21000000
00000000 00000000 00000000 00030810
00000000 036c5a00 00000000 00000006

26
board/freescale/t102xqds/t1024_pbi.cfg
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@ -1,26 +0,0 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
09010f00 081e000d
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
09000cd4 fffc0000
09000cd8 81000011
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
091380c0 000FFFFF

10
board/freescale/t102xqds/t1024_sd_rcw.cfg
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@ -1,10 +0,0 @@
# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
# PBL preamble and RCW header for T1024QDS
aa55aa55 010e0100
# Serdes protocol 0x6F
0810000e 00000000 00000000 00000000
37800001 00000012 68104000 21000000
00000000 00000000 00000000 00030810
00000000 036c5a00 00000000 00000006

10
board/freescale/t102xqds/t1024_spi_rcw.cfg
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@ -1,10 +0,0 @@
# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
# PBL preamble and RCW header for T1024QDS
aa55aa55 010e0100
# Serdes protocol 0x6F
0810000e 00000000 00000000 00000000
37800001 00000012 58104000 21000000
00000000 00000000 00000000 00030810
00000000 036c5a00 00000000 00000006

499
board/freescale/t102xqds/t102xqds.c
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@ -1,499 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <fdt_support.h>
#include <i2c.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
char buf[64];
struct cpu_type *cpu = gd->arch.cpu;
static const char *const freq[] = {"100", "125", "156.25", "100.0"};
int clock;
u8 sw = QIXIS_READ(arch);
printf("Board: %sQDS, ", cpu->name);
printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFC Card\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
puts("SERDES Reference: ");
sw = QIXIS_READ(brdcfg[2]);
clock = (sw >> 6) & 3;
printf("Clock1=%sMHz ", freq[clock]);
clock = (sw >> 4) & 3;
printf("Clock2=%sMHz\n", freq[clock]);
return 0;
}
int select_i2c_ch_pca9547(u8 ch, int bus_num)
{
int ret;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return ret;
}
ret = dm_i2c_write(dev, 0, &ch, 1);
#else
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
#endif
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
static int board_mux_lane_to_slot(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 brdcfg9;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
brdcfg9 = QIXIS_READ(brdcfg[9]);
QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
switch (srds_prtcl_s1) {
case 0:
/* SerDes1 is not enabled */
break;
case 0xd5:
case 0x5b:
case 0x6b:
case 0x77:
case 0x6f:
case 0x7f:
QIXIS_WRITE(brdcfg[12], 0x8c);
break;
case 0x40:
QIXIS_WRITE(brdcfg[12], 0xfc);
break;
case 0xd6:
case 0x5a:
case 0x6a:
case 0x56:
QIXIS_WRITE(brdcfg[12], 0x88);
break;
case 0x47:
QIXIS_WRITE(brdcfg[12], 0xcc);
break;
case 0x46:
QIXIS_WRITE(brdcfg[12], 0xc8);
break;
case 0x95:
case 0x99:
brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
QIXIS_WRITE(brdcfg[9], brdcfg9);
QIXIS_WRITE(brdcfg[12], 0x8c);
break;
case 0x116:
QIXIS_WRITE(brdcfg[12], 0x00);
break;
case 0x115:
case 0x119:
case 0x129:
case 0x12b:
/* Aurora, PCIe, SGMII, SATA */
QIXIS_WRITE(brdcfg[12], 0x04);
break;
default:
printf("WARNING: unsupported for SerDes Protocol %d\n",
srds_prtcl_s1);
return -1;
}
return 0;
}
#ifdef CONFIG_ARCH_T1024
static void board_mux_setup(void)
{
u8 brdcfg15;
brdcfg15 = QIXIS_READ(brdcfg[15]);
brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
if (hwconfig_arg_cmp("pin_mux", "tdm")) {
/* Route QE_TDM multiplexed signals to TDM Riser slot */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
/* to UCC (ProfiBus) interface */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
/* to DVI (HDMI) encoder */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
/* to DFP (LCD) encoder */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
}
if (hwconfig_arg_cmp("adaptor", "sdxc"))
/* Route SPI_CS multiplexed signals to SD slot */
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
}
#endif
void board_retimer_ds125df111_init(void)
{
u8 reg;
#ifdef CONFIG_DM_I2C
struct udevice *dev;
int ret, bus_num = 0;
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI,
1, &dev);
if (ret)
goto failed;
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
dm_i2c_write(dev, 0, &reg, 1);
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC,
1, &dev);
if (ret)
goto failed;
reg = I2C_MUX_CH5;
dm_i2c_write(dev, 0, &reg, 1);
/* Access to Control/Shared register */
ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR,
1, &dev);
if (ret)
goto failed;
reg = 0x0;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Read device revision and ID */
dm_i2c_read(dev, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast */
reg = 0x0c;
dm_i2c_write(dev, 0xff, &reg, 1);
/* Reset Channel Registers */
dm_i2c_read(dev, 0, &reg, 1);
reg |= 0x4;
dm_i2c_write(dev, 0, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
dm_i2c_read(dev, 9, &reg, 1);
reg |= 0x24;
dm_i2c_write(dev, 9, &reg, 1);
/* Select VCO Divider to full rate (000) */
dm_i2c_read(dev, 0x18, &reg, 1);
reg &= 0x8f;
dm_i2c_write(dev, 0x18, &reg, 1);
/* Select active PFD MUX input as re-timed data (001) */
dm_i2c_read(dev, 0x1e, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
dm_i2c_write(dev, 0x1e, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
dm_i2c_write(dev, 0x60, &reg, 1);
reg = 0xb2;
dm_i2c_write(dev, 0x61, &reg, 1);
reg = 0x90;
dm_i2c_write(dev, 0x62, &reg, 1);
reg = 0xb3;
dm_i2c_write(dev, 0x63, &reg, 1);
reg = 0xcd;
dm_i2c_write(dev, 0x64, &reg, 1);
return;
failed:
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
return;
#else
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
reg |= 0x24;
i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
reg &= 0x8f;
i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
/* Select active PFD MUX input as re-timed data (001) */
i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
reg = 0xb2;
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
#endif
}
int board_early_init_f(void)
{
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_mux_lane_to_slot();
board_retimer_ds125df111_init();
/* Increase IO drive strength to address FCS error on RGMII */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
return 0;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_64:
return 64000000;
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
#define NUM_SRDS_PLL 2
int misc_init_r(void)
{
#ifdef CONFIG_ARCH_T1024
board_mux_setup();
#endif
return 0;
}
void fdt_fixup_spi_mux(void *blob)
{
int nodeoff = 0;
if (hwconfig_arg_cmp("pin_mux", "tdm")) {
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"eon,en25s64")) >= 0) {
fdt_del_node(blob, nodeoff);
}
} else {
/* remove tdm node */
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"maxim,ds26522")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_spi_mux(blob);
return 0;
}
void qixis_dump_switch(void)
{
int i, nr_of_cfgsw;
QIXIS_WRITE(cms[0], 0x00);
nr_of_cfgsw = QIXIS_READ(cms[1]);
puts("DIP switch settings dump:\n");
for (i = 1; i <= nr_of_cfgsw; i++) {
QIXIS_WRITE(cms[0], i);
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}

14
board/freescale/t102xqds/t102xqds.h
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@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#ifndef __T102x_QDS_H__
#define __T102x_QDS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
int select_i2c_ch_pca9547(u8 ch, int bus_num);
#endif

63
board/freescale/t102xqds/t102xqds_qixis.h
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@ -1,63 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#ifndef __T1024QDS_QIXIS_H__
#define __T1024QDS_QIXIS_H__
/* Definitions of QIXIS Registers for T1024/T1023 QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
#define BRDCFG5_IMX_MASK 0xC0
#define BRDCFG5_IMX_DIU 0x80
#define BRDCFG5_SPIRTE_MASK 0x07
#define BRDCFG5_SPIRTE_TDM 0x01
#define BRDCFG5_SPIRTE_SDHC 0x02
#define BRDCFG9_XFI_TX_DISABLE 0x10
/* BRDCFG13[0:5] TDM configuration and setup */
#define BRDCFG13_TDM_MASK 0xfc
#define BRDCFG13_TDM_INTERFACE 0x37
#define BRDCFG13_HDLC_LOOPBACK 0x29
#define BRDCFG13_TDM_LOOPBACK 0x31
/* BRDCFG15[3] controls LCD Panel Powerdown */
#define BRDCFG15_LCDFM 0x20
#define BRDCFG15_LCDPD 0x10
#define BRDCFG15_LCDPD_MASK 0x10
#define BRDCFG15_LCDPD_ENABLED 0x00
/* BRDCFG15[6:7] controls DIU MUX selction*/
#define BRDCFG15_DIUSEL_MASK 0x03
#define BRDCFG15_DIUSEL_HDMI 0x00
#define BRDCFG15_DIUSEL_LCD 0x01
#define BRDCFG15_DIUSEL_UCC 0x02
#define BRDCFG15_DIUSEL_TDM 0x03
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
#define QIXIS_SYSCLK_150 0x5
#define QIXIS_SYSCLK_160 0x6
#define QIXIS_SYSCLK_166 0x7
#define QIXIS_SYSCLK_64 0x8
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
#endif

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