diff --git a/Kconfig b/Kconfig index 34a88ebe34..6d45534cf1 100644 --- a/Kconfig +++ b/Kconfig @@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ - ARCH_LS1046A) + ARCH_LS1046A || ARCH_QEMU) default 0x400 help Before relocation, memory is very limited on many platforms. Still, diff --git a/MAINTAINERS b/MAINTAINERS index 02971c2015..7bd9d8a8b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -878,6 +878,7 @@ M: Sughosh Ganu R: Heinrich Schuchardt S: Maintained F: cmd/rng.c +F: doc/api/rng.rst F: drivers/rng/ F: drivers/virtio/virtio_rng.c F: include/rng.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21df1c415f..edc9e38c6c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1905,7 +1905,6 @@ source "board/hisilicon/hikey/Kconfig" source "board/hisilicon/hikey960/Kconfig" source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" -source "board/phytec/pcm051/Kconfig" source "board/silica/pengwyn/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" diff --git a/arch/arm/dts/ca-presidio-engboard.dts b/arch/arm/dts/ca-presidio-engboard.dts index c03dacc54a..40c93d7042 100644 --- a/arch/arm/dts/ca-presidio-engboard.dts +++ b/arch/arm/dts/ca-presidio-engboard.dts @@ -10,11 +10,9 @@ #size-cells = <1>; mmc0: mmc@f4400000 { - compatible = "snps,dw-cortina"; + compatible = "cortina,ca-mmc"; reg = <0x0 0xf4400000 0x1000>; bus-width = <4>; - io_ds = <0x77>; - fifo-mode; sd_dll_ctrl = <0xf43200e8>; io_drv_ctrl = <0xf432004c>; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi index 7d9874cafa..d24f621cd6 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi @@ -68,3 +68,7 @@ &portc { bank-name = "portc"; }; + +&i2c0 { + i2c-scl-falling-time-ns = <300>; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index c52abeb1e7..3fedb6f1e1 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -20,6 +20,21 @@ st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x02000000>; + no-map; + }; + }; + led { red { label = "error"; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 84af7fa47b..a07c585415 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -21,6 +21,20 @@ st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x02000000>; + no-map; + }; + }; + led { red { label = "error"; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 4fb71100f5..186dc46754 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -70,11 +70,6 @@ reg = <0xe8000000 0x8000000>; no-map; }; - - optee@fe000000 { - reg = <0xfe000000 0x02000000>; - no-map; - }; }; aliases { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 812e370ee4..7589c6f9dc 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -58,11 +58,6 @@ reg = <0xd4000000 0x4000000>; no-map; }; - - optee@de000000 { - reg = <0xde000000 0x02000000>; - no-map; - }; }; led { diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index d75fab1530..870dae4d70 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -181,7 +181,6 @@ source "board/isee/igep00x0/Kconfig" source "board/overo/Kconfig" source "board/logicpd/zoom1/Kconfig" source "board/ti/am3517crane/Kconfig" -source "board/pandora/Kconfig" source "board/corscience/tricorder/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index c723b223e0..959f12efe1 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved */ #include @@ -224,19 +224,23 @@ static void stm32_fdt_disable_optee(void *blob) { int off, node; + /* Delete "optee" firmware node */ off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); if (off >= 0 && fdtdec_get_is_enabled(blob, off)) - fdt_status_disabled(blob, off); + fdt_del_node(blob, off); - /* Disabled "optee@..." reserved-memory node */ + /* Delete "optee@..." reserved-memory node */ off = fdt_path_offset(blob, "/reserved-memory/"); if (off < 0) return; for (node = fdt_first_subnode(blob, off); node >= 0; node = fdt_next_subnode(blob, node)) { - if (!strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) - fdt_status_disabled(blob, node); + if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) + continue; + + if (fdt_del_node(blob, node)) + printf("Failed to remove optee reserved-memory node\n"); } } diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 285cc56799..753d0750b2 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -24,45 +24,6 @@ config TARGET_SOCRATES bool "Support socrates" select ARCH_MPC8544 -config TARGET_B4420QDS - bool "Support B4420QDS" - select ARCH_B4420 - select SUPPORT_SPL - select PHYS_64BIT - imply PANIC_HANG - -config TARGET_B4860QDS - bool "Support B4860QDS" - select ARCH_B4860 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select FSL_DDR_INTERACTIVE if !SPL_BUILD - imply PANIC_HANG - -config TARGET_BSC9131RDB - bool "Support BSC9131RDB" - select ARCH_BSC9131 - select SUPPORT_SPL - select BOARD_EARLY_INIT_F - -config TARGET_BSC9132QDS - bool "Support BSC9132QDS" - select ARCH_BSC9132 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select BOARD_EARLY_INIT_F - select FSL_DDR_INTERACTIVE - -config TARGET_C29XPCIE - bool "Support C29XPCIE" - select ARCH_C29X - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select SUPPORT_TPL - select PHYS_64BIT - imply PANIC_HANG - config TARGET_P3041DS bool "Support P3041DS" select PHYS_64BIT @@ -95,14 +56,6 @@ config TARGET_P5040DS imply CMD_SATA imply PANIC_HANG -config TARGET_MPC8536DS - bool "Support MPC8536DS" - select ARCH_MPC8536 -# Use DDR3 controller with DDR2 DIMMs on this board - select SYS_FSL_DDRC_GEN3 - imply CMD_SATA - imply FSL_SATA - config TARGET_MPC8541CDS bool "Support MPC8541CDS" select ARCH_MPC8541 @@ -156,14 +109,6 @@ config TARGET_P1010RDB_PB imply CMD_SATA imply PANIC_HANG -config TARGET_P1022DS - bool "Support P1022DS" - select ARCH_P1022 - select SUPPORT_SPL - select SUPPORT_TPL - imply CMD_SATA - imply FSL_SATA - config TARGET_P1023RDB bool "Support P1023RDB" select ARCH_P1023 @@ -243,10 +188,6 @@ config TARGET_P2020RDB imply CMD_SATA imply SATA_SIL -config TARGET_P1_TWR - bool "Support p1_twr" - select ARCH_P1025 - config TARGET_P2041RDB bool "Support P2041RDB" select ARCH_P2041 @@ -260,16 +201,6 @@ config TARGET_QEMU_PPCE500 select ARCH_QEMU_E500 select PHYS_64BIT -config TARGET_T1024QDS - bool "Support T1024QDS" - select ARCH_T1024 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - imply CMD_EEPROM - imply CMD_SATA - imply FSL_SATA - config TARGET_T1023RDB bool "Support T1023RDB" select ARCH_T1023 @@ -290,16 +221,6 @@ config TARGET_T1024RDB imply CMD_EEPROM imply PANIC_HANG -config TARGET_T1040QDS - bool "Support T1040QDS" - select ARCH_T1040 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select PHYS_64BIT - select FSL_DDR_INTERACTIVE - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_T1040RDB bool "Support T1040RDB" select ARCH_T1040 @@ -371,15 +292,6 @@ config TARGET_T2081QDS select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE -config TARGET_T4160QDS - bool "Support T4160QDS" - select ARCH_T4160 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - imply CMD_SATA - imply PANIC_HANG - config TARGET_T4160RDB bool "Support T4160RDB" select ARCH_T4160 @@ -387,16 +299,6 @@ config TARGET_T4160RDB select PHYS_64BIT imply PANIC_HANG -config TARGET_T4240QDS - bool "Support T4240QDS" - select ARCH_T4240 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - select SUPPORT_SPL - select PHYS_64BIT - select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - imply CMD_SATA - imply PANIC_HANG - config TARGET_T4240RDB bool "Support T4240RDB" select ARCH_T4240 @@ -1595,12 +1497,7 @@ config SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). -source "board/freescale/b4860qds/Kconfig" -source "board/freescale/bsc9131rdb/Kconfig" -source "board/freescale/bsc9132qds/Kconfig" -source "board/freescale/c29xpcie/Kconfig" source "board/freescale/corenet_ds/Kconfig" -source "board/freescale/mpc8536ds/Kconfig" source "board/freescale/mpc8541cds/Kconfig" source "board/freescale/mpc8544ds/Kconfig" source "board/freescale/mpc8548cds/Kconfig" @@ -1609,19 +1506,14 @@ source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" -source "board/freescale/p1022ds/Kconfig" source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" -source "board/freescale/p1_twr/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" -source "board/freescale/t102xqds/Kconfig" source "board/freescale/t102xrdb/Kconfig" -source "board/freescale/t1040qds/Kconfig" source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" source "board/freescale/t208xrdb/Kconfig" -source "board/freescale/t4qds/Kconfig" source "board/freescale/t4rdb/Kconfig" source "board/gdsys/p1022/Kconfig" source "board/keymile/Kconfig" diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig deleted file mode 100644 index 9bb667ab4f..0000000000 --- a/board/freescale/b4860qds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_B4860QDS || TARGET_B4420QDS - -config SYS_BOARD - default "b4860qds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "B4860QDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS deleted file mode 100644 index 34ac099e44..0000000000 --- a/board/freescale/b4860qds/MAINTAINERS +++ /dev/null @@ -1,17 +0,0 @@ -B4860QDS BOARD -M: Ashish Kumar -S: Maintained -F: board/freescale/b4860qds/ -F: include/configs/B4860QDS.h -F: configs/B4420QDS_defconfig -F: configs/B4420QDS_NAND_defconfig -F: configs/B4420QDS_SPIFLASH_defconfig -F: configs/B4860QDS_defconfig -F: configs/B4860QDS_NAND_defconfig -F: configs/B4860QDS_SPIFLASH_defconfig -F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig - -B4860QDS_SECURE_BOOT BOARD -M: Ruchika Gupta -S: Maintained -F: configs/B4860QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile deleted file mode 100644 index c0ba2c0168..0000000000 --- a/board/freescale/b4860qds/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2012 Freescale Semiconductor, Inc. - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-y += b4860qds.o -obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o -obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c deleted file mode 100644 index cc8ff11ba4..0000000000 --- a/board/freescale/b4860qds/b4860qds.c +++ /dev/null @@ -1,1276 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/vsc3316_3308.h" -#include "../common/idt8t49n222a_serdes_clk.h" -#include "../common/zm7300.h" -#include "b4860qds.h" -#include "b4860qds_qixis.h" -#include "b4860qds_crossbar_con.h" - -#define CLK_MUX_SEL_MASK 0x4 -#define ETH_PHY_CLK_OUT 0x4 - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - static const char *const freq[] = {"100", "125", "156.25", "161.13", - "122.88", "122.88", "122.88"}; - int clock; - - printf("Board: %sQDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw >= 0x8 && sw <= 0xE) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 5) & 7; - printf("Bank1=%sMHz ", freq[clock]); - sw = QIXIS_READ(brdcfg[4]); - clock = (sw >> 6) & 3; - printf("Bank2=%sMHz\n", freq[clock]); - - return 0; -} - -int select_i2c_ch_pca(u8 ch) -{ - int ret; - - /* Selecting proper channel via PCA*/ - ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); - if (ret) { - printf("PCA: failed to select proper channel.\n"); - return ret; - } - - return 0; -} - -/* - * read_voltage from sensor on I2C bus - * We use average of 4 readings, waiting for 532us befor another reading - */ -#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ -#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ - -static inline int read_voltage(void) -{ - int i, ret, voltage_read = 0; - u16 vol_mon; - - for (i = 0; i < NUM_READINGS; i++) { - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { - printf("VID: Core voltage sensor error\n"); - return -1; - } - debug("VID: bus voltage reads 0x%04x\n", vol_mon); - /* LSB = 4mv */ - voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; - udelay(WAIT_FOR_ADC); - } - /* calculate the average */ - voltage_read /= NUM_READINGS; - - return voltage_read; -} - -static int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); - ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 fusesr; - u8 vid; - int vdd_target, vdd_last; - int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */ - int ret; - unsigned int orig_i2c_speed; - unsigned long vdd_string_override; - char *vdd_string; - static const uint16_t vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - struct vdd_drive { - u8 vid; - unsigned voltage; - }; - - ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - printf("VID: I2c failed to switch channel\n"); - ret = -1; - goto exit; - } - - /* get the voltage ID from fuse status register */ - fusesr = in_be32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - } - vdd_target = vdd[vid]; - debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n", - vid, vdd_target/10); - - /* check override variable for overriding VDD */ - vdd_string = env_get("b4qds_vdd_mv"); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - if (vdd_override >= 819 && vdd_override <= 1212) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("Invalid value.\n"); - } - - if (vdd_target == 0) { - printf("VID: VID not used\n"); - ret = 0; - goto exit; - } - - /* - * Read voltage monitor to check real voltage. - * Voltage monitor LSB is 4mv. - */ - vdd_last = read_voltage(); - if (vdd_last < 0) { - printf("VID: abort VID adjustment\n"); - ret = -1; - goto exit; - } - - debug("VID: Core voltage is at %d mV\n", vdd_last); - ret = select_i2c_ch_pca(I2C_MUX_CH_DPM); - if (ret) { - printf("VID: I2c failed to switch channel to DPM\n"); - ret = -1; - goto exit; - } - - /* Round up to the value of step of Voltage regulator */ - voltage = roundup(vdd_target, ZM_STEP); - debug("VID: rounded up voltage = %d\n", voltage); - - /* lower the speed to 100kHz to access ZM7300 device */ - debug("VID: Setting bus speed to 100KHz if not already set\n"); - orig_i2c_speed = i2c_get_bus_speed(); - if (orig_i2c_speed != 100000) - i2c_set_bus_speed(100000); - - /* Read the existing level on board, if equal to requsted one, - no need to re-set */ - existing_voltage = zm_read_voltage(); - - /* allowing the voltage difference of one step 0.0125V acceptable */ - if ((existing_voltage >= voltage) && - (existing_voltage < (voltage + ZM_STEP))) { - debug("VID: voltage already set as requested,returning\n"); - ret = existing_voltage; - goto out; - } - debug("VID: Changing voltage for board from %dmV to %dmV\n", - existing_voltage/10, voltage/10); - - if (zm_disable_wp() < 0) { - ret = -1; - goto out; - } - /* Change Voltage: the change is done through all the steps in the - way, to avoid reset to the board due to power good signal fail - in big voltage change gap jump. - */ - if (existing_voltage > voltage) { - temp_voltage = existing_voltage - ZM_STEP; - while (temp_voltage >= voltage) { - ret = zm_write_voltage(temp_voltage); - if (ret == temp_voltage) { - temp_voltage -= ZM_STEP; - } else { - /* ZM7300 device failed to set - * the voltage */ - printf - ("VID:Stepping down vol failed:%dmV\n", - temp_voltage/10); - ret = -1; - goto out; - } - } - } else { - temp_voltage = existing_voltage + ZM_STEP; - while (temp_voltage < (voltage + ZM_STEP)) { - ret = zm_write_voltage(temp_voltage); - if (ret == temp_voltage) { - temp_voltage += ZM_STEP; - } else { - /* ZM7300 device failed to set - * the voltage */ - printf - ("VID:Stepping up vol failed:%dmV\n", - temp_voltage/10); - ret = -1; - goto out; - } - } - } - - if (zm_enable_wp() < 0) - ret = -1; - - /* restore the speed to 400kHz */ -out: debug("VID: Restore the I2C bus speed to %dKHz\n", - orig_i2c_speed/1000); - i2c_set_bus_speed(orig_i2c_speed); - if (ret < 0) - goto exit; - - ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); - if (ret) { - printf("VID: I2c failed to switch channel\n"); - ret = -1; - goto exit; - } - vdd_last = read_voltage(); - select_i2c_ch_pca(I2C_CH_DEFAULT); - - if (vdd_last > 0) - printf("VID: Core voltage %d mV\n", vdd_last); - else - ret = -1; - -exit: - if (re_enable) - enable_interrupts(); - return ret; -} - -int configure_vsc3316_3308(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - unsigned int num_vsc16_con, num_vsc08_con; - u32 serdes1_prtcl, serdes2_prtcl; - int ret; - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - - serdes1_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - if (!serdes1_prtcl) { - printf("SERDES1 is not enabled\n"); - return 0; - } - serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); - - serdes2_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - if (!serdes2_prtcl) { - printf("SERDES2 is not enabled\n"); - return 0; - } - serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); - - switch (serdes1_prtcl) { - case 0x29: - case 0x2a: - case 0x2C: - case 0x2D: - case 0x2E: - /* - * Configuration: - * SERDES: 1 - * Lanes: A,B: SGMII - * Lanes: C,D,E,F,G,H: CPRI - */ - debug("Configuring crossbar to use onboard SGMII PHYs:" - "srds_prctl:%x\n", serdes1_prtcl); - num_vsc16_con = NUM_CON_VSC3316; - /* Configure VSC3316 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3316); - if (!ret) { - ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_4sfp_sgmii_12_56, - num_vsc16_con); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_4sfp_sgmii_12_56, - num_vsc16_con); - if (ret) - return ret; - } else { - return ret; - } - break; - - case 0x01: - case 0x02: - case 0x04: - case 0x05: - case 0x06: - case 0x07: - case 0x08: - case 0x09: - case 0x0A: - case 0x0B: - case 0x0C: - case 0x2F: - case 0x30: - case 0x32: - case 0x33: - case 0x34: - case 0x39: - case 0x3A: - case 0x3C: - case 0x3D: - case 0x5C: - case 0x5D: - /* - * Configuration: - * SERDES: 1 - * Lanes: A,B: AURORA - * Lanes: C,d: SGMII - * Lanes: E,F,G,H: CPRI - */ - debug("Configuring crossbar for Aurora, SGMII 3 and 4," - " and CPRI. srds_prctl:%x\n", serdes1_prtcl); - num_vsc16_con = NUM_CON_VSC3316; - /* Configure VSC3316 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3316); - if (!ret) { - ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_sfp_sgmii_aurora, - num_vsc16_con); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_sfp_sgmii_aurora, - num_vsc16_con); - if (ret) - return ret; - } else { - return ret; - } - break; - -#ifdef CONFIG_ARCH_B4420 - case 0x17: - case 0x18: - /* - * Configuration: - * SERDES: 1 - * Lanes: A,B,C,D: SGMII - * Lanes: E,F,G,H: CPRI - */ - debug("Configuring crossbar to use onboard SGMII PHYs:" - "srds_prctl:%x\n", serdes1_prtcl); - num_vsc16_con = NUM_CON_VSC3316; - /* Configure VSC3316 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3316); - if (!ret) { - ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_sgmii_lane_cd, num_vsc16_con); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_sgmii_lane_cd, num_vsc16_con); - if (ret) - return ret; - } else { - return ret; - } - break; -#endif - - case 0x3E: - case 0x0D: - case 0x0E: - case 0x12: - num_vsc16_con = NUM_CON_VSC3316; - /* Configure VSC3316 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3316); - if (!ret) { - ret = vsc3316_config(VSC3316_TX_ADDRESS, - vsc16_tx_sfp, num_vsc16_con); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_RX_ADDRESS, - vsc16_rx_sfp, num_vsc16_con); - if (ret) - return ret; - } else { - return ret; - } - break; - default: - printf("WARNING:VSC crossbars programming not supported for:%x" - " SerDes1 Protocol.\n", serdes1_prtcl); - return -1; - } - - num_vsc08_con = NUM_CON_VSC3308; - /* Configure VSC3308 crossbar switch */ - ret = select_i2c_ch_pca(I2C_CH_VSC3308); - switch (serdes2_prtcl) { -#ifdef CONFIG_ARCH_B4420 - case 0x9d: -#endif - case 0x9E: - case 0x9A: - case 0x98: - case 0x48: - case 0x49: - case 0x4E: - case 0x79: - case 0x7A: - if (!ret) { - ret = vsc3308_config(VSC3308_TX_ADDRESS, - vsc08_tx_amc, num_vsc08_con); - if (ret) - return ret; - ret = vsc3308_config(VSC3308_RX_ADDRESS, - vsc08_rx_amc, num_vsc08_con); - if (ret) - return ret; - } else { - return ret; - } - break; - case 0x80: - case 0x81: - case 0x82: - case 0x83: - case 0x84: - case 0x85: - case 0x86: - case 0x87: - case 0x88: - case 0x89: - case 0x8a: - case 0x8b: - case 0x8c: - case 0x8d: - case 0x8e: - case 0xb1: - case 0xb2: - if (!ret) { - /* - * Extract hwconfig from environment since environment - * is not setup properly yet - */ - env_get_f("hwconfig", buffer, sizeof(buffer)); - buf = buffer; - - if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", - "sfp_amc", "sfp", buf)) { -#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR - /* change default VSC3308 for XFI erratum */ - ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS, - vsc08_tx_sfp, num_vsc08_con); - if (ret) - return ret; - - ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS, - vsc08_rx_sfp, num_vsc08_con); - if (ret) - return ret; -#else - ret = vsc3308_config(VSC3308_TX_ADDRESS, - vsc08_tx_sfp, num_vsc08_con); - if (ret) - return ret; - - ret = vsc3308_config(VSC3308_RX_ADDRESS, - vsc08_rx_sfp, num_vsc08_con); - if (ret) - return ret; -#endif - } else { - ret = vsc3308_config(VSC3308_TX_ADDRESS, - vsc08_tx_amc, num_vsc08_con); - if (ret) - return ret; - - ret = vsc3308_config(VSC3308_RX_ADDRESS, - vsc08_rx_amc, num_vsc08_con); - if (ret) - return ret; - } - - } else { - return ret; - } - break; - default: - printf("WARNING:VSC crossbars programming not supported for: %x" - " SerDes2 Protocol.\n", serdes2_prtcl); - return -1; - } - - return 0; -} - -static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num) -{ - u32 rst_err; - - /* Steps For SerDes PLLs reset and reconfiguration - * or PLL power-up procedure - */ - debug("CALIBRATE PLL:%d\n", pll_num); - clrbits_be32(&srds_regs->bank[pll_num].rstctl, - SRDS_RSTCTL_SDRST_B); - udelay(10); - clrbits_be32(&srds_regs->bank[pll_num].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); - udelay(10); - setbits_be32(&srds_regs->bank[pll_num].rstctl, - SRDS_RSTCTL_RST); - setbits_be32(&srds_regs->bank[pll_num].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - - udelay(20); - - /* Check whether PLL has been locked or not */ - rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) & - SRDS_RSTCTL_RSTERR; - rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT; - debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err); - if (rst_err) - return rst_err; - - return rst_err; -} - -static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num) -{ - int ret = 0; - u32 fcap, dcbias, bcap, pllcr1, pllcr0; - - if (calibrate_pll(srds_regs, pll_num)) { - /* STEP 1 */ - /* Read fcap, dcbias and bcap value */ - clrbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OUT_EN); - fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & - SRDS_PLLSR2_FCAP; - fcap >>= SRDS_PLLSR2_FCAP_SHIFT; - bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) & - SRDS_PLLSR2_BCAP_EN; - bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; - setbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OUT_EN); - dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) & - SRDS_PLLSR2_DCBIAS; - dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; - debug("values of bcap:%x, fcap:%x and dcbias:%x\n", - bcap, fcap, dcbias); - if (fcap == 0 && bcap == 1) { - /* Step 3 */ - clrbits_be32(&srds_regs->bank[pll_num].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - clrbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_EN); - setbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_OVD); - if (calibrate_pll(srds_regs, pll_num)) { - /*save the fcap, dcbias and bcap values*/ - clrbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OUT_EN); - fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) - & SRDS_PLLSR2_FCAP; - fcap >>= SRDS_PLLSR2_FCAP_SHIFT; - bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) - & SRDS_PLLSR2_BCAP_EN; - bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT; - setbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OUT_EN); - dcbias = in_be32 - (&srds_regs->bank[pll_num].pllsr2) & - SRDS_PLLSR2_DCBIAS; - dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT; - - /* Step 4*/ - clrbits_be32(&srds_regs->bank[pll_num].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - setbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BYP_CAL); - clrbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_EN); - setbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_OVD); - /* change the fcap and dcbias to the saved - * values from Step 3 */ - clrbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_PLL_FCAP); - pllcr1 = (in_be32 - (&srds_regs->bank[pll_num].pllcr1)| - (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); - out_be32(&srds_regs->bank[pll_num].pllcr1, - pllcr1); - clrbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OVRD); - pllcr0 = (in_be32 - (&srds_regs->bank[pll_num].pllcr0)| - (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); - out_be32(&srds_regs->bank[pll_num].pllcr0, - pllcr0); - ret = calibrate_pll(srds_regs, pll_num); - if (ret) - return ret; - } else { - goto out; - } - } else { /* Step 5 */ - clrbits_be32(&srds_regs->bank[pll_num].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - udelay(10); - /* Change the fcap, dcbias, and bcap to the - * values from Step 1 */ - setbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BYP_CAL); - clrbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_PLL_FCAP); - pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)| - (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT)); - out_be32(&srds_regs->bank[pll_num].pllcr1, - pllcr1); - clrbits_be32(&srds_regs->bank[pll_num].pllcr0, - SRDS_PLLCR0_DCBIAS_OVRD); - pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)| - (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT)); - out_be32(&srds_regs->bank[pll_num].pllcr0, - pllcr0); - clrbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_EN); - setbits_be32(&srds_regs->bank[pll_num].pllcr1, - SRDS_PLLCR1_BCAP_OVD); - ret = calibrate_pll(srds_regs, pll_num); - if (ret) - return ret; - } - } -out: - return 0; -} - -static int check_serdes_pll_locks(void) -{ - serdes_corenet_t *srds1_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - serdes_corenet_t *srds2_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; - int i, ret1, ret2; - - debug("\nSerDes1 Lock check\n"); - for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { - ret1 = check_pll_locks(srds1_regs, i); - if (ret1) { - printf("SerDes1, PLL:%d didnt lock\n", i); - return ret1; - } - } - debug("\nSerDes2 Lock check\n"); - for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { - ret2 = check_pll_locks(srds2_regs, i); - if (ret2) { - printf("SerDes2, PLL:%d didnt lock\n", i); - return ret2; - } - } - - return 0; -} - -int config_serdes1_refclks(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 serdes1_prtcl, lane; - unsigned int flag_sgmii_aurora_prtcl = 0; - int i; - int ret = 0; - - serdes1_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - if (!serdes1_prtcl) { - printf("SERDES1 is not enabled\n"); - return -1; - } - serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); - - /* To prevent generation of reset request from SerDes - * while changing the refclks, By setting SRDS_RST_MSK bit, - * SerDes reset event cannot cause a reset request - */ - setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); - - /* Reconfigure IDT idt8t49n222a device for CPRI to work - * For this SerDes1's Refclk1 and refclk2 need to be set - * to 122.88MHz - */ - switch (serdes1_prtcl) { - case 0x29: - case 0x2A: - case 0x2C: - case 0x2D: - case 0x2E: - case 0x01: - case 0x02: - case 0x04: - case 0x05: - case 0x06: - case 0x07: - case 0x08: - case 0x09: - case 0x0A: - case 0x0B: - case 0x0C: - case 0x2F: - case 0x30: - case 0x32: - case 0x33: - case 0x34: - case 0x39: - case 0x3A: - case 0x3C: - case 0x3D: - case 0x5C: - case 0x5D: - debug("Configuring idt8t49n222a for CPRI SerDes clks:" - " for srds_prctl:%x\n", serdes1_prtcl); - ret = select_i2c_ch_pca(I2C_CH_IDT); - if (!ret) { - ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, - SERDES_REFCLK_122_88, - SERDES_REFCLK_122_88, 0); - if (ret) { - printf("IDT8T49N222A configuration failed.\n"); - goto out; - } else - debug("IDT8T49N222A configured.\n"); - } else { - goto out; - } - select_i2c_ch_pca(I2C_CH_DEFAULT); - - /* Change SerDes1's Refclk1 to 125MHz for on board - * SGMIIs or Aurora to work - */ - for (lane = 0; lane < SRDS_MAX_LANES; lane++) { - enum srds_prtcl lane_prtcl = serdes_get_prtcl - (0, serdes1_prtcl, lane); - switch (lane_prtcl) { - case SGMII_FM1_DTSEC1: - case SGMII_FM1_DTSEC2: - case SGMII_FM1_DTSEC3: - case SGMII_FM1_DTSEC4: - case SGMII_FM1_DTSEC5: - case SGMII_FM1_DTSEC6: - case AURORA: - flag_sgmii_aurora_prtcl++; - break; - default: - break; - } - } - - if (flag_sgmii_aurora_prtcl) - QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); - - /* Steps For SerDes PLLs reset and reconfiguration after - * changing SerDes's refclks - */ - for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { - debug("For PLL%d reset and reconfiguration after" - " changing refclks\n", i+1); - clrbits_be32(&srds_regs->bank[i].rstctl, - SRDS_RSTCTL_SDRST_B); - udelay(10); - clrbits_be32(&srds_regs->bank[i].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); - udelay(10); - setbits_be32(&srds_regs->bank[i].rstctl, - SRDS_RSTCTL_RST); - setbits_be32(&srds_regs->bank[i].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - } - break; - default: - printf("WARNING:IDT8T49N222A configuration not" - " supported for:%x SerDes1 Protocol.\n", - serdes1_prtcl); - } - -out: - /* Clearing SRDS_RST_MSK bit as now - * SerDes reset event can cause a reset request - */ - clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); - return ret; -} - -int config_serdes2_refclks(void) -{ - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes_corenet_t *srds2_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; - u32 serdes2_prtcl; - int ret = 0; - int i; - - serdes2_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - if (!serdes2_prtcl) { - debug("SERDES2 is not enabled\n"); - return -ENODEV; - } - serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); - - /* To prevent generation of reset request from SerDes - * while changing the refclks, By setting SRDS_RST_MSK bit, - * SerDes reset event cannot cause a reset request - */ - setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); - - /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work - * For this SerDes2's Refclk1 need to be set to 100MHz - */ - switch (serdes2_prtcl) { -#ifdef CONFIG_ARCH_B4420 - case 0x9d: -#endif - case 0x9E: - case 0x9A: - /* fallthrough */ - case 0xb1: - case 0xb2: - debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n", - serdes2_prtcl); - ret = select_i2c_ch_pca(I2C_CH_IDT); - if (!ret) { - ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2, - SERDES_REFCLK_100, - SERDES_REFCLK_156_25, 0); - if (ret) { - printf("IDT8T49N222A configuration failed.\n"); - goto out; - } else - debug("IDT8T49N222A configured.\n"); - } else { - goto out; - } - select_i2c_ch_pca(I2C_CH_DEFAULT); - - /* Steps For SerDes PLLs reset and reconfiguration after - * changing SerDes's refclks - */ - for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) { - clrbits_be32(&srds2_regs->bank[i].rstctl, - SRDS_RSTCTL_SDRST_B); - udelay(10); - clrbits_be32(&srds2_regs->bank[i].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); - udelay(10); - setbits_be32(&srds2_regs->bank[i].rstctl, - SRDS_RSTCTL_RST); - setbits_be32(&srds2_regs->bank[i].rstctl, - (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B - | SRDS_RSTCTL_SDRST_B)); - - udelay(10); - } - break; - default: - printf("IDT configuration not supported for:%x S2 Protocol.\n", - serdes2_prtcl); - } - -out: - /* Clearing SRDS_RST_MSK bit as now - * SerDes reset event can cause a reset request - */ - clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK); - return ret; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - int ret; - u32 svr = SVR_SOC_VER(get_svr()); - - /* Create law for MAPLE only for personalities having MAPLE */ - if ((svr == SVR_B4860) || (svr == SVR_B4440) || - (svr == SVR_B4420) || (svr == SVR_B4220)) { - set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, - LAW_TRGT_IF_MAPLE); - } - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0) < 0) - printf("Warning: Adjusting core voltage failed\n"); - - /* SerDes1 refclks need to be set again, as default clks - * are not suitable for CPRI and onboard SGMIIs to work - * simultaneously. - * This function will set SerDes1's Refclk1 and refclk2 - * as per SerDes1 protocols - */ - if (config_serdes1_refclks()) - printf("SerDes1 Refclks couldn't set properly.\n"); - else - printf("SerDes1 Refclks have been set.\n"); - - /* SerDes2 refclks need to be set again, as default clks - * are not suitable for PCIe SATA to work - * This function will set SerDes2's Refclk1 and refclk2 - * for SerDes2 protocols having PCIe in them - * for PCIe SATA to work - */ - ret = config_serdes2_refclks(); - if (!ret) - printf("SerDes2 Refclks have been set.\n"); - else if (ret == -ENODEV) - printf("SerDes disable, Refclks couldn't change.\n"); - else - printf("SerDes2 Refclk reconfiguring failed.\n"); - -#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \ - defined(CONFIG_SYS_FSL_ERRATUM_A006475) - /* Rechecking the SerDes locks after all SerDes configurations - * are done, As SerDes PLLs may not lock reliably at 5 G VCO - * and at cold temperatures. - * Following sequence ensure the proper locking of SerDes PLLs. - */ - if (SVR_MAJ(get_svr()) == 1) { - if (check_serdes_pll_locks()) - printf("SerDes plls still not locked properly.\n"); - else - printf("SerDes plls have been locked well.\n"); - } -#endif - - /* Configure VSC3316 and VSC3308 crossbar switches */ - if (configure_vsc3316_3308()) - printf("VSC:failed to configure VSC3316/3308.\n"); - else - printf("VSC:VSC3316/3308 successfully configured.\n"); - - select_i2c_ch_pca(I2C_CH_DEFAULT); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((sysclk_conf & 0x0C) >> 2) { - case QIXIS_CLK_100: - return 100000000; - case QIXIS_CLK_125: - return 125000000; - case QIXIS_CLK_133: - return 133333333; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch (ddrclk_conf & 0x03) { - case QIXIS_CLK_100: - return 100000000; - case QIXIS_CLK_125: - return 125000000; - case QIXIS_CLK_133: - return 133333333; - } - return 66666666; -} - -static int serdes_refclock(u8 sw, u8 sdclk) -{ - unsigned int clock; - int ret = -1; - u8 brdcfg4; - - if (sdclk == 1) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) - return SRDS_PLLCR0_RFCK_SEL_125; - else - clock = (sw >> 5) & 7; - } else - clock = (sw >> 6) & 3; - - switch (clock) { - case 0: - ret = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - ret = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - ret = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - case 3: - ret = SRDS_PLLCR0_RFCK_SEL_161_13; - break; - case 4: - case 5: - case 6: - ret = SRDS_PLLCR0_RFCK_SEL_122_88; - break; - default: - ret = -1; - break; - } - - return ret; -} - -#define NUM_SRDS_BANKS 2 - -int misc_init_r(void) -{ - u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS]; - unsigned int i; - int clock; - - sw = QIXIS_READ(brdcfg[2]); - clock = serdes_refclock(sw, 1); - if (clock >= 0) - actual[0] = clock; - else - printf("Warning: SDREFCLK1 switch setting is unsupported\n"); - - sw = QIXIS_READ(brdcfg[4]); - clock = serdes_refclock(sw, 2); - if (clock >= 0) - actual[1] = clock; - else - printf("Warning: SDREFCLK2 switch setting unsupported\n"); - - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES bank %u expects reference clock" - " %sMHz, but actual is %sMHz\n", i + 1, - serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} - -/* - * Dump board switch settings. - * The bits that cannot be read/sampled via some FPGA or some - * registers, they will be displayed as - * underscore in binary format. mask[] has those bits. - * Some bits are calculated differently than the actual switches - * if booting with overriding by FPGA. - */ -void qixis_dump_switch(void) -{ - int i; - u8 sw[5]; - - /* - * Any bit with 1 means that bit cannot be reverse engineered. - * It will be displayed as _ in binary format. - */ - static const u8 mask[] = {0x07, 0, 0, 0xff, 0}; - char buf[10]; - u8 brdcfg[16], dutcfg[16]; - - for (i = 0; i < 16; i++) { - brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); - dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); - } - - sw[0] = ((brdcfg[0] & 0x0f) << 4) | \ - (brdcfg[9] & 0x08); - sw[1] = ((dutcfg[1] & 0x01) << 7) | \ - ((dutcfg[2] & 0x07) << 4) | \ - ((dutcfg[6] & 0x10) >> 1) | \ - ((dutcfg[6] & 0x80) >> 5) | \ - ((dutcfg[1] & 0x40) >> 5) | \ - (dutcfg[6] & 0x01); - sw[2] = dutcfg[0]; - sw[3] = 0; - sw[4] = ((brdcfg[1] & 0x30) << 2) | \ - ((brdcfg[1] & 0xc0) >> 2) | \ - (brdcfg[1] & 0x0f); - - puts("DIP switch settings:\n"); - for (i = 0; i < 5; i++) { - printf("SW%d = 0b%s (0x%02x)\n", - i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); - } -} diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h deleted file mode 100644 index 4a8e91b58f..0000000000 --- a/board/freescale/b4860qds/b4860qds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); - -#endif diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h deleted file mode 100644 index b9d59c23be..0000000000 --- a/board/freescale/b4860qds/b4860qds_crossbar_con.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CROSSBAR_CONNECTIONS_H__ -#define __CROSSBAR_CONNECTIONS_H__ - -#define NUM_CON_VSC3316 8 -#define NUM_CON_VSC3308 4 - -static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, - {5, 11}, {4, 5}, {2, 6}, {12, 9} }; - -static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; - -static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, - {7, 8}, {9, 0}, {2, 14}, {12, 15}, - {-1, -1}, {-1, -1} }; - -static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, - {7, 8}, {9, 0}, {5, 14}, {4, 15}, - {-1, -1}, {-1, -1} }; - -static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, - {7, 8}, {9, 0}, {5, 14}, - {4, 15}, {2, 12}, {12, 13} }; - -#ifdef CONFIG_ARCH_B4420 -static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -#endif - -static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; - -static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, - {11, 11}, {5, 10}, {6, 3}, {9, 12} }; - -static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; - -static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, - {7, 8}, {1, 9}, {14, 3}, {15, 12}, - {-1, -1}, {-1, -1} }; - -static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, - {7, 8}, {1, 9}, {14, 11}, {15, 10}, - {-1, -1}, {-1, -1} }; - -static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, - {7, 8}, {1, 9}, {14, 11}, - {15, 10}, {13, 3}, {12, 12} }; - -#ifdef CONFIG_ARCH_B4420 -static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; -#endif - -static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, - {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; - -static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; - -static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} }; - -static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; - -static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} }; - -#endif diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h deleted file mode 100644 index d4299d8af1..0000000000 --- a/board/freescale/b4860qds/b4860qds_qixis.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __B4860QDS_QIXIS_H__ -#define __B4860QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for B4860QDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* CLK */ -#define QIXIS_CLK_66 0x0 -#define QIXIS_CLK_100 0x1 -#define QIXIS_CLK_125 0x2 -#define QIXIS_CLK_133 0x3 - -#define QIXIS_SRDS1CLK_122 0x5a -#define QIXIS_SRDS1CLK_125 0x5e - -/* SGMII */ -#define PHY_BASE_ADDR 0x18 -#define PORT_NUM 0x04 -#define REGNUM 0x00 -#endif diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg deleted file mode 100644 index 05377bac5b..0000000000 --- a/board/freescale/b4860qds/b4_pbi.cfg +++ /dev/null @@ -1,30 +0,0 @@ -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#slowing down the MDC clock to make it <= 2.5 MHZ -094fc030 00008148 -094fd030 00008148 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/freescale/b4860qds/b4_rcw.cfg b/board/freescale/b4860qds/b4_rcw.cfg deleted file mode 100644 index 597d3914ca..0000000000 --- a/board/freescale/b4860qds/b4_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x2A_0x98 -140e0018 0f001218 00000000 00000000 -54980000 9000a000 e8104000 a9000000 -01000000 00000000 00000000 0001b1f8 -00000000 14000020 00000000 00000011 diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c deleted file mode 100644 index d3aa349ddf..0000000000 --- a/board/freescale/b4860qds/ddr.c +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -dimm_params_t ddr_raw_timing = { - .n_ranks = 2, - .rank_density = 2147483648u, - .capacity = 4294967296u, - .primary_sdram_width = 64, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 1, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 2, /* ECC */ - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1071, - .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ - .taa_ps = 13910, - .twr_ps = 15000, - .trcd_ps = 13910, - .trrd_ps = 6000, - .trp_ps = 13910, - .tras_ps = 34000, - .trc_ps = 48910, - .trfc_ps = 260000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 35000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "RAW timing DDR"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | - */ - {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, - {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, - {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, - {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, - {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, - {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x3e; -} - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - gd->ram_size = dram_size; - - return 0; -} - -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]) -{ - int i, j; - unsigned long long total_mem, current_mem_base, total_ctlr_mem; - unsigned long long rank_density, ctlr_density = 0; - - current_mem_base = 0ull; - total_mem = 0; - /* - * This board has soldered DDR chips. DDRC1 has two rank. - * DDRC2 has only one rank. - * Assigning DDRC2 to lower address and DDRC1 to higher address. - */ - if (pinfo->memctl_opts[0].memctl_interleaving) { - rank_density = pinfo->dimm_params[0][0].rank_density >> - dbw_cap_adj[0]; - ctlr_density = rank_density; - - debug("rank density is 0x%llx, ctlr density is 0x%llx\n", - rank_density, ctlr_density); - for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { - switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - total_ctlr_mem = 2 * ctlr_density; - break; - default: - panic("Unknown interleaving mode"); - } - pinfo->common_timing_params[i].base_address = - current_mem_base; - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem = current_mem_base + total_ctlr_mem; - debug("ctrl %d base 0x%llx\n", i, current_mem_base); - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - } - } else { - /* - * Simple linear assignment if memory - * controllers are not interleaved. - */ - for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - /* Compute DIMM base addresses. */ - unsigned long long cap = - pinfo->dimm_params[i][j].capacity; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", - i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - debug("Total mem by %s is 0x%llx\n", __func__, total_mem); - - return total_mem; -} diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c deleted file mode 100644 index 6d5f3d1fda..0000000000 --- a/board/freescale/b4860qds/eth_b4860qds.c +++ /dev/null @@ -1,454 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - * Author: Sandeep Kumar Singh - */ - -/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */ - -/* - * This file handles the board muxing between the Fman Ethernet MACs and - * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII - * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board. - * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only - * one Fman device on B4860. The SERDES configuration is used to determine - * where the SGMII and XAUI cards exist, and also which Fman MACs are routed - * to which PHYs. So for a given Fman MAC, there is one and only PHY it - * connects to. MACs cannot be routed to PHYs dynamically. This configuration - * is done at boot time by reading SERDES protocol from RCW. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" -#include "../common/fman.h" -#include "../common/qixis.h" -#include "b4860qds_qixis.h" - -#define EMI_NONE 0xFFFFFFFF - -#ifdef CONFIG_FMAN_ENET - -/* - * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that - * lane at index is mapped to slot number n. A value of '0' will mean - * that the mapping must be determined dynamically, or that the lane maps to - * something other than a board slot - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, - 0, 0, 0, 0, - 1, 1, 1, 1, - 0, 0, 0, 0 -}; - -/* - * This function initializes the lane_to_slot[] array. It reads RCW to check - * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes - * lane_to_slot[] accordingly - */ -static void initialize_lane_to_slot(void) -{ - unsigned int serdes2_prtcl; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes2_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - debug("Initializing lane to slot: Serdes2 protocol: %x\n", - serdes2_prtcl); - - switch (serdes2_prtcl) { - case 0x17: - case 0x18: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B,C,D: SGMII - * Lanes: E,F: Aur - * Lanes: G,H: SRIO - */ - case 0x91: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B: SGMII - * Lanes: C,D: SRIO2 - * Lanes: E,F,G,H: XAUI2 - */ - case 0x93: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B,C,D: SGMII - * Lanes: E,F,G,H: XAUI2 - */ - case 0x98: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B,C,D: XAUI2 - * Lanes: E,F,G,H: XAUI2 - */ - case 0x9a: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B: PCI - * Lanes: C,D: SGMII - * Lanes: E,F,G,H: XAUI2 - */ - case 0x9e: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B,C,D: PCI - * Lanes: E,F,G,H: XAUI2 - */ - case 0xb1: - case 0xb2: - case 0x8c: - case 0x8d: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B,C,D: PCI - * Lanes: E,F: SGMII 3&4 - * Lanes: G,H: XFI - */ - case 0xc2: - /* - * Configuration: - * SERDES: 2 - * Lanes: A,B: SGMII - * Lanes: C,D: SRIO2 - * Lanes: E,F,G,H: XAUI2 - */ - lane_to_slot[12] = 2; - lane_to_slot[13] = lane_to_slot[12]; - lane_to_slot[14] = lane_to_slot[12]; - lane_to_slot[15] = lane_to_slot[12]; - break; - - default: - printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); - break; - } - return; -} - -#endif /* #ifdef CONFIG_FMAN_ENET */ - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - struct memac_mdio_info tg_memac_mdio_info; - unsigned int i; - unsigned int serdes1_prtcl, serdes2_prtcl; - int qsgmii; - struct mii_dev *bus; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes1_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - if (!serdes1_prtcl) { - printf("SERDES1 is not enabled\n"); - return 0; - } - serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); - - serdes2_prtcl = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - if (!serdes2_prtcl) { - printf("SERDES2 is not enabled\n"); - return 0; - } - serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); - - printf("Initializing Fman\n"); - - initialize_lane_to_slot(); - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - tg_memac_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the real 10G MDIO bus */ - fm_memac_mdio_init(bis, &tg_memac_mdio_info); - - /* - * Program the two on board DTSEC PHY addresses assuming that they are - * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and - * 6 to on board SGMII phys - */ - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); - - switch (serdes1_prtcl) { - case 0x29: - case 0x2a: - /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ - debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n", - CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, - CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, - CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC6, - CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); - break; -#ifdef CONFIG_ARCH_B4420 - case 0x17: - case 0x18: - /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ - debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n", - CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR, - CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); - /* Fixing Serdes clock by programming FPGA register */ - QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR); - break; -#endif - default: - printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", - serdes1_prtcl); - break; - } - switch (serdes2_prtcl) { - case 0x17: - case 0x18: - debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); - break; - case 0x48: - case 0x49: - debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC1, - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); - break; - case 0xb1: - case 0xb2: - case 0x8c: - case 0x8d: - debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n", - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); - /* - * XFI does not need a PHY to work, but to make U-Boot - * happy, assign a fake PHY address for a XFI port. - */ - fm_info_set_phy_address(FM1_10GEC1, 0); - fm_info_set_phy_address(FM1_10GEC2, 1); - break; - case 0x98: - /* XAUI in Slot1 and Slot2 */ - debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n", - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC1, - CONFIG_SYS_FM1_10GEC1_PHY_ADDR); - debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", - CONFIG_SYS_FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, - CONFIG_SYS_FM1_10GEC2_PHY_ADDR); - break; - case 0x9E: - /* XAUI in Slot2 */ - debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n", - CONFIG_SYS_FM1_10GEC2_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, - CONFIG_SYS_FM1_10GEC2_PHY_ADDR); - break; - default: - printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", - serdes2_prtcl); - break; - } - - /*set PHY address for QSGMII Riser Card on slot2*/ - bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); - qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); - - if (qsgmii) { - switch (serdes2_prtcl) { - case 0xb2: - case 0x8d: - fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); - break; - default: - break; - } - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - int idx = i - FM1_DTSEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - fm_info_set_mdio(i, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - break; - case PHY_INTERFACE_MODE_NONE: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: DTSEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - int idx = i - FM1_10GEC1; - - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - fm_info_set_mdio(i, - miiphy_get_dev_by_name - (DEFAULT_FM_TGEC_MDIO_NAME)); - break; - case PHY_INTERFACE_MODE_NONE: - fm_info_set_phy_address(i, 0); - break; - default: - printf("Fman1: TGEC%u set to unknown interface %i\n", - idx + 1, fm_info_get_enet_if(i)); - fm_info_set_phy_address(i, 0); - break; - } - } - - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - int phy; - char alias[32]; - struct fixed_link f_link; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - - prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - phy = fm_info_get_phy_address(port); - - sprintf(alias, "phy_sgmii_%x", phy); - fdt_set_phy_handle(fdt, compat, addr, alias); - fdt_status_okay_by_alias(fdt, alias); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - /* check if it's XFI interface for 10g */ - switch (prtcl2) { - case 0x80: - case 0x81: - case 0x82: - case 0x83: - case 0x84: - case 0x85: - case 0x86: - case 0x87: - case 0x88: - case 0x89: - case 0x8a: - case 0x8b: - case 0x8c: - case 0x8d: - case 0x8e: - case 0xb1: - case 0xb2: - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, - sizeof(f_link)); - break; - case 0x98: /* XAUI interface */ - strcpy(alias, "phy_xaui_slot1"); - fdt_status_okay_by_alias(fdt, alias); - - strcpy(alias, "phy_xaui_slot2"); - fdt_status_okay_by_alias(fdt, alias); - break; - case 0x9e: /* XAUI interface */ - case 0x9a: - case 0x93: - case 0x91: - strcpy(alias, "phy_xaui_slot1"); - fdt_status_okay_by_alias(fdt, alias); - break; - case 0x97: /* XAUI interface */ - case 0xc3: - strcpy(alias, "phy_xaui_slot2"); - fdt_status_okay_by_alias(fdt, alias); - break; - default: - break; - } - } -} - -/* - * Set status to disabled for unused ethernet node - */ -void fdt_fixup_board_enet(void *fdt) -{ - int i; - char alias[32]; - - for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_NONE: - sprintf(alias, "ethernet%u", i); - fdt_status_disabled_by_alias(fdt, alias); - break; - default: - break; - } - } -} diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c deleted file mode 100644 index b39d720068..0000000000 --- a/board/freescale/b4860qds/law.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c deleted file mode 100644 index 45dd461e77..0000000000 --- a/board/freescale/b4860qds/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c deleted file mode 100644 index fe5ce35013..0000000000 --- a/board/freescale/b4860qds/spl.c +++ /dev/null @@ -1,119 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "b4860qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((sysclk_conf & 0x0C) >> 2) { - case QIXIS_CLK_100: - return 100000000; - case QIXIS_CLK_125: - return 125000000; - case QIXIS_CLK_133: - return 133333333; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch (ddrclk_conf & 0x03) { - case QIXIS_CLK_100: - return 100000000; - case QIXIS_CLK_125: - return 125000000; - case QIXIS_CLK_133: - return 133333333; - } - return 66666666; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, uart_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - uart_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - uart_clk / 16 / CONFIG_BAUDRATE); - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - bd_t *bd; - - bd = (bd_t *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); - env_relocate(); -#else - /* relocate environment function pointers etc. */ - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#endif - - i2c_init_all(); - - puts("\n\n"); - - dram_init(); - -#ifdef CONFIG_SPL_NAND_BOOT - nand_boot(); -#endif -} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c deleted file mode 100644 index 68e2295cb5..0000000000 --- a/board/freescale/b4860qds/tlb.c +++ /dev/null @@ -1,154 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_SPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_64K, 1), -#endif - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_4K, 1), - - /* - * *I*G - SRIO - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for SRIO2. - */ -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_SYS_SRIO1_MEM_PHYS - /* *I*G* - SRIO1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_256M, 1), -#endif -#ifdef CONFIG_SYS_SRIO2_MEM_PHYS - /* *I*G* - SRIO2 */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_256M, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 17, BOOKE_PAGESZ_1M, 1), -#endif -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 17, BOOKE_PAGESZ_2G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig deleted file mode 100644 index dd9f765d7d..0000000000 --- a/board/freescale/bsc9131rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BSC9131RDB - -config SYS_BOARD - default "bsc9131rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "BSC9131RDB" - -endif diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS deleted file mode 100644 index 272d4ad3aa..0000000000 --- a/board/freescale/bsc9131rdb/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -BSC9131RDB BOARD -M: Poonam Aggrwal -S: Maintained -F: board/freescale/bsc9131rdb/ -F: include/configs/BSC9131RDB.h -F: configs/BSC9131RDB_NAND_defconfig -F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig -F: configs/BSC9131RDB_SPIFLASH_defconfig -F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile deleted file mode 100644 index 063db4495e..0000000000 --- a/board/freescale/bsc9131rdb/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2011-2012 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -obj-y += bsc9131rdb.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README deleted file mode 100644 index c8405970c1..0000000000 --- a/board/freescale/bsc9131rdb/README +++ /dev/null @@ -1,151 +0,0 @@ -Overview --------- -- BSC9131 is integrated device that targets Femto base station market. - It combines Power Architecture e500v2 and DSP StarCore SC3850 core - technologies with MAPLE-B2F baseband acceleration processing elements. -- It's MAPLE disabled personality is called 9231. - -The BSC9131 SoC includes the following function and features: -. Power Architecture subsystem including a e500 processor with 256-Kbyte shared - L2 cache -. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache -. The Multi Accelerator Platform Engine for Femto BaseStation Baseband - Processing (MAPLE-B2F) -. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, - Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, - and CRC algorithms -. Consists of accelerators for Convolution, Filtering, Turbo Encoding, - Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion - operations -. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with - ECC, up to 400-MHz clock/800 MHz data rate -. Dedicated security engine featuring trusted boot -. DMA controller -. OCNDMA with four bidirectional channels -. Interfaces -. Two triple-speed Gigabit Ethernet controllers featuring network acceleration - including IEEE 1588. v2 hardware support and virtualization (eTSEC) -. eTSEC 1 supports RGMII/RMII -. eTSEC 2 supports RGMII -. High-speed USB 2.0 host and device controller with ULPI interface -. Enhanced secure digital (SD/MMC) host controller (eSDHC) -. Antenna interface controller (AIC), supporting three industry standard - JESD207/three custom ADI RF interfaces (two dual port and one single port) - and three MAXIM's MaxPHY serial interfaces -. ADI lanes support both full duplex FDD support and half duplex TDD support -. Universal Subscriber Identity Module (USIM) interface that facilitates - communication to SIM cards or Eurochip pre-paid phone cards -. TDM with one TDM port -. Two DUART, four eSPI, and two I2C controllers -. Integrated Flash memory controller (IFC) -. TDM with 256 channels -. GPIO -. Sixteen 32-bit timers - -The e500 core subsystem within the Power Architecture consists of the following: -. 32-Kbyte L1 instruction cache -. 32-Kbyte L1 data cache -. 256-Kbyte L2 cache/L2 memory/L2 stash -. programmable interrupt controller (PIC) -. Debug support -. Timers - -The SC3850 core subsystem consists of the following: -. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) -. 32 Kbyte 8-way level 1 data cache (L1 DCache) -. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) -. Memory management unit (MMU) -. Enhanced programmable interrupt controller (EPIC) -. Debug and profiling unit (DPU) -. Two 32-bit timers - -BSC9131RDB board Overview -------------------------- - 1Gbyte DDR3 (on board DDR) - 128Mbyte 2K page size NAND Flash - 256 Kbit M24256 I2C EEPROM - 128 Mbit SPI Flash memory - USB-ULPI - eTSEC1: Connected to RGMII PHY - eTSEC2: Connected to RGMII PHY - DUART interface: supports one UARTs up to 115200 bps for console display - USIM connector - -Frequency Combinations Supported --------------------------------- -Core MHz/CCB MHz/DDR(MT/s) -1. 1000/500/800 -2. 800/400/667 - -Boot Methods Supported ------------------------ -1. NAND Flash -2. SPI Flash - -Default Boot Method --------------------- -NAND boot - -Building U-Boot --------------- -To build the U-Boot for BSC9131RDB: -1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default) - make BSC9131RDB_NAND -2. NAND Flash with sysclk 100MHz(J16 on RDB open) - make BSC9131RDB_NAND_SYSCLK100 -3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default) - make BSC9131RDB_SPIFLASH -4. SPI Flash with sysclk 100MHz(J16 on RDB open) - make BSC9131RDB_SPIFLASH_SYSCLK100 - -Memory map ------------ - 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable - 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M - 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K - 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K - 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K - 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M - -DDR Memory map ---------------- - 0x0000_0000 0x36FF_FFFF Memory passed onto Linux - 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area - 0x3800_0000 0x4FFF_FFFF DSP Private area - - Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for - data communcation between PowerPC and DSP core. - Rest is PowerPC private area. - -Flashing Images ---------------- -To place a new U-Boot image in the NAND flash and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot-nand.bin - nand erase 0 100000 - nand write 1000000 0 100000 - reset - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 bsc9131rdb.dtb - bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c deleted file mode 100644 index 75c2aec75d..0000000000 --- a/board/freescale/bsc9131rdb/bsc9131rdb.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); - - clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); - setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | - MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); - setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); - clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | - MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, - MPC85xx_PMUXCR_IFC_AD_GPIO | - MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); - - return 0; -} - -int checkboard(void) -{ - struct cpu_type *cpu; - - cpu = gd->arch.cpu; - printf("Board: %sRDB\n", cpu->name); - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -static const struct node_info nodes[] = { - { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, -}; -#endif -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif - - fsl_fdt_fixup_dr_usb(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c deleted file mode 100644 index 0951d7758a..0000000000 --- a/board/freescale/bsc9131rdb/ddr.c +++ /dev/null @@ -1,170 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_DRAM_SIZE 1024 - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {0, 0, NULL} -}; - -unsigned long get_sdram_size(void) -{ - return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); -} - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) { - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - } - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, - LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - - return ddr_size; -} - -#else /* CONFIG_SYS_DDR_RAW_TIMING */ -/* Micron MT41J256M8HX-15E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1870, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c deleted file mode 100644 index ccfe4a2410..0000000000 --- a/board/freescale/bsc9131rdb/law.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, - LAW_TRGT_IF_DSP_CCSR), - SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M, - LAW_TRGT_IF_OCN_DSP), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c deleted file mode 100644 index 4ae9ba06c8..0000000000 --- a/board/freescale/bsc9131rdb/spl_minimal.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -static void sdram_init(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); - __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); -#endif - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - - __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); - - /* Set, but do not enable the memory */ - __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); - - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* Initialize the DDR3 */ - sdram_init(); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c deleted file mode 100644 index e1aacf0607..0000000000 --- a/board/freescale/bsc9131rdb/tlb.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR (PA) */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* CCSRBAR (DSP) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, - CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1M, 1) - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig deleted file mode 100644 index e5499e6129..0000000000 --- a/board/freescale/bsc9132qds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_BSC9132QDS - -config SYS_BOARD - default "bsc9132qds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "BSC9132QDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS deleted file mode 100644 index 95abe3d408..0000000000 --- a/board/freescale/bsc9132qds/MAINTAINERS +++ /dev/null @@ -1,25 +0,0 @@ -BSC9132QDS BOARD -M: Naveen Burmi -S: Maintained -F: board/freescale/bsc9132qds/ -F: include/configs/BSC9132QDS.h -F: configs/BSC9132QDS_NAND_DDRCLK100_defconfig -F: configs/BSC9132QDS_NAND_DDRCLK133_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK100_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK133_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig - -BSC9132QDS_NAND_DDRCLK100_SECURE BOARD -M: Ruchika Gupta -S: Maintained -F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig -F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile deleted file mode 100644 index dcbdf42147..0000000000 --- a/board/freescale/bsc9132qds/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -obj-y += bsc9132qds.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README deleted file mode 100644 index ede95d41da..0000000000 --- a/board/freescale/bsc9132qds/README +++ /dev/null @@ -1,150 +0,0 @@ -Overview --------- - The BSC9132 is a highly integrated device that targets the evolving - Microcell, Picocell, and Enterprise-Femto base station market subsegments. - - The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 - core technologies with MAPLE-B2P baseband acceleration processing elements - to address the need for a high performance, low cost, integrated solution - that handles all required processing layers without the need for an - external device except for an RF transceiver or, in a Micro base station - configuration, a host device that handles the L3/L4 and handover between - sectors. - - The BSC9132 SoC includes the following function and features: - - Power Architecture subsystem including two e500 processors with - 512-Kbyte shared L2 cache - - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 - cache - - 32 Kbyte of shared M3 memory - - The Multi Accelerator Platform Engine for Pico BaseStation Baseband - Processing (MAPLE-B2P) - - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including - ECC), up to 1333 MHz data rate - - Dedicated security engine featuring trusted boot - - Two DMA controllers - - OCNDMA with four bidirectional channels - - SysDMA with sixteen bidirectional channels - - Interfaces - - Four-lane SerDes PHY - - PCI Express controller complies with the PEX Specification-Rev 2.0 - - Two Common Public Radio Interface (CPRI) controller lanes - - High-speed USB 2.0 host and device controller with ULPI interface - - Enhanced secure digital (SD/MMC) host controller (eSDHC) - - Antenna interface controller (AIC), supporting four industry - standard JESD207/four custom ADI RF interfaces - - ADI lanes support both full duplex FDD support & half duplex TDD - - Universal Subscriber Identity Module (USIM) interface that - facilitates communication to SIM cards or Eurochip pre-paid phone - cards - - Two DUART, two eSPI, and two I2C controllers - - Integrated Flash memory controller (IFC) - - GPIO - - Sixteen 32-bit timers - -The SC3850 core subsystem consists of the following: - - 32 KB, 8-way, level 1 instruction cache (L1 ICache) - - 32 KB, 8-way, level 1 data cache (L1 DCache) - - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) - - Memory management unit (MMU) - - Global interrupt controller ( GIC) - - Debug and profiling unit (DPU) - - Two 32-bit quad timers - -BSC9132QDS board Overview -------------------------- - 2Gbyte DDR3 (on board DDR), Dual Ranki - 32Mbyte 16bit NOR flash - 128Mbyte 2K page size NAND Flash - 256 Kbit M24256 I2C EEPROM - 128 Mbit SPI Flash memory - SD slot - USB-ULPI - eTSEC1: Connected to SGMII PHY - eTSEC2: Connected to SGMII PHY - PCIe - CPRI - SerDes - I2C RTC - DUART interface: supports one UARTs up to 115200 bps for console display - -Frequency Combinations Supported --------------------------------- -Core MHz/CCB MHz/DDR(MT/s) -1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz - (SYSCLK = 100MHz, DDRCLK = 100MHz) -2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz - (SYSCLK = 100MHz, DDRCLK = 133MHz) - -Boot Methods Supported ------------------------ -1. NOR Flash -2. NAND Flash -3. SD Card -4. SPI flash - -Default Boot Method --------------------- -NOR boot - -Building U-Boot --------------- -To build the U-Boot for BSC9132QDS: -1. NOR Flash - make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK -2. NAND Flash : It is currently not supported -3. SPI Flash - make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK -4. SD Card - make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK - make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK - -Memory map ------------ - 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable - 0x8000_0000 0x8FFF_FFFF NOR Flash 256M - 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M - 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M - 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M - 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M - 0xC000_0000 0xC000_7FFF M3 Memory 32K - 0xC001_0000 0xC001_FFFF PCI Express I/O 64K - 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K - 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K - 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K - 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M - -Flashing Images ---------------- -To place a new U-Boot image in the NAND flash and then boot -with that new image temporarily, use this: - tftp 1000000 u-boot-nand.bin - nand erase 0 100000 - nand write 1000000 0 100000 - reset - -Using the Device Tree Source File ---------------------------------- -To create the DTB (Device Tree Binary) image file, -use a command similar to this: - - dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb - -Likely, that .dts file will come from here; - - linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts - -Booting Linux -------------- -Place a linux uImage in the TFTP disk area. - - tftp 1000000 uImage - tftp 2000000 rootfs.ext2.gz.uboot - tftp c00000 bsc9132qds.dtb - bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c deleted file mode 100644 index 6870674f7a..0000000000 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ /dev/null @@ -1,432 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_PCI -#include -#include -#endif - -#include "../common/qixis.h" -DECLARE_GLOBAL_DATA_PTR; - - -int board_early_init_f(void) -{ - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - - return 0; -} - -void board_config_serdes_mux(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 pordevsr = in_be32(&gur->pordevsr); - u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - - switch (srds_cfg) { - /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ - case 1: - case 2: - case 3: - case 4: - case 5: - case 22: - case 23: - case 24: - case 25: - case 26: - QIXIS_WRITE_I2C(brdcfg[4], 0x03); - break; - - /* PEX(1) PEX(2) SGMII1 CPRI 1 */ - case 6: - case 7: - case 8: - case 9: - case 10: - case 27: - case 28: - case 29: - case 30: - case 31: - QIXIS_WRITE_I2C(brdcfg[4], 0x01); - break; - - /* PEX(1) PEX(2) SGMII1 SGMII2 */ - case 11: - case 32: - QIXIS_WRITE_I2C(brdcfg[4], 0x00); - break; - - /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ - case 12: - case 13: - case 14: - case 15: - case 16: - case 33: - case 34: - case 35: - case 36: - case 37: - QIXIS_WRITE_I2C(brdcfg[4], 0x07); - break; - - /* PEX(1) SGMII2 SGMII1 CPRI 1 */ - case 17: - case 18: - case 19: - case 20: - case 21: - case 38: - case 39: - case 40: - case 41: - case 42: - QIXIS_WRITE_I2C(brdcfg[4], 0x05); - break; - - /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ - case 43: - case 44: - case 45: - case 46: - case 47: - QIXIS_WRITE_I2C(brdcfg[4], 0x0F); - break; - - - default: - break; - } -} - -/* Configure DSP DDR controller */ -void dsp_ddr_configure(void) -{ - /* - *There are separate DDR-controllers for DSP and PowerPC side DDR. - *copy the ddr controller settings from PowerPC side DDR controller - *to the DSP DDR controller as connected DDR memories are similar. - */ - struct ccsr_ddr __iomem *pa_ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - struct ccsr_ddr temp_ddr; - struct ccsr_ddr __iomem *dsp_ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; - - memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); - temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; - temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; - memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); - dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_MTD_NOR_FLASH - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_64M, 1); - - set_tlb(1, flashbase + 0x4000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); -#endif - board_config_serdes_mux(); - dsp_ddr_configure(); - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - -int checkboard(void) -{ - struct cpu_type *cpu; - u8 sw; - - cpu = gd->arch.cpu; - printf("Board: %sQDS\n", cpu->name); - - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", - QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - printf("IFC chip select:"); - switch (sw) { - case 0: - printf("NOR\n"); - break; - case 2: - printf("Promjet\n"); - break; - case 4: - printf("NAND\n"); - break; - default: - printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - break; - } - - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; - -#endif - -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - tsec_eth_init(bis, tsec_info, num); -#endif - - #ifdef CONFIG_PCI - pci_eth_init(bis); - #endif - - return 0; -} - -#define USBMUX_SEL_MASK 0xc0 -#define USBMUX_SEL_UART2 0xc0 -#define USBMUX_SEL_USB 0x40 -#define SPIMUX_SEL_UART3 0x80 -#define GPS_MUX_SEL_GPS 0x40 - -#define TSEC_1588_CLKIN_MASK 0x03 -#define CON_XCVR_REF_CLK 0x00 - -int misc_init_r(void) -{ - u8 val; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 porbmsr = in_be32(&gur->porbmsr); - u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; - - /*Configure 1588 clock-in source from RF Card*/ - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); - - if (hwconfig("uart2") && hwconfig("usb1")) { - printf("UART2 and USB cannot work together on the board\n"); - printf("Remove one from hwconfig and reset\n"); - } else { - if (hwconfig("uart2")) { - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); - clrbits_be32(&gur->pmuxcr3, - MPC85xx_PMUXCR3_USB_SEL_MASK); - setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); - } else { - /* By default USB should be selected. - * Programming FPGA to select USB. */ - val = QIXIS_READ_I2C(brdcfg[5]); - QIXIS_WRITE_I2C(brdcfg[5], - (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); - } - - } - - if (hwconfig("sim")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SPI) { - - val = QIXIS_READ_I2C(brdcfg[3]); - QIXIS_WRITE_I2C(brdcfg[3], val|0x10); - clrbits_be32(&gur->pmuxcr, - MPC85xx_PMUXCR0_SIM_SEL_MASK); - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); - } - } - - if (hwconfig("uart3")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SDHC) { - - /* UART3 and SPI1 (Flashes) are muxed together */ - val = QIXIS_READ_I2C(brdcfg[3]); - QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); - clrbits_be32(&gur->pmuxcr3, - MPC85xx_PMUXCR3_UART3_SEL_MASK); - setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); - - /* MUX to select UART3 connection to J24 header - * or to GPS */ - val = QIXIS_READ_I2C(brdcfg[6]); - if (hwconfig("gps")) - QIXIS_WRITE_I2C(brdcfg[6], - (val | GPS_MUX_SEL_GPS)); - else - QIXIS_WRITE_I2C(brdcfg[6], - (val & ~(GPS_MUX_SEL_GPS))); - } - } - return 0; -} - -void fdt_del_node_compat(void *blob, const char *compatible) -{ - int err; - int off = fdt_node_offset_by_compatible(blob, -1, compatible); - if (off < 0) { - printf("WARNING: could not find compatible node %s: %s.\n", - compatible, fdt_strerror(off)); - return; - } - err = fdt_del_node(blob, off); - if (err < 0) { - printf("WARNING: could not remove %s: %s.\n", - compatible, fdt_strerror(err)); - } -} - -#if defined(CONFIG_OF_BOARD_SETUP) -#ifdef CONFIG_FDT_FIXUP_PARTITIONS -static const struct node_info nodes[] = { - { "cfi-flash", MTD_DEV_TYPE_NOR, }, - { "fsl,ifc-nand", MTD_DEV_TYPE_NAND, }, -}; -#endif -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - #if defined(CONFIG_PCI) - FT_FSL_PCI_SETUP; - #endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); -#ifdef CONFIG_FDT_FIXUP_PARTITIONS - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); -#endif - - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 porbmsr = in_be32(&gur->porbmsr); - u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; - - if (!(hwconfig("uart2") && hwconfig("usb1"))) { - /* If uart2 is there in hwconfig remove usb node from - * device tree */ - - if (hwconfig("uart2")) { - /* remove dts usb node */ - fdt_del_node_compat(blob, "fsl-usb2-dr"); - } else { - fsl_fdt_fixup_dr_usb(blob, bd); - fdt_del_node_and_alias(blob, "serial2"); - } - } - - if (hwconfig("uart3")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SDHC) - /* Delete SPI node from the device tree */ - fdt_del_node_and_alias(blob, "spi1"); - } else - fdt_del_node_and_alias(blob, "serial3"); - - if (hwconfig("sim")) { - if (romloc == PORBMSR_ROMLOC_NAND_2K || - romloc == PORBMSR_ROMLOC_NOR || - romloc == PORBMSR_ROMLOC_SPI) { - - /* remove dts sdhc node */ - fdt_del_node_compat(blob, "fsl,esdhc"); - } else if (romloc == PORBMSR_ROMLOC_SDHC) { - - /* remove dts sim node */ - fdt_del_node_compat(blob, "fsl,sim-v1.0"); - printf("SIM & SDHC can't work together on the board"); - printf("\nRemove sim from hwconfig and reset\n"); - } - } - - return 0; -} -#endif diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c deleted file mode 100644 index f4effe5a2d..0000000000 --- a/board/freescale/bsc9132qds/ddr.c +++ /dev/null @@ -1,191 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_DDR_RAW_TIMING - -fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - -fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, - .ddr_data_init = CONFIG_MEM_INIT_VALUE, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 -}; - - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {750, 850, &ddr_cfg_regs_800}, - {1060, 1333, &ddr_cfg_regs_1333}, - {0, 0, NULL} -}; - -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ -phys_size_t fixed_sdram(void) -{ - int i; - char buf[32]; - fsl_ddr_cfg_regs_t ddr_cfg_regs; - phys_size_t ddr_size; - ulong ddr_freq, ddr_freq_mhz; - - ddr_freq = get_ddr_freq(0); - ddr_freq_mhz = ddr_freq / 1000000; - - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { - if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && - (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { - memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, - sizeof(ddr_cfg_regs)); - break; - } - } - - if (fixed_ddr_parm_0[i].max_freq == 0) - panic("Unsupported DDR data rate %s MT/s data rate\n", - strmhz(buf, ddr_freq)); - - ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, - LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - } - - return ddr_size; -} - -#else /* CONFIG_SYS_DDR_RAW_TIMING */ -/* Micron MT41J512M8_187E */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 1073741824u, - .capacity = 1073741824u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 15, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1870, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 15000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c deleted file mode 100644 index 6dca3d1751..0000000000 --- a/board/freescale/bsc9132qds/law.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_FPGA_BASE_PHYS - SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), -#endif - SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, - LAW_TRGT_IF_DSP_CCSR), - SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, - LAW_TRGT_IF_OCN_DSP), - SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, - LAW_TRGT_IF_CLASS_DSP), - SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, - LAW_TRGT_IF_CLASS_DSP) -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c deleted file mode 100644 index dd56ad6b2b..0000000000 --- a/board/freescale/bsc9132qds/spl_minimal.c +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void sdram_init(void) -{ - struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; -#if CONFIG_DDR_CLK_FREQ == 100000000 - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_800 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2_800, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4_800, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); -#elif CONFIG_DDR_CLK_FREQ == 133000000 - __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); - __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); - __raw_writel(CONFIG_SYS_DDR_CONTROL_1333 | SDRAM_CFG_32_BE, &ddr->sdram_cfg); - __raw_writel(CONFIG_SYS_DDR_CONTROL_2_1333, &ddr->sdram_cfg_2); - __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); - - __raw_writel(CONFIG_SYS_DDR_TIMING_3_1333, &ddr->timing_cfg_3); - __raw_writel(CONFIG_SYS_DDR_TIMING_0_1333, &ddr->timing_cfg_0); - __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); - __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); - __raw_writel(CONFIG_SYS_DDR_MODE_1_1333, &ddr->sdram_mode); - __raw_writel(CONFIG_SYS_DDR_MODE_2_1333, &ddr->sdram_mode_2); - __raw_writel(CONFIG_SYS_DDR_INTERVAL_1333, &ddr->sdram_interval); - __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_1333, &ddr->sdram_clk_cntl); - __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_1333, &ddr->ddr_wrlvl_cntl); - - __raw_writel(CONFIG_SYS_DDR_TIMING_4_1333, &ddr->timing_cfg_4); - __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); - __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); -#else - puts("Not a valid DDR Freq Found! Please Reset\n"); -#endif - asm volatile("sync;isync"); - udelay(500); - - /* Let the controller go */ - out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); - - set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1); -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* Initialize the DDR3 */ - sdram_init(); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c deleted file mode 100644 index 9466814172..0000000000 --- a/board/freescale/bsc9132qds/tlb.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#ifdef CONFIG_SPL_NAND_BOOT - SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR (PA) */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - - /* CCSRBAR (DSP) */ - SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, - CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR, - MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, - CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_64K, 1), -#endif -#endif - -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_SYS_FPGA_BASE - /* *I*G - Board FPGA */ - SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_256K, 1), -#endif - -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig deleted file mode 100644 index 51e25c39df..0000000000 --- a/board/freescale/c29xpcie/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_C29XPCIE - -config SYS_BOARD - default "c29xpcie" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "C29XPCIE" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS deleted file mode 100644 index 44af12cdbe..0000000000 --- a/board/freescale/c29xpcie/MAINTAINERS +++ /dev/null @@ -1,10 +0,0 @@ -C29XPCIE BOARD -M: Po Liu -S: Maintained -F: board/freescale/c29xpcie/ -F: include/configs/C29XPCIE.h -F: configs/C29XPCIE_defconfig -F: configs/C29XPCIE_NAND_defconfig -F: configs/C29XPCIE_SPIFLASH_defconfig -F: configs/C29XPCIE_NOR_SECBOOT_defconfig -F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile deleted file mode 100644 index 2a9c1be802..0000000000 --- a/board/freescale/c29xpcie/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# - -MINIMAL= -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif -obj-y += c29xpcie.o -obj-y += cpld.o -obj-y += ddr.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/c29xpcie/README b/board/freescale/c29xpcie/README deleted file mode 100644 index a6120f1845..0000000000 --- a/board/freescale/c29xpcie/README +++ /dev/null @@ -1,99 +0,0 @@ -Overview -========= -C29XPCIE board is a series of Freescale PCIe add-in cards to perform -as public key crypto accelerator or secure key management module. -It includes C293PCIE board, C293PCIE board and C291PCIE board. -The Freescale C29x family is a high performance crypto co-processor. -It combines a single e500v2 core with necessary SEC engines. -(maximum core frequency 1000/1200 MHz). - -The C29xPCIE board features are as follows: -Memory subsystem: - - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 64 Mbyte NOR flash single-chip memory - - 4 Gbyte NAND flash memory - - 1 Mbit AT24C1024 I2C EEPROM - - 16 Mbyte SPI memory - -Interfaces: - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port - - eTSEC2, RGMII: one 10/100/1000 port - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging - -Physical Memory Map on C29xPCIE -=============================== -Address Start Address End Memory type -0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR -0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory -0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash -0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM -0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO -0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD -0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR - -Serial Port Configuration on C29xPCIE -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - -Settings of DIP-switch -====================== - SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash - SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash -Note: 1 stands for 'off', 0 stands for 'on' - -Build and program U-Boot to NOR flash -================================== -1. Build u-boot.bin image example: - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make C293PCIE - -2. Program u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff40000 +$filesize - => erase eff40000 +$filesize - => cp.b $loadaddr eff40000 $filesize - -3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. - -Alternate NOR bank -================== -There are four banks in C29XPCIE board, example to change bank booting: -1. Program u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off e9f40000 +$filesize - => erase e9f40000 +$filesize - => cp.b $loadaddr e9f40000 $filesize - -2. Switch to alternate NOR bank - => cpld_cmd reset altbank [bank] - - [bank] bank value select 1-4 - - bank 1 on the flash 0x0000000~0x0ffffff - - bank 2 on the flash 0x1000000~0x1ffffff - - bank 3 on the flash 0x2000000~0x2ffffff - - bank 4 on the flash 0x3000000~0x3ffffff - or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. - -Build and program U-Boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make C29xPCIE_SPIFLASH_config; make - Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin. - -2. Program u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on. diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c deleted file mode 100644 index 74502c6d18..0000000000 --- a/board/freescale/c29xpcie/c29xpcie.c +++ /dev/null @@ -1,159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cpld.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("Board: %sPCIe, ", cpu->name); - printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver)); - - return 0; -} - -int board_early_init_f(void) -{ - struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - - /* Clock configuration to access CPLD using IFC(GPCM) */ - setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned long flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 1; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_64M, 1); - - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - /* Register 1G MDIO bus */ - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void fdt_del_sec(void *blob, int offset) -{ - int nodeoff = 0; - - while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", - CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET - + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) { - fdt_del_node(blob, nodeoff); - offset++; - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - struct cpu_type *cpu; - - cpu = gd->arch.cpu; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - -#if defined(CONFIG_PCI) - FT_FSL_PCI_SETUP; -#endif - - fdt_fixup_memory(blob, (u64)base, (u64)size); - if (cpu->soc_ver == SVR_C291) - fdt_del_sec(blob, 1); - else if (cpu->soc_ver == SVR_C292) - fdt_del_sec(blob, 2); - - return 0; -} -#endif diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c deleted file mode 100644 index 826af428ce..0000000000 --- a/board/freescale/c29xpcie/cpld.c +++ /dev/null @@ -1,133 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/** - * Copyright 2013 Freescale Semiconductor - * Author: Mingkai Hu - * Po Liu - * - * This file provides support for the board-specific CPLD used on some Freescale - * reference boards. - * - * The following macros need to be defined: - * - * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the - * CPLD register map - * - */ - -#include -#include -#include -#include - -#include "cpld.h" -/** - * Set the boot bank to the alternate bank - */ -void cpld_set_altbank(u8 banksel) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - u8 reg11; - - reg11 = in_8(&cpld_data->flhcsr); - - switch (banksel) { - case 1: - out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) - | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1); - break; - case 2: - out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) - | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2); - break; - case 3: - out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) - | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3); - break; - case 4: - out_8(&cpld_data->flhcsr, (reg11 & CPLD_BANKSEL_MASK) - | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4); - break; - default: - printf("Invalid value! [1-4]\n"); - return; - } - - udelay(100); - do_reset(NULL, 0, 0, NULL); -} - -/** - * Set the boot bank to the default bank - */ -void cpld_set_defbank(void) -{ - cpld_set_altbank(4); -} - -#ifdef DEBUG -static void cpld_dump_regs(void) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - - printf("chipid1 = 0x%02x\n", in_8(&cpld_data->chipid1)); - printf("chipid2 = 0x%02x\n", in_8(&cpld_data->chipid2)); - printf("hwver = 0x%02x\n", in_8(&cpld_data->hwver)); - printf("cpldver = 0x%02x\n", in_8(&cpld_data->cpldver)); - printf("rstcon = 0x%02x\n", in_8(&cpld_data->rstcon)); - printf("flhcsr = 0x%02x\n", in_8(&cpld_data->flhcsr)); - printf("wdcsr = 0x%02x\n", in_8(&cpld_data->wdcsr)); - printf("wdkick = 0x%02x\n", in_8(&cpld_data->wdkick)); - printf("fancsr = 0x%02x\n", in_8(&cpld_data->fancsr)); - printf("ledcsr = 0x%02x\n", in_8(&cpld_data->ledcsr)); - printf("misc = 0x%02x\n", in_8(&cpld_data->misccsr)); - printf("bootor = 0x%02x\n", in_8(&cpld_data->bootor)); - printf("bootcfg1 = 0x%02x\n", in_8(&cpld_data->bootcfg1)); - printf("bootcfg2 = 0x%02x\n", in_8(&cpld_data->bootcfg2)); - printf("bootcfg3 = 0x%02x\n", in_8(&cpld_data->bootcfg3)); - printf("bootcfg4 = 0x%02x\n", in_8(&cpld_data->bootcfg4)); - putc('\n'); -} -#endif - -#ifndef CONFIG_SPL_BUILD -int cpld_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int rc = 0; - unsigned char value; - - if (argc <= 1) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "reset") == 0) { - if (!strcmp(argv[2], "altbank") && argv[3]) { - value = (u8)simple_strtoul(argv[3], NULL, 16); - cpld_set_altbank(value); - } else if (!argv[2]) - cpld_set_defbank(); - else - cmd_usage(cmdtp); -#ifdef DEBUG - } else if (strcmp(argv[1], "dump") == 0) { - cpld_dump_regs(); -#endif - } else - rc = cmd_usage(cmdtp); - - return rc; -} - -U_BOOT_CMD( - cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, - "Reset the board using the CPLD sequencer", - "reset - hard reset to default bank 4\n" - "cpld_cmd reset altbank [bank]- reset to alternate bank\n" - " - [bank] bank value select 1-4\n" - " - bank 1 on the flash 0x0000000~0x0ffffff\n" - " - bank 2 on the flash 0x1000000~0x1ffffff\n" - " - bank 3 on the flash 0x2000000~0x2ffffff\n" - " - bank 4 on the flash 0x3000000~0x3ffffff\n" -#ifdef DEBUG - "cpld_cmd dump - display the CPLD registers\n" -#endif - ); -#endif diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h deleted file mode 100644 index 02e9160854..0000000000 --- a/board/freescale/c29xpcie/cpld.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * Copyright 2013 Freescale Semiconductor - * Author: Mingkai Hu - * Po Liu - * - * This file provides support for the ngPIXIS, a board-specific FPGA used on - * some Freescale reference boards. - */ - -/* - * CPLD register set. Feel free to add board-specific #ifdefs where necessary. - */ -struct cpld_data { - u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ - u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ - u8 hwver; /* 0x2 - Hardware Version Register */ - u8 cpldver; /* 0x3 - Software Version Register */ - u8 res[12]; - u8 rstcon; /* 0x10 - Reset control register */ - u8 flhcsr; /* 0x11 - Flash control and status Register */ - u8 wdcsr; /* 0x12 - Watchdog control and status Register */ - u8 wdkick; /* 0x13 - Watchdog kick Register */ - u8 fancsr; /* 0x14 - Fan control and status Register */ - u8 ledcsr; /* 0x15 - LED control and status Register */ - u8 misccsr; /* 0x16 - Misc control and status Register */ - u8 bootor; /* 0x17 - Boot configure override Register */ - u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ - u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ - u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ - u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ -}; - -#define CPLD_BANKSEL_EN 0x02 -#define CPLD_BANKSEL_MASK 0x3f -#define CPLD_SELECT_BANK1 0xc0 -#define CPLD_SELECT_BANK2 0x80 -#define CPLD_SELECT_BANK3 0x40 -#define CPLD_SELECT_BANK4 0x00 diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c deleted file mode 100644 index 5795a27f65..0000000000 --- a/board/freescale/c29xpcie/ddr.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include - -#include "cpld.h" - -#define C29XPCIE_HARDWARE_REVA 0x40 -/* - * Micron MT41J128M16HA-15E - * */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 536870912u, - .capacity = 536870912u, - .primary_sdram_width = 32, - .ec_sdram_width = 8, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 2, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1650, - .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */ - .taa_ps = 14050, - .twr_ps = 15000, - .trcd_ps = 13500, - .trrd_ps = 75000, - .trp_ps = 13500, - .tras_ps = 40000, - .trc_ps = 49500, - .trfc_ps = 160000, - .twtr_ps = 75000, - .trtp_ps = 75000, - .refresh_rate_ps = 7800000, - .tfaw_ps = 30000, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - int i; - - popts->clk_adjust = 4; - popts->cpo_override = 0x1f; - popts->write_data_delay = 4; - popts->half_strength_driver_enable = 1; - popts->bstopre = 0x3cf; - popts->quad_rank_present = 1; - popts->rtt_override = 1; - popts->rtt_override_value = 1; - popts->dynamic_power = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x4; - popts->trwt_override = 1; - popts->trwt = 0; - - if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) - popts->ecc_mode = 0; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} - -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) -{ - int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd, - sizeof(generic_spd_eeprom_t)); - - if (ret) { - printf("DDR: failed to read SPD from address %u\n", - i2c_address); - memset(spd, 0, sizeof(generic_spd_eeprom_t)); - } -} diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c deleted file mode 100644 index 6d441d87a7..0000000000 --- a/board/freescale/c29xpcie/law.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, - LAW_TRGT_IF_PLATFORM_SRAM), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c deleted file mode 100644 index 421c2d4b1f..0000000000 --- a/board/freescale/c29xpcie/spl.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - bd_t *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - - /* relocate environment function pointers etc. */ - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_NAND_BOOT - puts("TPL\n"); -#else - puts("SPL\n"); -#endif - - nand_boot(); -} diff --git a/board/freescale/c29xpcie/spl_minimal.c b/board/freescale/c29xpcie/spl_minimal.c deleted file mode 100644 index 8193afdf6a..0000000000 --- a/board/freescale/c29xpcie/spl_minimal.c +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - - /* initialize selected port with appropriate baud rate */ - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - plat_ratio >>= 1; - gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - gd->bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot...\n"); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("SPL\n"); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c deleted file mode 100644 index ef844a0b3d..0000000000 --- a/board/freescale/c29xpcie/tlb.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - -#ifdef CONFIG_PCI - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256K, 1), -#endif -#endif - - SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64K, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, - CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, - CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256K, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, - CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_256M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_256M, 1), -#endif - -#ifdef CONFIG_SYS_INIT_L2_ADDR - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 12, BOOKE_PAGESZ_256K, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig deleted file mode 100644 index 1a6a9d4598..0000000000 --- a/board/freescale/mpc8536ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_MPC8536DS - -config SYS_BOARD - default "mpc8536ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "MPC8536DS" - -endif diff --git a/board/freescale/mpc8536ds/MAINTAINERS b/board/freescale/mpc8536ds/MAINTAINERS deleted file mode 100644 index 5ce5164e49..0000000000 --- a/board/freescale/mpc8536ds/MAINTAINERS +++ /dev/null @@ -1,9 +0,0 @@ -MPC8536DS BOARD -M: Priyanka Jain -S: Maintained -F: board/freescale/mpc8536ds/ -F: include/configs/MPC8536DS.h -F: configs/MPC8536DS_defconfig -F: configs/MPC8536DS_36BIT_defconfig -F: configs/MPC8536DS_SDCARD_defconfig -F: configs/MPC8536DS_SPIFLASH_defconfig diff --git a/board/freescale/mpc8536ds/Makefile b/board/freescale/mpc8536ds/Makefile deleted file mode 100644 index 6b936aa299..0000000000 --- a/board/freescale/mpc8536ds/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2008 Freescale Semiconductor. -# (C) Copyright 2001-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mpc8536ds.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/mpc8536ds/README b/board/freescale/mpc8536ds/README deleted file mode 100644 index 2a38bd6dda..0000000000 --- a/board/freescale/mpc8536ds/README +++ /dev/null @@ -1,127 +0,0 @@ -Overview: -========= - -The MPC8536E integrates a PowerPC processor core with system logic -required for imaging, networking, and communications applications. - -Boot from NAND: -=============== - -The MPC8536E is capable of booting from NAND flash which uses the image -u-boot-nand.bin. This image contains two parts: a first stage image(also -call 4K NAND loader and a second stage image. The former is appended to -the latter to produce u-boot-nand.bin. - -The bootup process can be divided into two stages: the first stage will -configure the L2SRAM, then copy the second stage image to L2SRAM and jump -to it. The second stage image is to configure all the hardware and boot up -to U-Boot command line. - -The 4K NAND loader's code comes from the corresponding nand_spl directory, -along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL -is mainly used to shrink the code size to the 4K size limitation. - -The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the -second stage image. It's set in the board config file when boot from NAND -is selected. - -Build and boot steps --------------------- - -1. Building image - make MPC8536DS_NAND_config - make CROSS_COMPILE=powerpc-none-linux-gnuspe- all - -2. Change dip-switch - SW2[5-8] = 1011 - SW9[1-3] = 101 - Note: 1 stands for 'on', 0 stands for 'off' - -3. Flash image - tftp 1000000 u-boot-nand.bin - nand erase 0 a0000 - nand write 1000000 0 a0000 - -Boot from On-chip ROM: -====================== - -The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC -and boot from eSPI. When power on, the porcessor excutes the ROM code to -initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from -the memory device that interfaced to the controller, such as the SDCard or -SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. - -The memory device should contain a specific data structure with control word -and config word at the fixed address. The config word direct the process how -to config the memory device, and the control word direct the processor where -to find the image on the memory device, or where copy the main image to. The -user can use any method to store the data structure to the memory device, only -if store it on the assigned address. - -Build and boot steps --------------------- - -For boot from eSDHC: -1. Build image - make MPC8536DS_SDCARD_config - make CROSS_COMPILE=powerpc-none-linux-gnuspe- all - -2. Change dip-switch - SW2[5-8] = 0111 - SW3[1] = 0 - SW8[7] = 0 - The on-board SD/MMC slot is active - SW8[7] = 1 - The externel SD/MMC slot is active - -3. Put image to SDCard - Put the follwing info at the assigned address on the SDCard: - - Offset | Data | Description - -------------------------------------------------------- - | 0x40-0x43 | 0x424F4F54 | BOOT signature | - -------------------------------------------------------- - | 0x48-0x4B | 0x00080000 | u-boot.bin's size | - -------------------------------------------------------- - | 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard | - -------------------------------------------------------- - | 0x58-0x5B | 0xF8F80000 | Target Address | - ------------------------------------------------------- - | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | - -------------------------------------------------------- - | 0x68-0x6B | 0x6 | Number of Config Addr/Data | - -------------------------------------------------------- - | 0x80-0x83 | 0xFF720100 | Config Addr 1 | - | 0x84-0x87 | 0xF8F80000 | Config Data 1 | - -------------------------------------------------------- - | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | - | 0x8c-0x8f | 0x0000000C | Config Data 2 | - -------------------------------------------------------- - | 0x90-0x93 | 0xFF720000 | Config Addr 3 | - | 0x94-0x97 | 0x80010000 | Config Data 3 | - -------------------------------------------------------- - | 0x98-0x9b | 0xFF72e40c | Config Addr 4 | - | 0x9c-0x9f | 0x00000040 | Config Data 4 | - -------------------------------------------------------- - | 0xa0-0xa3 | 0x40000001 | Config Addr 5 | - | 0xa4-0xa7 | 0x00000100 | Config Data 5 | - -------------------------------------------------------- - | 0xa8-0xab | 0x80000001 | Config Addr 6 | - | 0xac-0xaf | 0x80000001 | Config Data 6 | - -------------------------------------------------------- - | ...... | - -------------------------------------------------------- - | 0x???????? | u-boot.bin | - -------------------------------------------------------- - - then insert the SDCard to the active slot to boot up. - -For boot from eSPI: -1. Build image - make MPC8536DS_SPIFLASH_config - make CROSS_COMPILE=powerpc-none-linux-gnuspe- all - -2. Change dip-switch - SW2[5-8] = 0110 - -3. Put image to SPI flash - Put the info in the above table onto the SPI flash, then - boot up. diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c deleted file mode 100644 index 8319ae8245..0000000000 --- a/board/freescale/mpc8536ds/ddr.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2008 Freescale Semiconductor, Inc. - */ - -#include - -#include -#include - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for clock adjust: - * - number of chips on bus - * - position of slot - * - DDR1 vs. DDR2? - * - ??? - * - * This needs to be determined on a board-by-board basis. - * 0110 3/4 cycle late - * 0111 7/8 cycle late - */ - popts->clk_adjust = 7; - - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 10; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - - /* - * For wake up arp feature, we need enable auto self refresh - */ - popts->auto_self_refresh_en = 1; - popts->sr_it = 0x6; -} diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c deleted file mode 100644 index d59b12d82c..0000000000 --- a/board/freescale/mpc8536ds/law.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c deleted file mode 100644 index 5907a7b428..0000000000 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ /dev/null @@ -1,293 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/sgmii_riser.h" - -int board_early_init_f (void) -{ -#ifdef CONFIG_MMC - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | - MPC85xx_PMUXCR_SDHC_WP)); - - /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118, - * however, this erratum only applies to MPC8536 Rev1.0. - * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ - if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) && - (SVR_MIN(get_svr()) >= 0x1)) - || (SVR_MAJ(get_svr() & 0x7) > 0x1)) - setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); -#endif - return 0; -} - -int checkboard (void) -{ - u8 vboot; - u8 *pixis_base = (u8 *)PIXIS_BASE; - - printf("Board: MPC8536DS Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), - in_8(pixis_base + PIXIS_PVER)); - - vboot = in_8(pixis_base + PIXIS_VBOOT); - switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { - case PIXIS_VBOOT_LBMAP_NOR0: - puts ("vBank: 0\n"); - break; - case PIXIS_VBOOT_LBMAP_NOR1: - puts ("vBank: 1\n"); - break; - case PIXIS_VBOOT_LBMAP_NOR2: - puts ("vBank: 2\n"); - break; - case PIXIS_VBOOT_LBMAP_NOR3: - puts ("vBank: 3\n"); - break; - case PIXIS_VBOOT_LBMAP_PJET: - puts ("Promjet\n"); - break; - case PIXIS_VBOOT_LBMAP_NAND: - puts ("NAND\n"); - break; - } - - return 0; -} - -#if !defined(CONFIG_SPD_EEPROM) -/* - * Fixed sdram init -- doesn't use serial presence detect. - */ - -phys_size_t fixed_sdram (void) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - struct ccsr_ddr __iomem *ddr = &immap->im_ddr; - uint d_init; - - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; - - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; - -#if defined (CONFIG_DDR_ECC) - ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN; - ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS; - ddr->err_sbe = CONFIG_SYS_DDR_SBE; -#endif - asm("sync;isync"); - - udelay(500); - - ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - d_init = 1; - debug("DDR - 1st controller: memory initializing\n"); - /* - * Poll until memory is initialized. - * 512 Meg at 400 might hit this 200 times or so. - */ - while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { - udelay(1000); - } - debug("DDR: memory initialized\n\n"); - asm("sync; isync"); - udelay(500); -#endif - - return 512 * 1024 * 1024; -} - -#endif - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno; - - first_free_busno = fsl_pcie_init_board(0); - -#ifdef CONFIG_PCI1 - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - - pci_speed = 66666000; - pci_32 = 1; - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 1; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ - - return 0; -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].phyaddr = 0; - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - if (is_serdes_configured(SGMII_TSEC3)) { - puts("eTSEC3 is in sgmii mode.\n"); - tsec_info[num].phyaddr = 1; - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - -#ifdef CONFIG_FSL_SGMII_RISER - if (is_serdes_configured(SGMII_TSEC1) || - is_serdes_configured(SGMII_TSEC3)) { - fsl_sgmii_riser_init(tsec_info, num); - } -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - -#ifdef CONFIG_HAS_FSL_MPH_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - - return 0; -} -#endif diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c deleted file mode 100644 index 5df4788e0a..0000000000 --- a/board/freescale/mpc8536ds/tlb.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), - - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256K, 1), - - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_1M, 1), - -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA index 46c61237c7..0cb950d845 100644 --- a/board/freescale/p1010rdb/README.P1010RDB-PA +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -88,7 +88,7 @@ Note: 1 stands for 'on', 0 stands for 'off' Setting of hwconfig =================== If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example: setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig deleted file mode 100644 index f1792de8e3..0000000000 --- a/board/freescale/p1022ds/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P1022DS - -config SYS_BOARD - default "p1022ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P1022DS" - -endif diff --git a/board/freescale/p1022ds/MAINTAINERS b/board/freescale/p1022ds/MAINTAINERS deleted file mode 100644 index 62256c3703..0000000000 --- a/board/freescale/p1022ds/MAINTAINERS +++ /dev/null @@ -1,13 +0,0 @@ -P1022DS BOARD -M: Timur Tabi -S: Maintained -F: board/freescale/p1022ds/ -F: include/configs/P1022DS.h -F: configs/P1022DS_defconfig -F: configs/P1022DS_36BIT_defconfig -F: configs/P1022DS_36BIT_NAND_defconfig -F: configs/P1022DS_36BIT_SDCARD_defconfig -F: configs/P1022DS_36BIT_SPIFLASH_defconfig -F: configs/P1022DS_NAND_defconfig -F: configs/P1022DS_SDCARD_defconfig -F: configs/P1022DS_SPIFLASH_defconfig diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile deleted file mode 100644 index 699e5b5288..0000000000 --- a/board/freescale/p1022ds/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2010 Freescale Semiconductor, Inc. - -MINIMAL= - -ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_INIT_MINIMAL -MINIMAL=y -endif -endif - -ifdef MINIMAL -obj-y += spl_minimal.o -else -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -endif -obj-y += p1022ds.o -obj-y += ddr.o -obj-$(CONFIG_FSL_DIU_FB) += diu.o -endif - -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1022ds/README b/board/freescale/p1022ds/README deleted file mode 100644 index 04d9197074..0000000000 --- a/board/freescale/p1022ds/README +++ /dev/null @@ -1,23 +0,0 @@ -Overview --------- -P1022ds is a Low End Dual core platform supporting the P1022 processor -of QorIQ series. P1022 is an e500 based dual core SOC. - - -Pin Multiplex(hwconfig setting) -------------------------------- -Add the environment 'usb2', 'audclk' and 'tdm' to support pin multiplex -via hwconfig, i.e: -'setenv hwconfig usb2' to enable USB2 and disable eTsec2 -'setenv hwconfig tdm' to enable TDM and disable Audio -'setenv hwconfig audclk:12' to enable Audio(codec clock sources is 12MHz) - and disable TDM -'setenv hwconfig 'usb2;tdm' to enable USB2 and TDM, disable eTsec2 and Audio -'setenv hwconfig 'usb2;audclk:11' to enable USB2 and Audio(codec clock sources - is 11MHz), disable eTsec2 and TDM - -Warning: TDM and AUDIO can not enable simultaneous ! -and AUDIO codec clock sources only setting as 11MHz or 12MHz ! -'setenv hwconfig 'audclk:12;tdm' --- error ! -'setenv hwconfig 'audclk:11;tdm' --- error ! -'setenv hwconfig 'audclk:10' --- error ! diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c deleted file mode 100644 index 70932115f4..0000000000 --- a/board/freescale/p1022ds/ddr.c +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#include - -#include -#include - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 clk_adjust; /* Range: 0-8 */ - u32 cpo; /* Range: 2-31 */ - u32 write_data_delay; /* Range: 0-6 */ - u32 force_2t; -}; - -/* - * This table contains all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ -static const struct board_specific_parameters dimm0[] = { - /* - * memory controller 0 - * num| hi| clk| cpo|wrdata|2T - * ranks| mhz|adjst| | delay| - */ - {1, 549, 5, 31, 3, 0}, - {1, 850, 5, 31, 5, 0}, - {2, 549, 5, 31, 3, 0}, - {2, 850, 5, 31, 5, 0}, - {} -}; - -void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - unsigned long ddr_freq; - unsigned int i; - - - if (ctrl_num) { - printf("Wrong parameter for controller number %d", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* set odt_rd_cfg and odt_wr_cfg. */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = 0; - popts->cs_local_opts[i].odt_wr_cfg = 1; - } - - pbsp = dimm0; - /* - * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s!\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp->clk_adjust; - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = pbsp->write_data_delay; - popts->twot_en = pbsp->force_2t; - } else { - panic("DIMM is not supported by this board"); - } - -found: - popts->half_strength_driver_enable = 1; - - /* Per AN4039, enable ZQ calibration. */ - popts->zq_en = 1; - - /* - * For wake-up on ARP, we need auto self refresh enabled - */ - popts->auto_self_refresh_en = 1; - popts->sr_it = 0xb; -} diff --git a/board/freescale/p1022ds/diu.c b/board/freescale/p1022ds/diu.c deleted file mode 100644 index 918b4b9f6a..0000000000 --- a/board/freescale/p1022ds/diu.c +++ /dev/null @@ -1,478 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Authors: Timur Tabi - * - * FSL DIU Framebuffer driver - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/ngpixis.h" -#include - -/* The CTL register is called 'csr' in the ngpixis_t structure */ -#define PX_CTL_ALTACC 0x80 - -#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0 -#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00 -#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0 -#define PX_BRDCFG0_ELBC_DIU 0x02 - -#define PX_BRDCFG1_DVIEN 0x80 -#define PX_BRDCFG1_DFPEN 0x40 -#define PX_BRDCFG1_BACKLIGHT 0x20 - -#define PMUXCR_ELBCDIU_MASK 0xc0000000 -#define PMUXCR_ELBCDIU_NOR16 0x80000000 -#define PMUXCR_ELBCDIU_DIU 0x40000000 - -/* - * DIU Area Descriptor - * - * Note that we need to byte-swap the value before it's written to the AD - * register. So even though the registers don't look like they're in the same - * bit positions as they are on the MPC8610, the same value is written to the - * AD register on the MPC8610 and on the P1022. - */ -#define AD_BYTE_F 0x10000000 -#define AD_ALPHA_C_SHIFT 25 -#define AD_BLUE_C_SHIFT 23 -#define AD_GREEN_C_SHIFT 21 -#define AD_RED_C_SHIFT 19 -#define AD_PIXEL_S_SHIFT 16 -#define AD_COMP_3_SHIFT 12 -#define AD_COMP_2_SHIFT 8 -#define AD_COMP_1_SHIFT 4 -#define AD_COMP_0_SHIFT 0 - -/* - * Variables used by the DIU/LBC switching code. It's safe to makes these - * global, because the DIU requires DDR, so we'll only run this code after - * relocation. - */ -static u8 px_brdcfg0; -static u32 pmuxcr; -static void *lbc_lcs0_ba; -static void *lbc_lcs1_ba; -static u32 old_br0, old_or0, old_br1, old_or1; -static u32 new_br0, new_or0, new_br1, new_or1; - -void diu_set_pixel_clock(unsigned int pixclock) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - unsigned long speed_ccb, temp; - u32 pixval; - - speed_ccb = get_bus_freq(0); - temp = 1000000000 / pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - debug("DIU pixval = %u\n", pixval); - - /* Modify PXCLK in GUTS CLKDVDR */ - temp = in_be32(&gur->clkdvdr) & 0x2000FFFF; - out_be32(&gur->clkdvdr, temp); /* turn off clock */ - out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16)); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - const char *name; - u32 pixel_format; - u8 temp; - phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */ - - /* - * Indirect mode requires both BR0 and BR1 to be set to "GPCM", - * otherwise writes to these addresses won't actually appear on the - * local bus, and so the PIXIS won't see them. - * - * In FCM mode, writes go to the NAND controller, which does not pass - * them to the localbus directly. So we force BR0 and BR1 into GPCM - * mode, since we don't care about what's behind the localbus any - * more. However, we save those registers first, so that we can - * restore them when necessary. - */ - new_br0 = old_br0 = get_lbc_br(0); - new_br1 = old_br1 = get_lbc_br(1); - new_or0 = old_or0 = get_lbc_or(0); - new_or1 = old_or1 = get_lbc_or(1); - - /* - * Use the existing BRx/ORx values if it's already GPCM. Otherwise, - * force the values to simple 32KB GPCM windows with the most - * conservative timing. - */ - if ((old_br0 & BR_MSEL) != BR_MS_GPCM) { - new_br0 = (get_lbc_br(0) & BR_BA) | BR_V; - new_or0 = OR_AM_32KB | 0xFF7; - set_lbc_br(0, new_br0); - set_lbc_or(0, new_or0); - } - if ((old_br1 & BR_MSEL) != BR_MS_GPCM) { - new_br1 = (get_lbc_br(1) & BR_BA) | BR_V; - new_or1 = OR_AM_32KB | 0xFF7; - set_lbc_br(1, new_br1); - set_lbc_or(1, new_or1); - } - - /* - * Determine the physical addresses for Chip Selects 0 and 1. The - * BR0/BR1 registers contain the truncated physical addresses for the - * chip selects, mapped via the localbus LAW. Since the BRx registers - * only contain the lower 32 bits of the address, we have to determine - * the upper 4 bits some other way. The proper way is to scan the LAW - * table looking for a matching localbus address. Instead, we cheat. - * We know that the upper bits are 0 for 32-bit addressing, or 0xF for - * 36-bit addressing. - */ -#ifdef CONFIG_PHYS_64BIT - phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA); - phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA); -#else - phys0 = old_br0 & old_or0 & BR_BA; - phys1 = old_br1 & old_or1 & BR_BA; -#endif - - /* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */ - lbc_lcs0_ba = map_physmem(phys0, 1, 0); - lbc_lcs1_ba = map_physmem(phys1, 1, 0); - - pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | - (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | - (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | - (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | - (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); - - temp = in_8(&pixis->brdcfg1); - - if (strncmp(port, "lvds", 4) == 0) { - /* Single link LVDS */ - temp &= ~PX_BRDCFG1_DVIEN; - /* - * LVDS also needs backlight enabled, otherwise the display - * will be blank. - */ - temp |= (PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); - name = "Single-Link LVDS"; - } else { /* DVI */ - /* Enable the DVI port, disable the DFP and the backlight */ - temp &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT); - temp |= PX_BRDCFG1_DVIEN; - name = "DVI"; - } - - printf("DIU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - out_8(&pixis->brdcfg1, temp); - - /* - * Enable PIXIS indirect access mode. This is a hack that allows us to - * access PIXIS registers even when the LBC pins have been muxed to the - * DIU. - */ - setbits_8(&pixis->csr, PX_CTL_ALTACC); - - /* - * Route the LAD pins to the DIU. This will disable access to the eLBC, - * which means we won't be able to read/write any NOR flash addresses! - */ - out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); - px_brdcfg0 = in_8(lbc_lcs1_ba); - out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); - in_8(lbc_lcs1_ba); - - /* Set PMUXCR to switch the muxed pins from the LBC to the DIU */ - clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU); - pmuxcr = in_be32(&gur->pmuxcr); - - return fsl_diu_init(xres, yres, pixel_format, 0); -} - -/* - * set_mux_to_lbc - disable the DIU so that we can read/write to elbc - * - * On the Freescale P1022, the DIU video signal and the LBC address/data lines - * share the same pins, which means that when the DIU is active (e.g. the - * console is on the DVI display), NOR flash cannot be accessed. So we use the - * weak accessor feature of the CFI flash code to temporarily switch the pin - * mux from DIU to LBC whenever we want to read or write flash. This has a - * significant performance penalty, but it's the only way to make it work. - * - * There are two muxes: one on the chip, and one on the board. The chip mux - * controls whether the pins are used for the DIU or the LBC, and it is - * set via PMUXCR. The board mux controls whether those signals go to - * the video connector or the NOR flash chips, and it is set via the ngPIXIS. - */ -static int set_mux_to_lbc(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Switch the muxes only if they're currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != - PMUXCR_ELBCDIU_NOR16) { - /* - * In DIU mode, the PIXIS can only be accessed indirectly - * since we can't read/write the LBC directly. - */ - /* Set the board mux to LBC. This will disable the display. */ - out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); - out_8(lbc_lcs1_ba, px_brdcfg0); - in_8(lbc_lcs1_ba); - - /* Disable indirect PIXIS mode */ - out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr)); - clrbits_8(lbc_lcs1_ba, PX_CTL_ALTACC); - - /* Set the chip mux to LBC mode, so that writes go to flash. */ - out_be32(&gur->pmuxcr, (pmuxcr & ~PMUXCR_ELBCDIU_MASK) | - PMUXCR_ELBCDIU_NOR16); - in_be32(&gur->pmuxcr); - - /* Restore the BR0 and BR1 settings */ - set_lbc_br(0, old_br0); - set_lbc_or(0, old_or0); - set_lbc_br(1, old_br1); - set_lbc_or(1, old_or1); - - return 1; - } - - return 0; -} - -/* - * set_mux_to_diu - re-enable the DIU muxing - * - * This function restores the chip and board muxing to point to the DIU. - */ -static void set_mux_to_diu(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Set BR0 and BR1 to GPCM mode */ - set_lbc_br(0, new_br0); - set_lbc_or(0, new_or0); - set_lbc_br(1, new_br1); - set_lbc_or(1, new_or1); - - /* Enable indirect PIXIS mode */ - setbits_8(&pixis->csr, PX_CTL_ALTACC); - - /* Set the board mux to DIU. This will enable the display. */ - out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0)); - out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU); - in_8(lbc_lcs1_ba); - - /* Set the chip mux to DIU mode. */ - out_be32(&gur->pmuxcr, pmuxcr); - in_be32(&gur->pmuxcr); -} - -/* - * pixis_read - board-specific function to read from the PIXIS - * - * This function overrides the generic pixis_read() function, so that it can - * use PIXIS indirect mode if necessary. - */ -u8 pixis_read(unsigned int reg) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Use indirect mode if the mux is currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != - PMUXCR_ELBCDIU_NOR16) { - out_8(lbc_lcs0_ba, reg); - return in_8(lbc_lcs1_ba); - } else { - void *p = (void *)PIXIS_BASE; - - return in_8(p + reg); - } -} - -/* - * pixis_write - board-specific function to write to the PIXIS - * - * This function overrides the generic pixis_write() function, so that it can - * use PIXIS indirect mode if necessary. - */ -void pixis_write(unsigned int reg, u8 value) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Use indirect mode if the mux is currently set to DIU mode */ - if ((in_be32(&gur->pmuxcr) & PMUXCR_ELBCDIU_MASK) != - PMUXCR_ELBCDIU_NOR16) { - out_8(lbc_lcs0_ba, reg); - out_8(lbc_lcs1_ba, value); - /* Do a read-back to ensure the write completed */ - in_8(lbc_lcs1_ba); - } else { - void *p = (void *)PIXIS_BASE; - - out_8(p + reg, value); - } -} - -void pixis_bank_reset(void) -{ - /* - * For some reason, a PIXIS bank reset does not work if the PIXIS is - * in indirect mode, so switch to direct mode first. - */ - set_mux_to_lbc(); - - out_8(&pixis->vctl, 0); - out_8(&pixis->vctl, 1); - - while (1); -} - -#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - -void flash_write8(u8 value, void *addr) -{ - int sw = set_mux_to_lbc(); - - __raw_writeb(value, addr); - if (sw) { - /* - * To ensure the post-write is completed to eLBC, software must - * perform a dummy read from one valid address from eLBC space - * before changing the eLBC_DIU from NOR mode to DIU mode. - * set_mux_to_diu() includes a sync that will ensure the - * __raw_readb() completes before it switches the mux. - */ - __raw_readb(addr); - set_mux_to_diu(); - } -} - -void flash_write16(u16 value, void *addr) -{ - int sw = set_mux_to_lbc(); - - __raw_writew(value, addr); - if (sw) { - /* - * To ensure the post-write is completed to eLBC, software must - * perform a dummy read from one valid address from eLBC space - * before changing the eLBC_DIU from NOR mode to DIU mode. - * set_mux_to_diu() includes a sync that will ensure the - * __raw_readb() completes before it switches the mux. - */ - __raw_readb(addr); - set_mux_to_diu(); - } -} - -void flash_write32(u32 value, void *addr) -{ - int sw = set_mux_to_lbc(); - - __raw_writel(value, addr); - if (sw) { - /* - * To ensure the post-write is completed to eLBC, software must - * perform a dummy read from one valid address from eLBC space - * before changing the eLBC_DIU from NOR mode to DIU mode. - * set_mux_to_diu() includes a sync that will ensure the - * __raw_readb() completes before it switches the mux. - */ - __raw_readb(addr); - set_mux_to_diu(); - } -} - -void flash_write64(u64 value, void *addr) -{ - int sw = set_mux_to_lbc(); - uint32_t *p = addr; - - /* - * There is no __raw_writeq(), so do the write manually. We don't trust - * the compiler, so we use inline assembly. - */ - __asm__ __volatile__( - "stw%U0%X0 %2,%0;\n" - "stw%U1%X1 %3,%1;\n" - : "=m" (*p), "=m" (*(p + 1)) - : "r" ((uint32_t) (value >> 32)), "r" ((uint32_t) (value))); - - if (sw) { - /* - * To ensure the post-write is completed to eLBC, software must - * perform a dummy read from one valid address from eLBC space - * before changing the eLBC_DIU from NOR mode to DIU mode. We - * read addr+4 because we just wrote to addr+4, so that's how we - * maintain execution order. set_mux_to_diu() includes a sync - * that will ensure the __raw_readb() completes before it - * switches the mux. - */ - __raw_readb(addr + 4); - set_mux_to_diu(); - } -} - -u8 flash_read8(void *addr) -{ - u8 ret; - - int sw = set_mux_to_lbc(); - - ret = __raw_readb(addr); - if (sw) - set_mux_to_diu(); - - return ret; -} - -u16 flash_read16(void *addr) -{ - u16 ret; - - int sw = set_mux_to_lbc(); - - ret = __raw_readw(addr); - if (sw) - set_mux_to_diu(); - - return ret; -} - -u32 flash_read32(void *addr) -{ - u32 ret; - - int sw = set_mux_to_lbc(); - - ret = __raw_readl(addr); - if (sw) - set_mux_to_diu(); - - return ret; -} - -u64 flash_read64(void *addr) -{ - u64 ret; - - int sw = set_mux_to_lbc(); - - /* There is no __raw_readq(), so do the read manually */ - ret = *(volatile u64 *)addr; - if (sw) - set_mux_to_diu(); - - return ret; -} - -#endif diff --git a/board/freescale/p1022ds/law.c b/board/freescale/p1022ds/law.c deleted file mode 100644 index 079095d008..0000000000 --- a/board/freescale/p1022ds/law.c +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c deleted file mode 100644 index d10160d17a..0000000000 --- a/board/freescale/p1022ds/p1022ds.c +++ /dev/null @@ -1,364 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/ngpixis.h" - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, 0x1000); -#ifdef CONFIG_SYS_RAMBOOT - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); -#endif - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - - /* Set the pin muxing to enable ETSEC2. */ - clrbits_be32(&gur->pmuxcr2, 0x001F8000); - - /* Enable the SPI */ - clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); - - return 0; -} - -int checkboard(void) -{ - u8 sw; - - printf("Board: P1022DS Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", - in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); - - sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); - - switch ((sw & PIXIS_LBMAP_MASK) >> 6) { - case 0: - printf ("vBank: %u\n", ((sw & 0x30) >> 4)); - break; - case 1: - printf ("NAND\n"); - break; - case 2: - case 3: - puts ("Promjet\n"); - break; - } - - return 0; -} - -#define CONFIG_TFP410_I2C_ADDR 0x38 - -/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ -#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK 0x0c -#define CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK 0x03 - -/* Route the I2C1 pins to the SSI port instead. */ -#define CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI 0x08 - -/* Choose the 12.288Mhz codec reference clock */ -#define CONFIG_PIXIS_BRDCFG1_AUDCLK_12 0x02 - -/* Choose the 11.2896Mhz codec reference clock */ -#define CONFIG_PIXIS_BRDCFG1_AUDCLK_11 0x01 - -/* Connect to USB2 */ -#define CONFIG_PIXIS_BRDCFG0_USB2 0x10 -/* Connect to TFM bus */ -#define CONFIG_PIXIS_BRDCFG1_TDM 0x0c -/* Connect to SPI */ -#define CONFIG_PIXIS_BRDCFG0_SPI 0x80 - -int misc_init_r(void) -{ - u8 temp; - const char *audclk; - size_t arglen; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - /* For DVI, enable the TFP410 Encoder. */ - - temp = 0xBF; - if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) - return -1; - if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x08, 1, &temp, sizeof(temp)) < 0) - return -1; - debug("DVI Encoder Read: 0x%02x\n", temp); - - temp = 0x10; - if (i2c_write(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) - return -1; - if (i2c_read(CONFIG_TFP410_I2C_ADDR, 0x0A, 1, &temp, sizeof(temp)) < 0) - return -1; - debug("DVI Encoder Read: 0x%02x\n",temp); - - /* Enable the USB2 in PMUXCR2 and FGPA */ - if (hwconfig("usb2")) { - clrsetbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_ETSECUSB_MASK, - MPC85xx_PMUXCR2_USB); - setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_USB2); - } - - /* tdm and audio can not enable simultaneous*/ - if (hwconfig("tdm") && hwconfig("audclk")){ - printf("WARNING: TDM and AUDIO can not be enabled simultaneous !\n"); - return -1; - } - - /* Enable the TDM in PMUXCR and FGPA */ - if (hwconfig("tdm")) { - clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_MASK, - MPC85xx_PMUXCR_TDM); - setbits_8(&pixis->brdcfg1, CONFIG_PIXIS_BRDCFG1_TDM); - /* TDM need some configration option by SPI */ - clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SPI_MASK, - MPC85xx_PMUXCR_SPI); - setbits_8(&pixis->brdcfg0, CONFIG_PIXIS_BRDCFG0_SPI); - } - - /* - * Enable the reference clock for the WM8776 codec, and route the MUX - * pins for SSI. The default is the 12.288 MHz clock - */ - - if (hwconfig("audclk")) { - temp = in_8(&pixis->brdcfg1) & ~(CONFIG_PIXIS_BRDCFG1_SSI_TDM_MASK | - CONFIG_PIXIS_BRDCFG1_AUDCLK_MASK); - temp |= CONFIG_PIXIS_BRDCFG1_SSI_TDM_SSI; - - audclk = hwconfig_arg("audclk", &arglen); - /* Check the first two chars only */ - if (audclk && (strncmp(audclk, "11", 2) == 0)) - temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_11; - else - temp |= CONFIG_PIXIS_BRDCFG1_AUDCLK_12; - setbits_8(&pixis->brdcfg1, temp); - } - - return 0; -} - -/* - * A list of PCI and SATA slots - */ -enum slot_id { - SLOT_PCIE1 = 1, - SLOT_PCIE2, - SLOT_PCIE3, - SLOT_PCIE4, - SLOT_PCIE5, - SLOT_SATA1, - SLOT_SATA2 -}; - -/* - * This array maps the slot identifiers to their names on the P1022DS board. - */ -static const char *slot_names[] = { - [SLOT_PCIE1] = "Slot 1", - [SLOT_PCIE2] = "Slot 2", - [SLOT_PCIE3] = "Slot 3", - [SLOT_PCIE4] = "Slot 4", - [SLOT_PCIE5] = "Mini-PCIe", - [SLOT_SATA1] = "SATA 1", - [SLOT_SATA2] = "SATA 2", -}; - -/* - * This array maps a given SERDES configuration and SERDES device to the PCI or - * SATA slot that it connects to. This mapping is hard-coded in the FPGA. - */ -static u8 serdes_dev_slot[][SATA2 + 1] = { - [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 }, - [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4, - [PCIE2] = SLOT_PCIE5 }, - [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, - [PCIE2] = SLOT_PCIE3, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2, - [PCIE2] = SLOT_PCIE3 }, - [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3, - [PCIE2] = SLOT_PCIE3, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x1c] = { [PCIE1] = SLOT_PCIE1, - [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 }, - [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 }, - [0x1f] = { [PCIE1] = SLOT_PCIE1 }, -}; - - -/* - * Returns the name of the slot to which the PCIe or SATA controller is - * connected - */ -const char *board_serdes_name(enum srds_prtcl device) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - u32 pordevsr = in_be32(&gur->pordevsr); - unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> - MPC85xx_PORDEVSR_IO_SEL_SHIFT; - enum slot_id slot = serdes_dev_slot[srds_cfg][device]; - const char *name = slot_names[slot]; - - if (name) - return name; - else - return "Nothing"; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -/* - * Initialize on-board and/or PCI Ethernet devices - * - * Returns: - * <0, error - * 0, no ethernet devices found - * >0, number of ethernet devices initialized - */ -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[2]; - unsigned int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - num++; -#endif - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis); -} - -#ifdef CONFIG_OF_BOARD_SETUP -/** - * ft_codec_setup - fix up the clock-frequency property of the codec node - * - * Update the clock-frequency property based on the value of the 'audclk' - * hwconfig option. If audclk is not specified, then don't write anything - * to the device tree, because it means that the codec clock is disabled. - */ -static void ft_codec_setup(void *blob, const char *compatible) -{ - const char *audclk; - size_t arglen; - u32 freq; - - audclk = hwconfig_arg("audclk", &arglen); - if (audclk) { - if (strncmp(audclk, "11", 2) == 0) - freq = 11289600; - else - freq = 12288000; - - do_fixup_by_compat_u32(blob, compatible, "clock-frequency", - freq, 1); - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_FSL_SGMII_RISER - fsl_sgmii_riser_fdt_fixup(blob); -#endif - - /* Update the WM8776 node's clock frequency property */ - ft_codec_setup(blob, "wlf,wm8776"); - - return 0; -} -#endif diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c deleted file mode 100644 index 39e1bee6f3..0000000000 --- a/board/freescale/p1022ds/spl.c +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/ngpixis.h" -#include -#include -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -static const u32 sysclk_tbl[] = { - 66666000, 7499900, 83332500, 8999900, - 99999000, 11111000, 12499800, 13333200 -}; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L2_SIZE; -} - -void board_init_f(ulong bootflag) -{ - int px_spd; - u32 plat_ratio, sys_clk, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - - console_init_f(); - - /* Set pmuxcr to allow both i2c1 and i2c2 */ - setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); - setbits_be32(&gur->pmuxcr, - in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); - -#ifdef CONFIG_SPL_SPI_BOOT - /* Enable the SPI */ - clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); -#endif - - /* Read back the register to synchronize the write. */ - in_be32(&gur->pmuxcr); - - /* initialize selected port with appropriate baud rate */ - px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); - sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - bus_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI Flash boot...\n"); -#endif - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *)CONFIG_SPL_GD_ADDR; - bd_t *bd; - - memset(gd, 0, sizeof(gd_t)); - bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; - bd->bi_memsize = CONFIG_SYS_L2_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; -#ifndef CONFIG_SPL_NAND_BOOT - env_init(); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); -#endif - /* relocate environment function pointers etc. */ -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; -#else - env_relocate(); -#endif - -#ifdef CONFIG_SYS_I2C - i2c_init_all(); -#else - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif - - dram_init(); -#ifdef CONFIG_SPL_NAND_BOOT - puts("Tertiary program loader running in sram..."); -#else - puts("Second program loader running in sram...\n"); -#endif - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c deleted file mode 100644 index 31de26318d..0000000000 --- a/board/freescale/p1022ds/spl_minimal.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2011 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include - - -const static u32 sysclk_tbl[] = { - 66666000, 7499900, 83332500, 8999900, - 99999000, 11111000, 12499800, 13333200 -}; - -void board_init_f(ulong bootflag) -{ - int px_spd; - u32 plat_ratio, sys_clk, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) - set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); - set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); -#endif - /* for FPGA */ - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); - - /* initialize selected port with appropriate baud rate */ - px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); - sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; - plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; - bus_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - bus_clk / 16 / CONFIG_BAUDRATE); - - puts("\nNAND boot... "); - - /* copy code to RAM and jump to it - this should not return */ - /* NOTE - code has to be copied out of NAND buffer before - * other blocks can be read. - */ - relocate_code(CONFIG_SPL_RELOC_STACK, 0, - CONFIG_SPL_RELOC_TEXT_BASE); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - puts("\nSecond program loader running in sram..."); - nand_boot(); -} - -void putc(char c) -{ - if (c == '\n') - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); - - NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); -} - -void puts(const char *str) -{ - while (*str) - putc(*str++); -} diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c deleted file mode 100644 index 194fbd5afc..0000000000 --- a/board/freescale/p1022ds/tlb.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2010 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - /* W**G* - Flash/promjet, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), -#endif - - SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4K, 1), - -#if defined(CONFIG_SYS_RAMBOOT) || \ - (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* **** - eSDHC/eSPI/NAND boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), - /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_1G, 1), -#endif - -#ifdef CONFIG_SYS_NAND_BASE - /* *I*G - NAND */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16K, 1), -#endif - -#ifdef CONFIG_SYS_INIT_L2_ADDR - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 11, BOOKE_PAGESZ_256K, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig deleted file mode 100644 index 8f9a8d4415..0000000000 --- a/board/freescale/p1_twr/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P1_TWR - -config SYS_BOARD - default "p1_twr" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "p1_twr" - -endif diff --git a/board/freescale/p1_twr/MAINTAINERS b/board/freescale/p1_twr/MAINTAINERS deleted file mode 100644 index 0f9f98f459..0000000000 --- a/board/freescale/p1_twr/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -P1_TWR BOARD -M: Xiaobo Xie -S: Maintained -F: board/freescale/p1_twr/ -F: include/configs/p1_twr.h -F: configs/TWR-P1025_defconfig diff --git a/board/freescale/p1_twr/Makefile b/board/freescale/p1_twr/Makefile deleted file mode 100644 index 5e6c658551..0000000000 --- a/board/freescale/p1_twr/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. -# - -obj-y += p1_twr.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c deleted file mode 100644 index 85f1f6344a..0000000000 --- a/board/freescale/p1_twr/ddr.c +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Fixed sdram init -- doesn't use serial presence detect. */ -phys_size_t fixed_sdram(void) -{ - sys_info_t sysinfo; - char buf[32]; - size_t ddr_size; - fsl_ddr_cfg_regs_t ddr_cfg_regs = { - .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, - .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, - .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, -#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 - .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS, - .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG, - .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2, -#endif - .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3, - .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0, - .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, - .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, - .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, - .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, - .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1, - .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2, - .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, - .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL, - .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT, - .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL, - .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, - .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, - .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, - .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, - .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, - .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL, - .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, - .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, - .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 - }; - - get_sys_info(&sysinfo); - printf("Configuring DDR for %s MT/s data rate\n", - strmhz(buf, sysinfo.freq_ddrbus)); - - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; - - fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - ddr_size, LAW_TRGT_IF_DDR_1) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; - - return ddr_size; -} diff --git a/board/freescale/p1_twr/law.c b/board/freescale/p1_twr/law.c deleted file mode 100644 index 45721f6140..0000000000 --- a/board/freescale/p1_twr/law.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_SSD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC) -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c deleted file mode 100644 index 8e1522a604..0000000000 --- a/board/freescale/p1_twr/p1_twr.c +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SYSCLK_64 64000000 -#define SYSCLK_66 66666666 - -unsigned long get_board_sys_clk(ulong dummy) -{ - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); - unsigned int cpdat_val = 0; - - /* Set-up up pin muxing based on board switch settings */ - cpdat_val = par_io[1].cpdat; - - /* Check switch setting for SYSCLK select (PB3) */ - if (cpdat_val & 0x10000000) - return SYSCLK_64; - else - return SYSCLK_66; - - return 0; -} - -#ifdef CONFIG_QE - -#define PCA_IOPORT_I2C_ADDR 0x23 -#define PCA_IOPORT_OUTPUT_CMD 0x2 -#define PCA_IOPORT_CFG_CMD 0x6 - -const qe_iop_conf_t qe_iop_conf_tab[] = { - -#ifdef CONFIG_TWR_P1025 - /* GPIO */ - {1, 0, 1, 0, 0}, - {1, 18, 1, 0, 0}, - - /* GPIO for switch options */ - {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */ - {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */ - {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */ - {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */ - - /* QE_MUX_MDC */ - {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ - - /* QE_MUX_MDIO */ - {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ - - /* UCC_1_MII */ - {0, 23, 2, 0, 2}, /* CLK12 */ - {0, 24, 2, 0, 1}, /* CLK9 */ - {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ - {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ - {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ - {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ - {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ - {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ - {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ - {0, 17, 2, 0, 2}, /* ENET1_CRS */ - {0, 16, 2, 0, 2}, /* ENET1_COL */ - - /* UCC_5_RMII */ - {1, 11, 2, 0, 1}, /* CLK13 */ - {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ - {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ - {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ - {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ - {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ - {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ - {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ - - /* TDMA - clock option is configured in OS based on board setting */ - {1, 23, 2, 0, 2}, /* TDMA_TXD */ - {1, 25, 2, 0, 2}, /* TDMA_RXD */ - {1, 26, 1, 0, 2}, /* TDMA_SYNC */ -#endif - - {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ -}; -#endif - -int board_early_init_f(void) -{ - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); - - /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */ - clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); - - return 0; -} - -int checkboard(void) -{ - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u8 boot_status; - - printf("Board: %s\n", CONFIG_BOARDNAME); - - boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf; - puts("rom_loc: "); - if (boot_status == PORBMSR_ROMLOC_NOR) - puts("nor flash"); - else if (boot_status == PORBMSR_ROMLOC_SDHC) - puts("sd"); - else - puts("unknown"); - puts("\n"); - - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ - 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */ - return 0; -} - -int board_eth_init(bd_t *bis) -{ - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - ccsr_gur_t *gur __attribute__((unused)) = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - printf("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - num++; -#endif - - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); - -#if defined(CONFIG_UEC_ETH) - /* QE0 and QE3 need to be exposed for UCC1 - * and UCC5 Eth mode (in PMUXCR register). - * Currently QE/LBC muxed pins assumed to be - * LBC for U-Boot and PMUXCR updated by OS if required */ - - uec_standard_init(bis); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_QE) -static void fdt_board_fixup_qe_pins(void *blob) -{ - int node; - - if (!hwconfig("qe")) { - /* For QE and eLBC pins multiplexing, - * When don't use QE function, remove - * qe node from dt blob. - */ - node = fdt_path_offset(blob, "/qe"); - if (node >= 0) - fdt_del_node(blob, node); - } else { - /* For TWR Peripheral Modules - TWR-SER2 - * board only can support Signal Port MII, - * so delete one UEC node when use MII port. - */ - if (hwconfig("mii")) - node = fdt_path_offset(blob, "/qe/ucc@2400"); - else - node = fdt_path_offset(blob, "/qe/ucc@2000"); - if (node >= 0) - fdt_del_node(blob, node); - } - - return; -} -#endif - -#ifdef CONFIG_OF_BOARD_SETUP -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - FT_FSL_PCI_SETUP; - -#ifdef CONFIG_QE - do_fixup_by_compat(blob, "fsl,qe", "status", "okay", - sizeof("okay"), 0); -#endif -#if defined(CONFIG_TWR_P1025) - fdt_board_fixup_qe_pins(blob); -#endif - fsl_fdt_fixup_dr_usb(blob, bd); - - return 0; -} -#endif diff --git a/board/freescale/p1_twr/tlb.c b/board/freescale/p1_twr/tlb.c deleted file mode 100644 index 8e403e3e44..0000000000 --- a/board/freescale/p1_twr/tlb.c +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_1M, 1), - -#ifndef CONFIG_SPL_BUILD - /* W**G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_64M, 1), - - /* W**G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_SSD_BASE, CONFIG_SYS_SSD_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_1M, 1), - -#ifdef CONFIG_PCI - /* *I*G* - PCI memory 1.5G */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O effective: 192K */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), -#endif - -#endif - -#ifdef CONFIG_SYS_RAMBOOT - /* *I*G - eSDHC boot */ - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 8, BOOKE_PAGESZ_1G, 1), -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig deleted file mode 100644 index 87818a8d3a..0000000000 --- a/board/freescale/t102xqds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_T1024QDS - -config SYS_BOARD - default "t102xqds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T102xQDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/t102xqds/MAINTAINERS b/board/freescale/t102xqds/MAINTAINERS deleted file mode 100644 index 7e30e5f84b..0000000000 --- a/board/freescale/t102xqds/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -T102XQDS BOARD -#M: Shengzhou Liu -S: Orphan (since 2018-05) -F: board/freescale/t102xqds/ -F: include/configs/T102xQDS.h -F: configs/T1024QDS_defconfig -F: configs/T1024QDS_NAND_defconfig -F: configs/T1024QDS_SDCARD_defconfig -F: configs/T1024QDS_SPIFLASH_defconfig -F: configs/T1024QDS_DDR4_defconfig -F: configs/T1024QDS_SECURE_BOOT_defconfig -F: configs/T1024QDS_DDR4_SECURE_BOOT_defconfig diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile deleted file mode 100644 index ae872b46c3..0000000000 --- a/board/freescale/t102xqds/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2014 Freescale Semiconductor, Inc. - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-y += t102xqds.o -obj-y += eth_t102xqds.o -obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o -endif -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t102xqds/README b/board/freescale/t102xqds/README deleted file mode 100644 index c00e3bafbe..0000000000 --- a/board/freescale/t102xqds/README +++ /dev/null @@ -1,328 +0,0 @@ -T1024 SoC Overview ------------------- -The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor -combines two or one 64-bit Power Architecture e5500 core respectively with high -performance datapath acceleration logic, and network peripheral bus interfaces -required for networking and telecommunications. This processor can be used in -applications such as enterprise WLAN access points, routers, switches, firewall -and other packet processing intensive small enterprise and branch office appliances, -and general-purpose embedded computing. Its high level of integration offers -significant performance benefits and greatly helps to simplify board design. - - -The T1024 SoC includes the following function and features: -- two e5500 cores, each with a private 256 KB L2 cache - - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant) - - Three levels of instructions: User, supervisor, and hypervisor - - Independent boot and reset - - Secure boot capability -- 256 KB shared L3 CoreNet platform cache (CPC) -- Interconnect CoreNet platform - - CoreNet coherency manager supporting coherent and noncoherent transactions - with prioritization and bandwidth allocation amongst CoreNet endpoints - - 150 Gbps coherent read bandwidth -- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support -- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - - Packet parsing, classification, and distribution - - Queue management for scheduling, packet sequencing, and congestion management - - Cryptography Acceleration (SEC 5.x) - - IEEE 1588 support - - Hardware buffer management for buffer allocation and deallocation - - MACSEC on DPAA-based Ethernet ports -- Ethernet interfaces - - Four 1 Gbps Ethernet controllers -- Parallel Ethernet interfaces - - Two RGMII interfaces -- High speed peripheral interfaces - - Three PCI Express 2.0 controllers/ports running at up to 5 GHz - - One SATA controller supporting 1.5 and 3.0 Gb/s operation - - One QSGMII interface - - Four SGMII interface supporting 1000 Mbps - - Three SGMII interfaces supporting up to 2500 Mbps - - 10GbE XFI or 10Base-KR interface -- Additional peripheral interfaces - - Two USB 2.0 controllers with integrated PHY - - SD/eSDHC/eMMC - - eSPI controller - - Four I2C controllers - - Four UARTs - - Four GPIO controllers - - Integrated flash controller (IFC) - - LCD interface (DIU) with 12 bit dual data rate -- Multicore programmable interrupt controller (PIC) -- Two 8-channel DMA engines -- Single source clocking implementation -- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) -- QUICC Engine block - - 32-bit RISC controller for flexible support of the communications peripherals - - Serial DMA channel for receive and transmit on all serial channels - - Two universal communication controllers, supporting TDM, HDLC, and UART - -T1023 Personality ------------------- -T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and -unavailable deep sleep. Rest of the blocks are almost same as T1024. -Differences between T1024 and T1023 -Feature T1024 T1023 -QUICC Engine: yes no -DIU: yes no -Deep Sleep: yes no -I2C controller: 4 3 -DDR: 64-bit 32-bit -IFC: 32-bit 28-bit - - -T1024QDS board Overview ------------------------ -- SERDES Connections - 4 lanes supporting the following: - - PCI Express: supports Gen 1 and Gen 2 - - SGMII 1G and SGMII 2.5G - - QSGMII - - XFI - - SATA 2.0 - - High-speed multiplexers route the SerDes traffic to appropriate slots or connectors. - - Aurora debug with dedicated connectors. -- DDR Controller - - Supports up to 1600 MTPS data-rate. - - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card. - - Supports Single-, dual- or quad-rank DIMMs - - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT. -- IFC/Local Bus - - NAND Flash: 8-bit, async, up to 2GB - - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - - NOR devices support 8 virtual banks - - Socketed to allow alternate devices - - GASIC: Simple (minimal) target within QIXIS FPGA - - PromJET rapid memory download support - - IFC Debug/Development card -- Ethernet - - Two on-board RGMII 10M/100M/1G ethernet ports. - - One QSGMII interface - - Four SGMII interface supporting 1Gbps - - Three SGMII interfaces supporting 2.5Gbps - - one 10Gbps XFI or 10Base-KR interface -- QIXIS System Logic FPGA - - Manages system power and reset sequencing. - - Manages the configurations of DUT, board, and clock for dynamic shmoo. - - Collects V-I-T data in background for code/power profiling. - - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion). - - General fault monitoring and logging. - - Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off. -- Clocks - - System and DDR clock (SYSCLK, DDRCLK). - - Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz. - - Software programmable in 1 MHz increments from 1-200 MHz. - - SERDES clocks - - Provides clocks to SerDes blocks and slots. - - 100 MHz, 125 MHz and 156.25 MHz options. - - Spread-spectrum option for 100 MHz. -- Power Supplies - - Dedicated PMBus regulator for VDD and VDDC. - - Adjustable from 0.7V to 1.3V at 35A - - VDD can be disabled independanty from VDDC for “deep sleep”. - - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A. - - VTT/MVREF automatically track operating voltage. - - Dedicated 2.5V VPP supply. - - Dedicated regulators/filters for AVDD supplies. - - Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD. -- Video - - DIU supports video up to 1280x1024x32 bpp. - - Chrontel CH7201 for HDMI connection. - - TI DS90C387R for direct LCD connection. - - Raw (not encoded) video connector for testing or other encoders. -- USB - - Supports two USB 2.0 ports with integrated PHYs. - - Two type A ports with 5V@1.5A per port. - - Second port can be converted to OTG mini-AB. -- SDHC - For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features: - - upport for optional clock feedback paths. - - Support for optional high-speed voltage translation direction controls. - - Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC. - - Support for eMMC memory devices. -- SPI - -On-board support of 3 different devices and sizes. -- Other IO - - Two Serial ports - - ProfiBus port - - Four I2C ports - - -Memory map on T1024QDS ----------------------- -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB -0x0_0000_0000 0x0_ffff_ffff DDR 4GB - - -128MB NOR Flash memory Map --------------------------- -Start Address End Address Definition Max size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -SerDes clock vs DIP-switch settings ------------------------------------ -SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4] -0x6F 100MHz 125MHz 1101 -0xD6 100MHz 100MHz 1111 -0x99 156.25MHz 100MHz 1011 - - -T1024 Clock frequency ----------------------- -BIN Core DDR Platform FMan -Bin1: 1400MHz 1600MT/s 400MHz 700MHz -Bin2: 1200MHz 1600MT/s 400MHz 600MHz -Bin3: 1000MHz 1600MT/s 400MHz 500MHz - - - -Software configurations and board settings ------------------------------------------- -1. NOR boot: - a. build NOR boot image - $ make T1024QDS_defconfig (For DDR3L, by default) - or make T1024QDS_D4_defconfig (For DDR4) - $ make - b. program u-boot.bin image to NOR flash - => tftp 1000000 u-boot.bin - => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize - set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot - - Switching between default bank0 and alternate bank4 on NOR flash - To change boot source to vbank4: - via software: run command 'qixis_reset altbank' in U-Boot. - via DIP-switch: set SW6[1:4] = '0100' - - To change boot source to vbank0: - via software: run command 'qixis_reset' in U-Boot. - via DIP-Switch: set SW6[1:4] = '0000' - -2. NAND Boot: - a. build PBL image for NAND boot - $ make T1024QDS_NAND_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to NAND flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => nand erase 0 $filesize - => nand write 1000000 0 $filesize - set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot - -3. SPI Boot: - a. build PBL image for SPI boot - $ make T1024QDS_SPIFLASH_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to SPI flash - => tftp 1000000 u-boot-with-spl-pbl.bin - => sf probe 0 - => sf erase 0 f0000 - => sf write 1000000 0 $filesize - set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot - -4. SD Boot: - a. build PBL image for SD boot - $ make T1024QDS_SDCARD_defconfig - $ make - b. program u-boot-with-spl-pbl.bin to SD/MMC card - => tftp 1000000 u-boot-with-spl-pbl.bin - => mmc write 1000000 8 0x800 - => tftp 1000000 fsl_fman_ucode_t1024_xx.bin - => mmc write 1000000 0x820 80 - set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot - - -DIU/QE-TDM/SDXC settings -------------------- -a) For TDM Riser: set pin_mux=tdm in hwconfig -b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig -c) For HDMI(DVI): set pin_mux=hdmi in hwconfig -d) For LCD(DFP): set pin_mux=lcd in hwconfig -e) For SDXC: set adaptor=sdxc in hwconfig - -2-stage NAND/SPI/SD boot loader -------------------------------- -PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. -SPL further initializes DDR using SPD and environment variables -and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR. -Finally SPL transers control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (30KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-Boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T1024QDS -------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot 1MB -0x100000 0x15FFFF U-Boot env 8KB -0x160000 0x17FFFF FMAN Ucode 128KB -0x180000 0x19FFFF QE Firmware 128KB - - -SD Card memory Map on T1024QDS ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 U-Boot img 1MB -0x800 0016 U-Boot env 8KB -0x820 0256 FMAN Ucode 128KB -0x920 0256 QE Firmware 128KB - - -SPI Flash memory Map on T1024QDS ----------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB -0x100000 0x101FFF U-Boot env 8KB -0x110000 0x12FFFF FMAN Ucode 128KB -0x130000 0x14FFFF QE Firmware 128KB - - -For more details, please refer to T1024QDS Reference Manual and access -website www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c deleted file mode 100644 index c27cecd5aa..0000000000 --- a/board/freescale/t102xqds/ddr.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * datarate_mhz_high values need to be in ascending order - */ -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ -#if defined(CONFIG_SYS_FSL_DDR4) - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - struct cpu_type *cpu = gd->arch.cpu; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust according to the board ddr freqency and n_banks - * specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found\n"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); - debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ", - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2); - debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * rtt and rtt_wr override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ -#else - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x5f; -#endif - - /* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit, - * set DDR bus width to 32bit for T1023 - */ - if (cpu->soc_ver == SVR_T1023) - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; - -#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 - /* for DDR bus 32bit test on T1024 */ - popts->data_bus_width = DDR_DATA_BUS_WIDTH_32; -#endif -} - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *qixis_base = (void *)QIXIS_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(qixis_base + 0x21, 0x2); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif - -int dram_init(void) -{ - phys_size_t dram_size; - -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) - fsl_dp_resume(); -#endif - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t102xqds/eth_t102xqds.c b/board/freescale/t102xqds/eth_t102xqds.c deleted file mode 100644 index 49ea21a83a..0000000000 --- a/board/freescale/t102xqds/eth_t102xqds.c +++ /dev/null @@ -1,445 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Shengzhou Liu - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/fman.h" -#include "t102xqds_qixis.h" - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII1 0 -#define EMI1_RGMII2 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT2 3 -#define EMI1_SLOT3 4 -#define EMI1_SLOT4 5 -#define EMI1_SLOT5 6 -#define EMI2 7 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { - "T1024QDS_MDIO_RGMII1", - "T1024QDS_MDIO_RGMII2", - "T1024QDS_MDIO_SLOT1", - "T1024QDS_MDIO_SLOT2", - "T1024QDS_MDIO_SLOT3", - "T1024QDS_MDIO_SLOT4", - "T1024QDS_MDIO_SLOT5", - "T1024QDS_MDIO_10GC", - "NULL", -}; - -/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */ -static u8 lane_to_slot[] = {2, 3, 4, 5}; - -static const char *t1024qds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name; - - if (muxval > EMI2) - return NULL; - - name = t1024qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t1024qds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t1024qds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - - if (muxval < 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t1024qds_mdio *priv = bus->priv; - - t1024qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t1024qds_mdio *priv = bus->priv; - - t1024qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t1024qds_mdio_reset(struct mii_dev *bus) -{ - struct t1024qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t1024qds_mdio_init(char *realbusname, u8 muxval) -{ - struct t1024qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t1024qds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t1024qds private data\n"); - free(bus); - return -1; - } - - bus->read = t1024qds_mdio_read; - bus->write = t1024qds_mdio_write; - bus->reset = t1024qds_mdio_reset; - strcpy(bus->name, t1024qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - struct fixed_link f_link; - - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) { - if (port == FM1_DTSEC3) { - fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "rgmii"); - fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { - if (port == FM1_DTSEC1) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii_vsc8234_phy_s5"); - } else if (port == FM1_DTSEC2) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii_vsc8234_phy_s4"); - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) { - if (port == FM1_DTSEC3) { - fdt_set_phy_handle(fdt, compat, addr, - "sgmii_aqr105_phy_s3"); - } - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1"); - break; - case FM1_DTSEC2: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2"); - break; - case FM1_DTSEC3: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3"); - break; - case FM1_DTSEC4: - fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4"); - break; - default: - break; - } - fdt_delprop(fdt, offset, "phy-connection-type"); - fdt_setprop_string(fdt, offset, "phy-connection-type", - "qsgmii"); - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { - /* XFI interface */ - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - /* no PHY for XFI */ - fdt_delprop(fdt, offset, "phy-handle"); - fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); - fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); - } -} - -void fdt_fixup_board_enet(void *fdt) -{ -} - -/* - * This function reads RCW to check if Serdes1{A:D} is configured - * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - switch (srds_s1) { - case 0x46: - case 0x47: - lane_to_slot[1] = 2; - break; - default: - break; - } -} - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_s1; - - srds_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - /* Set the two on-board RGMII PHY address */ - fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR); - - switch (srds_s1) { - case 0xd5: - case 0xd6: - /* QSGMII in Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, 0x8); - fm_info_set_phy_address(FM1_DTSEC2, 0x9); - fm_info_set_phy_address(FM1_DTSEC3, 0xa); - fm_info_set_phy_address(FM1_DTSEC4, 0xb); - break; - case 0x95: - case 0x99: - /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks the - * XAUI card is used for the XFI MAC, which will cause error. - */ - fm_info_set_phy_address(FM1_10GEC1, 4); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x6f: - /* SGMII in Slot3, Slot4, Slot5 */ - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x7f: - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); - break; - case 0x47: - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x77: - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3); - break; - case 0x5a: - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x6a: - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x5b: - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - break; - case 0x6b: - fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR); - break; - default: - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_SGMII_2500: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_SGMII) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_2500_FM1_DTSEC1 + idx); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - } - - if (lane < 0) - break; - - slot = lane_to_slot[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - - switch (slot) { - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - case 5: - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, mii_dev_for_muxval( - mdio_mux[i])); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - if (i == FM1_DTSEC3) - mdio_mux[i] = EMI1_RGMII2; - else if (i == FM1_DTSEC4) - mdio_mux[i] = EMI1_RGMII1; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - XFI_FM1_MAC1 + idx); - if (lane < 0) - break; - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/t102xqds/law.c b/board/freescale/t102xqds/law.c deleted file mode 100644 index d3c1dba934..0000000000 --- a/board/freescale/t102xqds/law.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { -#ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef QIXIS_BASE_PHYS - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t102xqds/pci.c b/board/freescale/t102xqds/pci.c deleted file mode 100644 index 1b1cc0483c..0000000000 --- a/board/freescale/t102xqds/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c deleted file mode 100644 index 9f4a43ed56..0000000000 --- a/board/freescale/t102xqds/spl.c +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "t102xqds_qixis.h" -#include "../common/spl.h" - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - -#if defined(CONFIG_ARCH_T1040) && defined(CONFIG_SPL_NAND_BOOT) - /* - * There is T1040 SoC issue where NOR, FPGA are inaccessible during - * NAND boot because IFC signals > IFC_AD7 are not enabled. - * This workaround changes RCW source to make all signals enabled. - */ - u32 porsr1, pinctl; -#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 - - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); -#endif - - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#if defined(CONFIG_SPL_MMC_BOOT) - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_SPI_BOOT) - puts("\nSPI boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - bd_t *bd; - - bd = (bd_t *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_SPI_BOOT - fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - fsl_spi_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t102xqds/t1024_nand_rcw.cfg b/board/freescale/t102xqds/t1024_nand_rcw.cfg deleted file mode 100644 index 4b8f7194dc..0000000000 --- a/board/freescale/t102xqds/t1024_nand_rcw.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz -# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz - -# PBL preamble and RCW header for T1024QDS -aa55aa55 010e0100 -# Serdes protocol 0x6F -0810000e 00000000 00000000 00000000 -37800001 00000012 e8104000 21000000 -00000000 00000000 00000000 00030810 -00000000 036c5a00 00000000 00000006 diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg deleted file mode 100644 index 98efca25a2..0000000000 --- a/board/freescale/t102xqds/t1024_pbi.cfg +++ /dev/null @@ -1,26 +0,0 @@ -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 256KB SRAM -09010100 00000000 -09010104 fffc0007 -09010f00 081e000d -09010000 80000000 -#Configure LAW for CPC1 -09000cd0 00000000 -09000cd4 fffc0000 -09000cd8 81000011 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -091380c0 000FFFFF diff --git a/board/freescale/t102xqds/t1024_sd_rcw.cfg b/board/freescale/t102xqds/t1024_sd_rcw.cfg deleted file mode 100644 index 3eca275db3..0000000000 --- a/board/freescale/t102xqds/t1024_sd_rcw.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz -# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz - -# PBL preamble and RCW header for T1024QDS -aa55aa55 010e0100 -# Serdes protocol 0x6F -0810000e 00000000 00000000 00000000 -37800001 00000012 68104000 21000000 -00000000 00000000 00000000 00030810 -00000000 036c5a00 00000000 00000006 diff --git a/board/freescale/t102xqds/t1024_spi_rcw.cfg b/board/freescale/t102xqds/t1024_spi_rcw.cfg deleted file mode 100644 index 1601e35fc8..0000000000 --- a/board/freescale/t102xqds/t1024_spi_rcw.cfg +++ /dev/null @@ -1,10 +0,0 @@ -# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz -# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz - -# PBL preamble and RCW header for T1024QDS -aa55aa55 010e0100 -# Serdes protocol 0x6F -0810000e 00000000 00000000 00000000 -37800001 00000012 58104000 21000000 -00000000 00000000 00000000 00030810 -00000000 036c5a00 00000000 00000006 diff --git a/board/freescale/t102xqds/t102xqds.c b/board/freescale/t102xqds/t102xqds.c deleted file mode 100644 index fd489851db..0000000000 --- a/board/freescale/t102xqds/t102xqds.c +++ /dev/null @@ -1,499 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "t102xqds.h" -#include "t102xqds_qixis.h" -#include "../common/sleep.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - struct cpu_type *cpu = gd->arch.cpu; - static const char *const freq[] = {"100", "125", "156.25", "100.0"}; - int clock; - u8 sw = QIXIS_READ(arch); - - printf("Board: %sQDS, ", cpu->name); - printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); - printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); - -#ifdef CONFIG_SDCARD - puts("SD/MMC\n"); -#elif CONFIG_SPIFLASH - puts("SPI\n"); -#else - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0x15) - printf("IFC Card\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); -#endif - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - puts("SERDES Reference: "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1=%sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2=%sMHz\n", freq[clock]); - - return 0; -} - -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; -#ifdef CONFIG_DM_I2C - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -static int board_mux_lane_to_slot(void) -{ - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1; - u8 brdcfg9; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - - brdcfg9 = QIXIS_READ(brdcfg[9]); - QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE); - - switch (srds_prtcl_s1) { - case 0: - /* SerDes1 is not enabled */ - break; - case 0xd5: - case 0x5b: - case 0x6b: - case 0x77: - case 0x6f: - case 0x7f: - QIXIS_WRITE(brdcfg[12], 0x8c); - break; - case 0x40: - QIXIS_WRITE(brdcfg[12], 0xfc); - break; - case 0xd6: - case 0x5a: - case 0x6a: - case 0x56: - QIXIS_WRITE(brdcfg[12], 0x88); - break; - case 0x47: - QIXIS_WRITE(brdcfg[12], 0xcc); - break; - case 0x46: - QIXIS_WRITE(brdcfg[12], 0xc8); - break; - case 0x95: - case 0x99: - brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE; - QIXIS_WRITE(brdcfg[9], brdcfg9); - QIXIS_WRITE(brdcfg[12], 0x8c); - break; - case 0x116: - QIXIS_WRITE(brdcfg[12], 0x00); - break; - case 0x115: - case 0x119: - case 0x129: - case 0x12b: - /* Aurora, PCIe, SGMII, SATA */ - QIXIS_WRITE(brdcfg[12], 0x04); - break; - default: - printf("WARNING: unsupported for SerDes Protocol %d\n", - srds_prtcl_s1); - return -1; - } - - return 0; -} - -#ifdef CONFIG_ARCH_T1024 -static void board_mux_setup(void) -{ - u8 brdcfg15; - - brdcfg15 = QIXIS_READ(brdcfg[15]); - brdcfg15 &= ~BRDCFG15_DIUSEL_MASK; - - if (hwconfig_arg_cmp("pin_mux", "tdm")) { - /* Route QE_TDM multiplexed signals to TDM Riser slot */ - QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM); - QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2); - QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & - ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM); - } else if (hwconfig_arg_cmp("pin_mux", "ucc")) { - /* to UCC (ProfiBus) interface */ - QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC); - } else if (hwconfig_arg_cmp("pin_mux", "hdmi")) { - /* to DVI (HDMI) encoder */ - QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI); - } else if (hwconfig_arg_cmp("pin_mux", "lcd")) { - /* to DFP (LCD) encoder */ - QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM | - BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD); - } - - if (hwconfig_arg_cmp("adaptor", "sdxc")) - /* Route SPI_CS multiplexed signals to SD slot */ - QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) & - ~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC); -} -#endif - -void board_retimer_ds125df111_init(void) -{ - u8 reg; - -#ifdef CONFIG_DM_I2C - struct udevice *dev; - int ret, bus_num = 0; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) - goto failed; - - /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ - reg = I2C_MUX_CH7; - dm_i2c_write(dev, 0, ®, 1); - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_SEC, - 1, &dev); - if (ret) - goto failed; - - reg = I2C_MUX_CH5; - dm_i2c_write(dev, 0, ®, 1); - - /* Access to Control/Shared register */ - ret = i2c_get_chip_for_busnum(bus_num, I2C_RETIMER_ADDR, - 1, &dev); - if (ret) - goto failed; - reg = 0x0; - dm_i2c_write(dev, 0xff, ®, 1); - - /* Read device revision and ID */ - dm_i2c_read(dev, 1, ®, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast */ - reg = 0x0c; - dm_i2c_write(dev, 0xff, ®, 1); - - /* Reset Channel Registers */ - dm_i2c_read(dev, 0, ®, 1); - reg |= 0x4; - dm_i2c_write(dev, 0, ®, 1); - - /* Enable override divider select and Enable Override Output Mux */ - dm_i2c_read(dev, 9, ®, 1); - reg |= 0x24; - dm_i2c_write(dev, 9, ®, 1); - - /* Select VCO Divider to full rate (000) */ - dm_i2c_read(dev, 0x18, ®, 1); - reg &= 0x8f; - dm_i2c_write(dev, 0x18, ®, 1); - - /* Select active PFD MUX input as re-timed data (001) */ - dm_i2c_read(dev, 0x1e, ®, 1); - reg &= 0x3f; - reg |= 0x20; - dm_i2c_write(dev, 0x1e, ®, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - dm_i2c_write(dev, 0x60, ®, 1); - reg = 0xb2; - dm_i2c_write(dev, 0x61, ®, 1); - reg = 0x90; - dm_i2c_write(dev, 0x62, ®, 1); - reg = 0xb3; - dm_i2c_write(dev, 0x63, ®, 1); - reg = 0xcd; - dm_i2c_write(dev, 0x64, ®, 1); - return; - -failed: - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return; -#else - /* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */ - reg = I2C_MUX_CH7; - i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, ®, 1); - reg = I2C_MUX_CH5; - i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); - - /* Access to Control/Shared register */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); - - /* Read device revision and ID */ - i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); - debug("Retimer version id = 0x%x\n", reg); - - /* Enable Broadcast */ - reg = 0x0c; - i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); - - /* Reset Channel Registers */ - i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); - reg |= 0x4; - i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); - - /* Enable override divider select and Enable Override Output Mux */ - i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); - reg |= 0x24; - i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); - - /* Select VCO Divider to full rate (000) */ - i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); - reg &= 0x8f; - i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); - - /* Select active PFD MUX input as re-timed data (001) */ - i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); - reg &= 0x3f; - reg |= 0x20; - i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); - - /* Set data rate as 10.3125 Gbps */ - reg = 0x0; - i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); - reg = 0xb2; - i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); - reg = 0x90; - i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); - reg = 0xb3; - i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); - reg = 0xcd; - i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); -#endif -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - board_mux_lane_to_slot(); - board_retimer_ds125df111_init(); - - /* Increase IO drive strength to address FCS error on RGMII */ - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -#define NUM_SRDS_PLL 2 -int misc_init_r(void) -{ -#ifdef CONFIG_ARCH_T1024 - board_mux_setup(); -#endif - return 0; -} - -void fdt_fixup_spi_mux(void *blob) -{ - int nodeoff = 0; - - if (hwconfig_arg_cmp("pin_mux", "tdm")) { - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "eon,en25s64")) >= 0) { - fdt_del_node(blob, nodeoff); - } - } else { - /* remove tdm node */ - while ((nodeoff = fdt_node_offset_by_compatible(blob, 0, - "maxim,ds26522")) >= 0) { - fdt_del_node(blob, nodeoff); - } - } -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - fdt_fixup_spi_mux(blob); - - return 0; -} - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} diff --git a/board/freescale/t102xqds/t102xqds.h b/board/freescale/t102xqds/t102xqds.h deleted file mode 100644 index d327b5edb9..0000000000 --- a/board/freescale/t102xqds/t102xqds.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#ifndef __T102x_QDS_H__ -#define __T102x_QDS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch, int bus_num); - -#endif diff --git a/board/freescale/t102xqds/t102xqds_qixis.h b/board/freescale/t102xqds/t102xqds_qixis.h deleted file mode 100644 index b84a33fc48..0000000000 --- a/board/freescale/t102xqds/t102xqds_qixis.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __T1024QDS_QIXIS_H__ -#define __T1024QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for T1024/T1023 QDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ -#define BRDCFG5_IMX_MASK 0xC0 -#define BRDCFG5_IMX_DIU 0x80 - -#define BRDCFG5_SPIRTE_MASK 0x07 -#define BRDCFG5_SPIRTE_TDM 0x01 -#define BRDCFG5_SPIRTE_SDHC 0x02 -#define BRDCFG9_XFI_TX_DISABLE 0x10 - -/* BRDCFG13[0:5] TDM configuration and setup */ -#define BRDCFG13_TDM_MASK 0xfc -#define BRDCFG13_TDM_INTERFACE 0x37 -#define BRDCFG13_HDLC_LOOPBACK 0x29 -#define BRDCFG13_TDM_LOOPBACK 0x31 - -/* BRDCFG15[3] controls LCD Panel Powerdown */ -#define BRDCFG15_LCDFM 0x20 -#define BRDCFG15_LCDPD 0x10 -#define BRDCFG15_LCDPD_MASK 0x10 -#define BRDCFG15_LCDPD_ENABLED 0x00 - -/* BRDCFG15[6:7] controls DIU MUX selction*/ -#define BRDCFG15_DIUSEL_MASK 0x03 -#define BRDCFG15_DIUSEL_HDMI 0x00 -#define BRDCFG15_DIUSEL_LCD 0x01 -#define BRDCFG15_DIUSEL_UCC 0x02 -#define BRDCFG15_DIUSEL_TDM 0x03 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - - -#define QIXIS_SRDS1CLK_122 0x5a -#define QIXIS_SRDS1CLK_125 0x5e -#endif diff --git a/board/freescale/t102xqds/tlb.c b/board/freescale/t102xqds/tlb.c deleted file mode 100644 index 3546331aab..0000000000 --- a/board/freescale/t102xqds/tlb.c +++ /dev/null @@ -1,116 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the - * SRAM is at 0xfffc0000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256K, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - -#ifndef CONFIG_SPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef QIXIS_BASE - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_4K, 1), -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 12, BOOKE_PAGESZ_1G, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 13, BOOKE_PAGESZ_1G, 1) -#endif - /* entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so if needed more, will use entry 16 later. - */ -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig deleted file mode 100644 index ec3ff0c1ec..0000000000 --- a/board/freescale/t1040qds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_T1040QDS - -config SYS_BOARD - default "t1040qds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T1040QDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS deleted file mode 100644 index 1e276e3db9..0000000000 --- a/board/freescale/t1040qds/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -T1040QDS BOARD -M: Poonam Aggrwal -S: Maintained -F: board/freescale/t1040qds/ -F: include/configs/T1040QDS.h -F: configs/T1040QDS_defconfig -F: configs/T1040QDS_DDR4_defconfig - -T1040QDS_SECURE_BOOT BOARD -M: Ruchika Gupta -S: Maintained -F: configs/T1040QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile deleted file mode 100644 index e10a54af88..0000000000 --- a/board/freescale/t1040qds/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -obj-y += t1040qds.o -obj-y += ddr.o -obj-$(CONFIG_PCI) += pci.o -obj-y += law.o -obj-y += tlb.o -obj-y += eth.o -obj-y += diu.o diff --git a/board/freescale/t1040qds/README b/board/freescale/t1040qds/README deleted file mode 100644 index 6c5ffc07f8..0000000000 --- a/board/freescale/t1040qds/README +++ /dev/null @@ -1,169 +0,0 @@ -Overview --------- -The T1040QDS is a Freescale reference board that hosts the T1040 SoC -(and variants). - -T1040 SoC Overview ------------------- -The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA -processor cores with high-performance data path acceleration architecture -and network peripheral interfaces required for networking & telecommunications. - -The T1040/T1042 SoC includes the following function and features: - - - Four e5500 cores, each with a private 256 KB L2 cache - - 256 KB shared L3 CoreNet platform cache (CPC) - - Interconnect CoreNet platform - - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration - for the following functions: - - Packet parsing, classification, and distribution - - Queue management for scheduling, packet sequencing, and congestion - management - - Cryptography Acceleration (SEC 5.0) - - RegEx Pattern Matching Acceleration (PME 2.2) - - IEEE Std 1588 support - - Hardware buffer management for buffer allocation and deallocation - - Ethernet interfaces - - Integrated 8-port Gigabit Ethernet switch (T1040 only) - - Four 1 Gbps Ethernet controllers - - Two RGMII interfaces or one RGMII and one MII interfaces - - High speed peripheral interfaces - - Four PCI Express 2.0 controllers running at up to 5 GHz - - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation - - Upto two QSGMII interface - - Upto six SGMII interface supporting 1000 Mbps - - One SGMII interface supporting upto 2500 Mbps - - Additional peripheral interfaces - - Two USB 2.0 controllers with integrated PHY - - SD/eSDHC/eMMC - - eSPI controller - - Four I2C controllers - - Four UARTs - - Four GPIO controllers - - Integrated flash controller (IFC) - - LCD and HDMI interface (DIU) with 12 bit dual data rate - - TDM interface - - Multicore programmable interrupt controller (PIC) - - Two 8-channel DMA engines - - Single source clocking implementation - - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - - T1040QDS board Overview - ----------------------- - - SERDES Connections, 8 lanes supporting: - — PCI Express: supporting Gen 1 and Gen 2; - — SGMII - — QSGMII - — SATA 2.0 - — Aurora debug with dedicated connectors (T1040 only) - - DDR Controller - - Supports rates of up to 1600 MHz data-rate - - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. - -IFC/Local Bus - - NAND flash: 8-bit, async, up to 2GB. - - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - - GASIC: Simple (minimal) target within Qixis FPGA - - PromJET rapid memory download support - - Ethernet - - Two on-board RGMII 10/100/1G ethernet ports. - - PHY #0 remains powered up during deep-sleep (T1040 only) - - QIXIS System Logic FPGA - - Clocks - - System and DDR clock (SYSCLK, “DDRCLK”) - - SERDES clocks - - Power Supplies - - Video - - DIU supports video at up to 1280x1024x32bpp - - USB - - Supports two USB 2.0 ports with integrated PHYs - — Two type A ports with 5V@1.5A per port. - — Second port can be converted to OTG mini-AB - - SDHC - - SDHC port connects directly to an adapter card slot, featuring: - - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC - — Supporting eMMC memory devices - - SPI - - On-board support of 3 different devices and sizes - - Other IO - - Two Serial ports - - ProfiBus port - - Four I2C ports - -Memory map on T1040QDS ----------------------- -The addresses in brackets are physical addresses. - -Start Address End Address Description Size -0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB -0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB -0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB -0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB -0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB -0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB -0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB -0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB -0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB -0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB -0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB -0xF_0000_0000 0xF_003F_FFFF DCSR 4MB -0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB -0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB -0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB -0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB -0x0_0000_0000 0x0_ffff_ffff DDR 2GB - - -NOR Flash memory Map on T1040QDS --------------------------------- - Start End Definition Size -0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB -0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB -0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB -0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB -0xEC000000 0xEC01FFFF RCW (alt bank) 128KB -0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB -0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB -0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB -0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB -0xE8000000 0xE801FFFF RCW (current bank) 128KB - - -Various Software configurations/environment variables/commands --------------------------------------------------------------- -The below commands apply to T1040QDS - -1. U-Boot environment variable hwconfig - The default hwconfig is: - hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: - dr_mode=host,phy_type=utmi - Note: For USB gadget set "dr_mode=peripheral" - -2. FMAN Ucode versions - fsl_fman_ucode_t1040.bin - -3. Switching to alternate bank - Commands for switching to alternate bank. - - 1. To change from vbank0 to vbank4 - => qixis_reset altbank (it will boot using vbank4) - - 2.To change from vbank4 to vbank0 - => qixis reset (it will boot using vbank0) - -T1040 Personality --------------------- - -T1022 Personality --------------------- -T1022 is a reduced personality of T1040 with less core/clusters. - -T1042 Personality --------------------- -T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit -Ethernet switch. Rest of the blocks are same as T1040 diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c deleted file mode 100644 index 0a817d0ee8..0000000000 --- a/board/freescale/t1040qds/ddr.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - pbsp = udimms[0]; - - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found\n"); - printf("for data rate %lu MT/s\n", ddr_freq); - printf("Trying to use the highest speed (%u) parameters\n", - pbsp_highest->datarate_mhz_high); - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 1; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * rtt and rtt_wr override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ -#ifdef CONFIG_SYS_FSL_DDR4 - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) | - DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */ - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x69; -#else - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); -#endif -} - -#if defined(CONFIG_DEEP_SLEEP) -void board_mem_sleep_setup(void) -{ - void __iomem *qixis_base = (void *)QIXIS_BASE; - - /* does not provide HW signals for power management */ - clrbits_8(qixis_base + 0x21, 0x2); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing....using SPD\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - -#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) - fsl_dp_resume(); -#endif - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h deleted file mode 100644 index 0f88698ab5..0000000000 --- a/board/freescale/t1040qds/ddr.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | - */ -#ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, -#elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, -#else -#error DDR type not defined -#endif - {} -}; - -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; -#endif diff --git a/board/freescale/t1040qds/diu.c b/board/freescale/t1040qds/diu.c deleted file mode 100644 index 0b1aeed69e..0000000000 --- a/board/freescale/t1040qds/diu.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * Author: Priyanka Jain - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/diu_ch7301.h" -#include "t1040qds.h" -#include "t1040qds_qixis.h" - -/* - * DIU Area Descriptor - * - * Note that we need to byte-swap the value before it's written to the AD - * register. So even though the registers don't look like they're in the same - * bit positions as they are on the MPC8610, the same value is written to the - * AD register on the MPC8610 and on the P1022. - */ -#define AD_BYTE_F 0x10000000 -#define AD_ALPHA_C_SHIFT 25 -#define AD_BLUE_C_SHIFT 23 -#define AD_GREEN_C_SHIFT 21 -#define AD_RED_C_SHIFT 19 -#define AD_PIXEL_S_SHIFT 16 -#define AD_COMP_3_SHIFT 12 -#define AD_COMP_2_SHIFT 8 -#define AD_COMP_1_SHIFT 4 -#define AD_COMP_0_SHIFT 0 - -void diu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long speed_ccb, temp; - u32 pixval; - int ret = 0; - speed_ccb = get_bus_freq(0); - temp = 1000000000 / pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - - /* Program HDMI encoder */ - /* Switch channel to DIU */ - select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0); - - /* Set dispaly encoder */ - ret = diu_set_dvi_encoder(temp); - if (ret) { - puts("Failed to set DVI encoder\n"); - return; - } - - /* Switch channel to default */ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - - /* Program pixel clock */ - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, - ((pixval << PXCK_BITS_START) & PXCK_MASK)); - /* enable clock*/ - out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK | - ((pixval << PXCK_BITS_START) & PXCK_MASK)); -} - -int platform_diu_init(unsigned int xres, unsigned int yres, const char *port) -{ - u32 pixel_format; - u8 sw; - - /*Route I2C4 to DIU system as HSYNC/VSYNC*/ - sw = QIXIS_READ(brdcfg[5]); - QIXIS_WRITE(brdcfg[5], - ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU))); - - /*Configure Display ouput port as HDMI*/ - sw = QIXIS_READ(brdcfg[15]); - QIXIS_WRITE(brdcfg[15], - ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK)) - | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI))); - - pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) | - (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) | - (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) | - (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) | - (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT)); - - printf("DIU: Switching to monitor @ %ux%u\n", xres, yres); - - - return fsl_diu_init(xres, yres, pixel_format, 0); -} diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c deleted file mode 100644 index b349b77951..0000000000 --- a/board/freescale/t1040qds/eth.c +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * The RGMII PHYs are provided by the two on-board PHY connected to - * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board - * PHY or by the standard four-port SGMII riser card (VSC). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/fman.h" -#include "../common/qixis.h" - -#include "t1040qds_qixis.h" - -#ifdef CONFIG_FMAN_ENET - /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. - * Bank 1 -> Lanes A, B, C, D - * Bank 2 -> Lanes E, F, G, H - */ - - /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here - * means that the mapping must be determined dynamically, or that the lane - * maps to something other than a board slot. - */ -static u8 lane_to_slot[] = { - 0, 0, 0, 0, 0, 0, 0, 0 -}; - -/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs - * housed. - */ -static int riser_phy_addr[] = { - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, - CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, -}; - -/* Slot2 does not have EMI connections */ -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII0 0 -#define EMI1_RGMII1 1 -#define EMI1_SLOT1 2 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI1_SLOT6 6 -#define EMI1_SLOT7 7 -#define EMI2 8 - -static int mdio_mux[NUM_FM_PORTS]; - -static const char * const mdio_names[] = { - "T1040_QDS_MDIO0", - "T1040_QDS_MDIO1", - "T1040_QDS_MDIO2", - "T1040_QDS_MDIO3", - "T1040_QDS_MDIO4", - "T1040_QDS_MDIO5", - "T1040_QDS_MDIO6", - "T1040_QDS_MDIO7", -}; - -struct t1040_qds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t1040_qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -static void t1040_qds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if (muxval <= 7) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t1040_qds_mdio *priv = bus->priv; - - t1040_qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t1040_qds_mdio *priv = bus->priv; - - t1040_qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t1040_qds_mdio_reset(struct mii_dev *bus) -{ - struct t1040_qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t1040_qds_mdio_init(char *realbusname, u8 muxval) -{ - struct t1040_qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate t1040_qds MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate t1040_qds private data\n"); - free(bus); - return -1; - } - - bus->read = t1040_qds_mdio_read; - bus->write = t1040_qds_mdio_write; - bus->reset = t1040_qds_mdio_reset; - strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -/* - * Initialize the lane_to_slot[] array. - * - * On the T1040QDS board the mapping is controlled by ?? register. - */ -static void initialize_lane_to_slot(void) -{ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL) - >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - - QIXIS_WRITE(cms[0], 0x07); - - switch (serdes1_prtcl) { - case 0x60: - case 0x66: - case 0x67: - case 0x69: - lane_to_slot[1] = 7; - lane_to_slot[2] = 6; - lane_to_slot[3] = 5; - break; - case 0x86: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - break; - case 0x87: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - lane_to_slot[7] = 7; - break; - case 0x89: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - lane_to_slot[6] = 7; - lane_to_slot[7] = 7; - break; - case 0x8d: - lane_to_slot[1] = 7; - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - lane_to_slot[5] = 3; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0x8F: - case 0x85: - lane_to_slot[1] = 7; - lane_to_slot[2] = 6; - lane_to_slot[3] = 5; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xA5: - lane_to_slot[1] = 7; - lane_to_slot[6] = 3; - lane_to_slot[7] = 3; - break; - case 0xA7: - lane_to_slot[1] = 7; - lane_to_slot[2] = 6; - lane_to_slot[3] = 5; - lane_to_slot[7] = 7; - break; - case 0xAA: - lane_to_slot[1] = 7; - lane_to_slot[6] = 7; - lane_to_slot[7] = 7; - break; - case 0x40: - lane_to_slot[2] = 7; - lane_to_slot[3] = 7; - break; - default: - printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", - serdes1_prtcl); - break; - } -} - -/* - * Given the following ... - * - * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' - * compatible string and 'addr' physical address) - * - * 2) An Fman port - * - * ... update the phy-handle property of the Ethernet node to point to the - * right PHY. This assumes that we already know the PHY for each port. - * - * The offset of the Fman Ethernet node is also passed in for convenience, but - * it is not used, and we recalculate the offset anyway. - * - * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. - * Inside the Fman, "ports" are things that connect to MACs. We only call them - * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs - * and ports are the same thing. - * - */ -void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, - enum fm_port port, int offset) -{ - phy_interface_t intf = fm_info_get_enet_if(port); - char phy[16]; - - /* The RGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_RGMII) { - sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - - /* The SGMII PHY is identified by the MAC connected to it */ - if (intf == PHY_INTERFACE_MODE_SGMII) { - int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 - + port); - u8 slot; - if (lane < 0) - return; - slot = lane_to_slot[lane]; - if (slot) { - /* Slot housing a SGMII riser card */ - sprintf(phy, "phy_s%x_%02x", slot, - (fm_info_get_phy_address(port - FM1_DTSEC1)- - CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); - fdt_set_phy_handle(fdt, compat, addr, phy); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i, lane, idx; - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - - switch (mdio_mux[i]) { - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT5: - fdt_status_okay_by_alias(fdt, "emi1_slot5"); - break; - case EMI1_SLOT6: - fdt_status_okay_by_alias(fdt, "emi1_slot6"); - break; - case EMI1_SLOT7: - fdt_status_okay_by_alias(fdt, "emi1_slot7"); - break; - } - break; - case PHY_INTERFACE_MODE_RGMII: - if (i == FM1_DTSEC4) - fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); - - if (i == FM1_DTSEC5) - fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); - break; - default: - break; - } - } -} -#endif /* #ifdef CONFIG_FMAN_ENET */ - -static void set_brdcfg9_for_gtx_clk(void) -{ - u8 brdcfg9; - brdcfg9 = QIXIS_READ(brdcfg[9]); -/* Initializing EPHY2 clock to RGMII mode */ - brdcfg9 &= ~(BRDCFG9_EPHY2_MASK); - brdcfg9 |= (BRDCFG9_EPHY2_VAL); - QIXIS_WRITE(brdcfg[9], brdcfg9); -} - -void t1040_handle_phy_interface_sgmii(int i) -{ - int lane, idx, slot; - idx = i - FM1_DTSEC1; - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - - if (lane < 0) - return; - slot = lane_to_slot[lane]; - - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - case 3: - if (FM1_DTSEC4 == i) - fm_info_set_phy_address(i, riser_phy_addr[0]); - if (FM1_DTSEC5 == i) - fm_info_set_phy_address(i, riser_phy_addr[1]); - - mdio_mux[i] = EMI1_SLOT3; - - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - case 5: - /* Slot housing a SGMII riser card? */ - fm_info_set_phy_address(i, riser_phy_addr[0]); - mdio_mux[i] = EMI1_SLOT5; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - case 6: - /* Slot housing a SGMII riser card? */ - fm_info_set_phy_address(i, riser_phy_addr[0]); - mdio_mux[i] = EMI1_SLOT6; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - case 7: - if (FM1_DTSEC1 == i) - fm_info_set_phy_address(i, riser_phy_addr[0]); - if (FM1_DTSEC2 == i) - fm_info_set_phy_address(i, riser_phy_addr[1]); - if (FM1_DTSEC3 == i) - fm_info_set_phy_address(i, riser_phy_addr[2]); - if (FM1_DTSEC5 == i) - fm_info_set_phy_address(i, riser_phy_addr[3]); - - mdio_mux[i] = EMI1_SLOT7; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); -} -void t1040_handle_phy_interface_rgmii(int i) -{ - fm_info_set_phy_address(i, i == FM1_DTSEC5 ? - CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : - CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : - EMI1_RGMII0; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); -} - -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_FMAN_ENET - struct memac_mdio_info memac_mdio_info; - unsigned int i; -#ifdef CONFIG_VSC9953 - int lane; - int phy_addr; - phy_interface_t phy_int; - struct mii_dev *bus; -#endif - - printf("Initializing Fman\n"); - set_brdcfg9_for_gtx_clk(); - - initialize_lane_to_slot(); - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - memac_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; - memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the real 1G MDIO bus */ - fm_memac_mdio_init(bis, &memac_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); - t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); - - /* - * Program on board RGMII PHY addresses. If the SGMII Riser - * card used, we'll override the PHY address later. For any DTSEC that - * is RGMII, we'll also override its PHY address later. We assume that - * DTSEC4 and DTSEC5 are used for RGMII. - */ - fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_QSGMII: - fm_info_set_mdio(i, NULL); - break; - case PHY_INTERFACE_MODE_SGMII: - t1040_handle_phy_interface_sgmii(i); - break; - - case PHY_INTERFACE_MODE_RGMII: - /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ - t1040_handle_phy_interface_rgmii(i); - break; - default: - break; - } - } - -#ifdef CONFIG_VSC9953 - for (i = 0; i < VSC9953_MAX_PORTS; i++) { - lane = -1; - phy_addr = 0; - phy_int = PHY_INTERFACE_MODE_NONE; - switch (i) { - case 0: - case 1: - case 2: - case 3: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); - /* PHYs connected over QSGMII */ - if (lane >= 0) { - phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + - i; - phy_int = PHY_INTERFACE_MODE_QSGMII; - break; - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_SW1_MAC1 + i); - - if (lane < 0) - break; - - /* PHYs connected over QSGMII */ - if (i != 3 || lane_to_slot[lane] == 7) - phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + i; - else - phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; - phy_int = PHY_INTERFACE_MODE_SGMII; - break; - case 4: - case 5: - case 6: - case 7: - lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); - /* PHYs connected over QSGMII */ - if (lane >= 0) { - phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + - i - 4; - phy_int = PHY_INTERFACE_MODE_QSGMII; - break; - } - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_SW1_MAC1 + i); - /* PHYs connected over SGMII */ - if (lane >= 0) { - phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR - + i - 3; - phy_int = PHY_INTERFACE_MODE_SGMII; - } - break; - case 8: - if (serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1) < 0) - /* FM1@DTSEC1 is connected to SW1@PORT8 */ - vsc9953_port_enable(i); - break; - case 9: - if (serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC2) < 0) { - /* Enable L2 On MAC2 using SCFG */ - struct ccsr_scfg *scfg = (struct ccsr_scfg *) - CONFIG_SYS_MPC85xx_SCFG; - - out_be32(&scfg->esgmiiselcr, - in_be32(&scfg->esgmiiselcr) | - (0x80000000)); - vsc9953_port_enable(i); - } - break; - } - - if (lane >= 0) { - bus = mii_dev_for_muxval(lane_to_slot[lane]); - vsc9953_port_info_set_mdio(i, bus); - vsc9953_port_enable(i); - } - vsc9953_port_info_set_phy_address(i, phy_addr); - vsc9953_port_info_set_phy_int(i, phy_int); - } - -#endif - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} diff --git a/board/freescale/t1040qds/law.c b/board/freescale/t1040qds/law.c deleted file mode 100644 index cf27655c14..0000000000 --- a/board/freescale/t1040qds/law.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { -#ifdef CONFIG_MTD_NOR_FLASH - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef QIXIS_BASE_PHYS - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t1040qds/pci.c b/board/freescale/t1040qds/pci.c deleted file mode 100644 index 5152cdf18a..0000000000 --- a/board/freescale/t1040qds/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg deleted file mode 100644 index 121b005baf..0000000000 --- a/board/freescale/t1040qds/t1040_pbi.cfg +++ /dev/null @@ -1,27 +0,0 @@ -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#Configure CPC1 as 256KB SRAM -09010100 00000000 -09010104 fffc0007 -09010f00 081e000d -09010000 80000000 -#Configure LAW for CPC1 -09000cf0 00000000 -09000cf4 fffc0000 -09000cf8 81000011 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Configure SPI controller -09110000 80000403 -09110020 2d170008 -09110024 00100008 -09110028 00100008 -0911002c 00100008 -#Flush PBL data -09138000 00000000 -091380c0 00000000 diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg deleted file mode 100644 index 0d0dfa5a46..0000000000 --- a/board/freescale/t1040qds/t1040_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -# serdes protocol 0x66 -0a10000c 0c000000 00000000 00000000 -66000002 00000000 fc027000 01000000 -00000000 00000000 00000000 00030810 -00000000 03fc500f 00000000 00000000 diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c deleted file mode 100644 index cf38d843ac..0000000000 --- a/board/freescale/t1040qds/t1040qds.c +++ /dev/null @@ -1,307 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/sleep.h" -#include "../common/qixis.h" -#include "t1040qds.h" -#include "t1040qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - static const char *const freq[] = {"100", "125", "156.25", "161.13", - "122.88", "122.88", "122.88"}; - int clock; - - printf("Board: %sQDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("PromJet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else if (sw == 0x15) - printf("IFCCard\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference: "); - sw = QIXIS_READ(brdcfg[2]); - clock = (sw >> 6) & 3; - printf("Clock1=%sMHz ", freq[clock]); - clock = (sw >> 4) & 3; - printf("Clock2=%sMHz\n", freq[clock]); - - return 0; -} - -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; - -#ifdef CONFIG_DM_I2C - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -static void qe_board_setup(void) -{ - u8 brdcfg15, brdcfg9; - - if (hwconfig("qe") && hwconfig("tdm")) { - brdcfg15 = QIXIS_READ(brdcfg[15]); - /* - * TDMRiser uses QE-TDM - * Route QE_TDM signals to TDM Riser slot - */ - QIXIS_WRITE(brdcfg[15], brdcfg15 | 7); - } else if (hwconfig("qe") && hwconfig("uart")) { - brdcfg15 = QIXIS_READ(brdcfg[15]); - brdcfg9 = QIXIS_READ(brdcfg[9]); - /* - * Route QE_TDM signals to UCC - * ProfiBus controlled by UCC3 - */ - brdcfg15 &= 0xfc; - QIXIS_WRITE(brdcfg[15], brdcfg15 | 2); - QIXIS_WRITE(brdcfg[9], brdcfg9 | 4); - } -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_DEEP_SLEEP) - if (is_warm_boot()) - fsl_dp_disable_console(); -#endif - - return 0; -} - -int board_early_init_r(void) -{ -#ifdef CONFIG_SYS_FLASH_BASE - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_64: - return 64000000; - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -#define NUM_SRDS_BANKS 2 -int misc_init_r(void) -{ - u8 sw; - serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - u32 actual[NUM_SRDS_BANKS] = { 0 }; - int i; - - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < NUM_SRDS_BANKS; i++) { - unsigned int clock = (sw >> (6 - 2 * i)) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - } - } - - puts("SerDes1"); - for (i = 0; i < NUM_SRDS_BANKS; i++) { - u32 pllcr0 = srds_regs->bank[i].pllcr0; - u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("expects ref clk%d %sMHz, but actual is %sMHz\n", - i + 1, serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - qe_board_setup(); - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} - -void qixis_dump_switch(void) -{ - int i, nr_of_cfgsw; - - QIXIS_WRITE(cms[0], 0x00); - nr_of_cfgsw = QIXIS_READ(cms[1]); - - puts("DIP switch settings dump:\n"); - for (i = 1; i <= nr_of_cfgsw; i++) { - QIXIS_WRITE(cms[0], i); - printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); - } -} - -int board_need_mem_reset(void) -{ - return 1; -} diff --git a/board/freescale/t1040qds/t1040qds.h b/board/freescale/t1040qds/t1040qds.h deleted file mode 100644 index 781bcdefc9..0000000000 --- a/board/freescale/t1040qds/t1040qds.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#ifndef __T1040_QDS_H__ -#define __T1040_QDS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); -int select_i2c_ch_pca9547(u8 ch, int bus_bum); - -#endif diff --git a/board/freescale/t1040qds/t1040qds_qixis.h b/board/freescale/t1040qds/t1040qds_qixis.h deleted file mode 100644 index 213d7011db..0000000000 --- a/board/freescale/t1040qds/t1040qds_qixis.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __T1040QDS_QIXIS_H__ -#define __T1040QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for T1040QDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/ -#define BRDCFG5_IMX_MASK 0xC0 -#define BRDCFG5_IMX_DIU 0x80 - -/* BRDCFG9[2] controls EPHY2 Clock */ -#define BRDCFG9_EPHY2_MASK 0x20 -#define BRDCFG9_EPHY2_VAL 0x00 - -/* BRDCFG15[3] controls LCD Panel Powerdown*/ -#define BRDCFG15_LCDPD_MASK 0x10 -#define BRDCFG15_LCDPD_ENABLED 0x00 - -/* BRDCFG15[6:7] controls DIU MUX selction*/ -#define BRDCFG15_DIUSEL_MASK 0x03 -#define BRDCFG15_DIUSEL_HDMI 0x00 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 -#define QIXIS_SYSCLK_64 0x8 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - - -#define QIXIS_SRDS1CLK_122 0x5a -#define QIXIS_SRDS1CLK_125 0x5e -#endif diff --git a/board/freescale/t1040qds/tlb.c b/board/freescale/t1040qds/tlb.c deleted file mode 100644 index 216b119135..0000000000 --- a/board/freescale/t1040qds/tlb.c +++ /dev/null @@ -1,107 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the - * SRAM is at 0xfffc0000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_256K, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef QIXIS_BASE - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_4K, 1), -#endif - -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig deleted file mode 100644 index f7c1a0c15d..0000000000 --- a/board/freescale/t4qds/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_T4160QDS || TARGET_T4240QDS - -config SYS_BOARD - default "t4qds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "T4240QDS" - -source "board/freescale/common/Kconfig" - -endif diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS deleted file mode 100644 index 44bb2f5c6d..0000000000 --- a/board/freescale/t4qds/MAINTAINERS +++ /dev/null @@ -1,18 +0,0 @@ -T4QDS BOARD -#M: Shaohui Xie -S: Orphan (since 2018-05) -F: board/freescale/t4qds/ -F: include/configs/T4240QDS.h -F: configs/T4160QDS_defconfig -F: configs/T4160QDS_NAND_defconfig -F: configs/T4160QDS_SDCARD_defconfig -F: configs/T4240QDS_defconfig -F: configs/T4240QDS_NAND_defconfig -F: configs/T4240QDS_SDCARD_defconfig -F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig - -T4160QDS_SECURE_BOOT BOARD -M: Ruchika Gupta -S: Maintained -F: configs/T4160QDS_SECURE_BOOT_defconfig -F: configs/T4240QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile deleted file mode 100644 index 11144222d3..0000000000 --- a/board/freescale/t4qds/Makefile +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2012 Freescale Semiconductor, Inc. - -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -else -obj-$(CONFIG_TARGET_T4160QDS) += t4240qds.o eth.o -obj-$(CONFIG_TARGET_T4240QDS) += t4240qds.o eth.o -obj-$(CONFIG_PCI) += pci.o -endif - -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/t4qds/README b/board/freescale/t4qds/README deleted file mode 100644 index bf238146db..0000000000 --- a/board/freescale/t4qds/README +++ /dev/null @@ -1,194 +0,0 @@ -Overview --------- -The T4240QDS is a high-performance computing evaluation, development and test -platform supporting the T4240 QorIQâ„ĸ Power Architectureâ„ĸ processor. T4240QDS is -optimized to support the high-bandwidth DDR3 memory ports, as well as the -highly-configurable SerDes ports. The system is lead-free and RoHS-compliant. - -Board Features - SERDES Connections - 32 lanes grouped into four 8-lane banks - Two “front side” banks dedicated to Ethernet - - High-speed crosspoint switch fabric on selected lanes - - Two PCI Express slots with side-band connector supporting - - SGMII - - XAUI - - HiGig - - I-pass connectors allow board-to-board and loopback support - Two “back side” banks dedicated to other protocols - - High-speed crosspoint switch fabric on all lanes - - Four PCI Express slots with side-band connector supporting - - PCI Express 3.0 - - SATA 2.0 - - SRIO 2.0 - - Supports 4X Aurora debug with two connectors - DDR Controllers - Three independant 64-bit DDR3 controllers - Supports rates of 1866 up to 2133 MHz data-rate - Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller - DDR power supplies 1.5V to all devices with automatic tracking of VTT. - Power software-switchable to 1.35V if software detects all DDR3LP devices. - MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and - 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time - increases by 1 clock. - - IFC/Local Bus - NAND flash: 8-bit, async or sync, up to 2GB. - NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - - NOR devices support 16 virtual banks - GASIC: Minimal target within Qixis FPGA - PromJET rapid memory download support - Address demultiplexing handled within FPGA. - - Flexible demux allows 8 or 16 bit evaluation. - IFC Debug/Development card - - Support for 32-bit devices - Ethernet - Support two on-board RGMII 10/100/1G ethernet ports. - SGMII and XAUI support via SERDES block (see above). - 1588 support via Symmetricom board. - QIXIS System Logic FPGA - Manages system power and reset sequencing - Manages DUT, board, clock, etc. configuration for dynamic shmoo - Collects V-I-T data in background for code/power profiling. - Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion) - General fault monitoring and logging - Runs from ATX “hot” power rails allowing operation while system is off. - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz. - - Software selectable in 1MHz increments from 1-200MHz. - SERDES clocks - - Provides clocks to all SerDes blocks and slots - - 100, 125 and 156.25 MHz - Power Supplies - Dedicated regulators for VDD - - Adjustable from (0.7V to 1.3V at 80A - - Regulators can be controlled by VID and/or software - Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A - - VTT/MVREF automatically track operating voltage - Dedicated regulators/filters for AVDD supplies - Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc. - USB - Supports two USB 2.0 ports with integrated PHYs - - One type A, one type micro-AB with 1.0A power per port. - Other IO - eSDHC/MMC - - SDHC card slot - eSPI port - - High-speed serial flash - Two Serial port - Four I2C ports - XFI - XFI is supported on T4QDS-XFI board which removed slot3 and routed - four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or - direct attach cable(copper), the copper cable is used to emulate - 10GBASE-KR scenario. - So, for XFI usage, there are two scenarios, one will use fiber cable, - another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-Boot - will fixup the dtb accordingly. - It's used as: fsl_10gkr_copper:<10g_mac_name> - The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2, they - do not have to be coexist in hwconfig. If a MAC is listed in the env - "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable - will be used by default. - for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2" in - hwconfig, then both four XFI ports will use copper cable. - set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - XFI ports will use copper cable, the other two XFI ports will use fiber - cable. - -Memory map ----------- -The addresses in brackets are physical addresses. - -0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB) -0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory -0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers) -0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan -0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan -0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO -0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash -0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR -0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS -0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores - -The physical address of the last (boot page translation) varies with the actual DDR size. - -Voltage ID and VDD override --------------------- -T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage -accordingly. The voltage can also be override by command vdd_override. The -syntax is - -vdd_override , eg. 1050 is for 1.050v. - -Upon success, the actual voltage will be read back. The value is checked -for safety and any invalid value will not adjust the voltage. - -Another way to override VDD is to use environmental variable, in case of using -command is too late for some debugging. The syntax is - -setenv t4240qds_vdd_mv -saveenv -reset - -The override voltage takes effect when booting. - -Note: voltage adjustment needs to be done step by step. Changing voltage too -rapidly may cause current surge. The voltage stepping is done by software. -Users can set the final voltage directly. - -2-stage NAND/SD boot loader -------------------------------- -PBL initializes the internal SRAM and copy SPL(160K) in SRAM. -SPL further initialise DDR using SPD and environment variables -and copy U-Boot(768 KB) from NAND/SD device to DDR. -Finally SPL transers control to U-Boot for futher booting. - -SPL has following features: - - Executes within 256K - - No relocation required - -Run time view of SPL framework -------------------------------------------------- -|Area | Address | -------------------------------------------------- -|SecureBoot header | 0xFFFC0000 (32KB) | -------------------------------------------------- -|GD, BD | 0xFFFC8000 (4KB) | -------------------------------------------------- -|ENV | 0xFFFC9000 (8KB) | -------------------------------------------------- -|HEAP | 0xFFFCB000 (50KB) | -------------------------------------------------- -|STACK | 0xFFFD8000 (22KB) | -------------------------------------------------- -|U-Boot SPL | 0xFFFD8000 (160KB) | -------------------------------------------------- - -NAND Flash memory Map on T4QDS --------------------------------------------------------------- -Start End Definition Size -0x000000 0x0FFFFF U-Boot img 1MB -0x140000 0x15FFFF U-Boot env 128KB -0x160000 0x17FFFF FMAN Ucode 128KB - -Micro SD Card memory Map on T4QDS ----------------------------------------------------- -Block #blocks Definition Size -0x008 2048 U-Boot img 1MB -0x800 0016 U-Boot env 8KB -0x820 0128 FMAN ucode 64KB - -Switch Settings: (ON is 1, OFF is 0) -=============== -NAND boot SW setting: -SW1[1:8] = 10000010 -SW2[1.1] = 0 -SW6[1:4] = 1001 - -SD boot SW setting: -SW1[1:8] = 00100000 -SW2[1.1] = 0 diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c deleted file mode 100644 index 4fdd69d424..0000000000 --- a/board/freescale/t4qds/ddr.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ddr.h" - -DECLARE_GLOBAL_DATA_PTR; - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; - ulong ddr_freq; - - if (ctrl_num > 2) { - printf("Not supported controller number %d\n", ctrl_num); - return; - } - if (!pdimm->n_ranks) - return; - - /* - * we use identical timing for all slots. If needed, change the code - * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; - */ - if (popts->registered_dimm_en) - pbsp = rdimms[0]; - else - pbsp = udimms[0]; - - - /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr - * freqency and n_banks specified in board_specific_parameters table. - */ - ddr_freq = get_ddr_freq(0) / 1000000; - while (pbsp->datarate_mhz_high) { - if (pbsp->n_ranks == pdimm->n_ranks && - (pdimm->rank_density >> 30) >= pbsp->rank_gb) { - if (ddr_freq <= pbsp->datarate_mhz_high) { - popts->cpo_override = pbsp->cpo; - popts->write_data_delay = - pbsp->write_data_delay; - popts->clk_adjust = pbsp->clk_adjust; - popts->wrlvl_start = pbsp->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp->force_2t; - goto found; - } - pbsp_highest = pbsp; - } - pbsp++; - } - - if (pbsp_highest) { - printf("Error: board specific timing not found " - "for data rate %lu MT/s\n" - "Trying to use the highest speed (%u) parameters\n", - ddr_freq, pbsp_highest->datarate_mhz_high); - popts->cpo_override = pbsp_highest->cpo; - popts->write_data_delay = pbsp_highest->write_data_delay; - popts->clk_adjust = pbsp_highest->clk_adjust; - popts->wrlvl_start = pbsp_highest->wrlvl_start; - popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; - popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; - popts->twot_en = pbsp_highest->force_2t; - } else { - panic("DIMM is not supported by this board"); - } -found: - debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" - "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " - "wrlvl_ctrl_3 0x%x\n", - pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, - pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, - pbsp->wrlvl_ctl_3); - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; - /* - * Write leveling override - */ - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - - /* - * Rtt and Rtt_WR override - */ - popts->rtt_override = 0; - - /* Enable ZQ calibration */ - popts->zq_en = 1; - - /* DHC_EN =1, ODT = 75 Ohm */ - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); - - /* optimize cpo for erratum A-009942 */ - popts->cpo_sample = 0x63; -} - -int dram_init(void) -{ - phys_size_t dram_size; - - puts("Initializing....using SPD\n"); - -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) - dram_size = fsl_ddr_sdram(); -#else - /* DDR has been initialised by first stage boot loader */ - dram_size = fsl_ddr_sdram_size(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - gd->ram_size = dram_size; - - return 0; -} diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h deleted file mode 100644 index a28d4314da..0000000000 --- a/board/freescale/t4qds/ddr.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DDR_H__ -#define __DDR_H__ -struct board_specific_parameters { - u32 n_ranks; - u32 datarate_mhz_high; - u32 rank_gb; - u32 clk_adjust; - u32 wrlvl_start; - u32 wrlvl_ctl_2; - u32 wrlvl_ctl_3; - u32 cpo; - u32 write_data_delay; - u32 force_2t; -}; - -/* - * These tables contain all valid speeds we want to override with board - * specific parameters. datarate_mhz_high values need to be in ascending order - * for each n_ranks group. - */ - -static const struct board_specific_parameters udimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, - {} -}; - -static const struct board_specific_parameters rdimm0[] = { - /* - * memory controller 0 - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | - */ - {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {} -}; - -/* - * The three slots have slightly different timing. The center values are good - * for all slots. We use identical speed tables for them. In future use, if - * DIMMs require separated tables, make more entries as needed. - */ -static const struct board_specific_parameters *udimms[] = { - udimm0, -}; - -/* - * The three slots have slightly different timing. See comments above. - */ -static const struct board_specific_parameters *rdimms[] = { - rdimm0, -}; - - -#endif diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c deleted file mode 100644 index 810868ff39..0000000000 --- a/board/freescale/t4qds/eth.c +++ /dev/null @@ -1,869 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "../common/fman.h" -#include - -#include "t4240qds_qixis.h" - -#define EMI_NONE 0xFFFFFFFF -#define EMI1_RGMII 0 -#define EMI1_SLOT1 1 -#define EMI1_SLOT2 2 -#define EMI1_SLOT3 3 -#define EMI1_SLOT4 4 -#define EMI1_SLOT5 5 -#define EMI1_SLOT7 7 -#define EMI2 8 -/* Slot6 and Slot8 do not have EMI connections */ - -static int mdio_mux[NUM_FM_PORTS]; - -static const char *mdio_names[] = { - "T4240QDS_MDIO0", - "T4240QDS_MDIO1", - "T4240QDS_MDIO2", - "T4240QDS_MDIO3", - "T4240QDS_MDIO4", - "T4240QDS_MDIO5", - "NULL", - "T4240QDS_MDIO7", - "T4240QDS_10GC", -}; - -static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; -static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; -static u8 slot_qsgmii_phyaddr[5][4] = { - {0, 0, 0, 0},/* not used, to make index match slot No. */ - {0, 1, 2, 3}, - {4, 5, 6, 7}, - {8, 9, 0xa, 0xb}, - {0xc, 0xd, 0xe, 0xf}, -}; -static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0}; - -static const char *t4240qds_mdio_name_for_muxval(u8 muxval) -{ - return mdio_names[muxval]; -} - -struct mii_dev *mii_dev_for_muxval(u8 muxval) -{ - struct mii_dev *bus; - const char *name = t4240qds_mdio_name_for_muxval(muxval); - - if (!name) { - printf("No bus for muxval %x\n", muxval); - return NULL; - } - - bus = miiphy_get_dev_by_name(name); - - if (!bus) { - printf("No bus by name %s\n", name); - return NULL; - } - - return bus; -} - -struct t4240qds_mdio { - u8 muxval; - struct mii_dev *realbus; -}; - -static void t4240qds_mux_mdio(u8 muxval) -{ - u8 brdcfg4; - if ((muxval < 6) || (muxval == 7)) { - brdcfg4 = QIXIS_READ(brdcfg[4]); - brdcfg4 &= ~BRDCFG4_EMISEL_MASK; - brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); - QIXIS_WRITE(brdcfg[4], brdcfg4); - } -} - -static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, - int regnum) -{ - struct t4240qds_mdio *priv = bus->priv; - - t4240qds_mux_mdio(priv->muxval); - - return priv->realbus->read(priv->realbus, addr, devad, regnum); -} - -static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, - int regnum, u16 value) -{ - struct t4240qds_mdio *priv = bus->priv; - - t4240qds_mux_mdio(priv->muxval); - - return priv->realbus->write(priv->realbus, addr, devad, regnum, value); -} - -static int t4240qds_mdio_reset(struct mii_dev *bus) -{ - struct t4240qds_mdio *priv = bus->priv; - - return priv->realbus->reset(priv->realbus); -} - -static int t4240qds_mdio_init(char *realbusname, u8 muxval) -{ - struct t4240qds_mdio *pmdio; - struct mii_dev *bus = mdio_alloc(); - - if (!bus) { - printf("Failed to allocate T4240QDS MDIO bus\n"); - return -1; - } - - pmdio = malloc(sizeof(*pmdio)); - if (!pmdio) { - printf("Failed to allocate T4240QDS private data\n"); - free(bus); - return -1; - } - - bus->read = t4240qds_mdio_read; - bus->write = t4240qds_mdio_write; - bus->reset = t4240qds_mdio_reset; - strcpy(bus->name, t4240qds_mdio_name_for_muxval(muxval)); - - pmdio->realbus = miiphy_get_dev_by_name(realbusname); - - if (!pmdio->realbus) { - printf("No bus with name %s\n", realbusname); - free(bus); - free(pmdio); - return -1; - } - - pmdio->muxval = muxval; - bus->priv = pmdio; - - return mdio_register(bus); -} - -void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, - enum fm_port port, int offset) -{ - int interface = fm_info_get_enet_if(port); - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - - prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - if (interface == PHY_INTERFACE_MODE_SGMII || - interface == PHY_INTERFACE_MODE_QSGMII) { - switch (port) { - case FM1_DTSEC1: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy21"); - break; - case FM1_DTSEC2: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy22"); - break; - case FM1_DTSEC3: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy23"); - break; - case FM1_DTSEC4: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy24"); - break; - case FM1_DTSEC6: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy12"); - break; - case FM1_DTSEC9: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy14"); - else - fdt_set_phy_handle(blob, prop, pa, - "phy_sgmii4"); - break; - case FM1_DTSEC10: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy13"); - else - fdt_set_phy_handle(blob, prop, pa, - "phy_sgmii3"); - break; - case FM2_DTSEC1: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy41"); - break; - case FM2_DTSEC2: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy42"); - break; - case FM2_DTSEC3: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy43"); - break; - case FM2_DTSEC4: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy44"); - break; - case FM2_DTSEC6: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy32"); - break; - case FM2_DTSEC9: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy34"); - else - fdt_set_phy_handle(blob, prop, pa, - "phy_sgmii12"); - break; - case FM2_DTSEC10: - if (qsgmiiphy_fix[port]) - fdt_set_phy_handle(blob, prop, pa, - "sgmii_phy33"); - else - fdt_set_phy_handle(blob, prop, pa, - "phy_sgmii11"); - break; - default: - break; - } - } else if (interface == PHY_INTERFACE_MODE_XGMII && - ((prtcl2 == 55) || (prtcl2 == 57))) { - /* - * if the 10G is XFI, check hwconfig to see what is the - * media type, there are two types, fiber or copper, - * fix the dtb accordingly. - */ - int media_type = 0; - struct fixed_link f_link; - char lane_mode[20] = {"10GBASE-KR"}; - char buf[32] = "serdes-2,"; - int off; - - switch (port) { - case FM1_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { - media_type = 1; - fdt_set_phy_handle(blob, prop, pa, - "phy_xfi1"); - sprintf(buf, "%s%s%s", buf, "lane-a,", - (char *)lane_mode); - } - break; - case FM1_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) { - media_type = 1; - fdt_set_phy_handle(blob, prop, pa, - "phy_xfi2"); - sprintf(buf, "%s%s%s", buf, "lane-b,", - (char *)lane_mode); - } - break; - case FM2_10GEC1: - if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g1")) { - media_type = 1; - fdt_set_phy_handle(blob, prop, pa, - "phy_xfi3"); - sprintf(buf, "%s%s%s", buf, "lane-d,", - (char *)lane_mode); - } - break; - case FM2_10GEC2: - if (hwconfig_sub("fsl_10gkr_copper", "fm2_10g2")) { - media_type = 1; - fdt_set_phy_handle(blob, prop, pa, - "phy_xfi4"); - sprintf(buf, "%s%s%s", buf, "lane-c,", - (char *)lane_mode); - } - break; - default: - return; - } - - if (!media_type) { - /* fixed-link is used for XFI fiber cable */ - fdt_delprop(blob, offset, "phy-handle"); - f_link.phy_id = port; - f_link.duplex = 1; - f_link.link_speed = 10000; - f_link.pause = 0; - f_link.asym_pause = 0; - fdt_setprop(blob, offset, "fixed-link", &f_link, - sizeof(f_link)); - } else { - /* set property for copper cable */ - off = fdt_node_offset_by_compat_reg(blob, - "fsl,fman-memac-mdio", pa + 0x1000); - fdt_setprop_string(blob, off, "lane-instance", buf); - } - } -} - -void fdt_fixup_board_enet(void *fdt) -{ - int i; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - - prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - switch (mdio_mux[i]) { - case EMI1_SLOT1: - fdt_status_okay_by_alias(fdt, "emi1_slot1"); - break; - case EMI1_SLOT2: - fdt_status_okay_by_alias(fdt, "emi1_slot2"); - break; - case EMI1_SLOT3: - fdt_status_okay_by_alias(fdt, "emi1_slot3"); - break; - case EMI1_SLOT4: - fdt_status_okay_by_alias(fdt, "emi1_slot4"); - break; - default: - break; - } - break; - case PHY_INTERFACE_MODE_XGMII: - /* check if it's XFI interface for 10g */ - if ((prtcl2 == 55) || (prtcl2 == 57)) { - if (i == FM1_10GEC1 && hwconfig_sub( - "fsl_10gkr_copper", "fm1_10g1")) - fdt_status_okay_by_alias( - fdt, "xfi_pcs_mdio1"); - if (i == FM1_10GEC2 && hwconfig_sub( - "fsl_10gkr_copper", "fm1_10g2")) - fdt_status_okay_by_alias( - fdt, "xfi_pcs_mdio2"); - if (i == FM2_10GEC1 && hwconfig_sub( - "fsl_10gkr_copper", "fm2_10g1")) - fdt_status_okay_by_alias( - fdt, "xfi_pcs_mdio3"); - if (i == FM2_10GEC2 && hwconfig_sub( - "fsl_10gkr_copper", "fm2_10g2")) - fdt_status_okay_by_alias( - fdt, "xfi_pcs_mdio4"); - break; - } - switch (i) { - case FM1_10GEC1: - fdt_status_okay_by_alias(fdt, "emi2_xauislot1"); - break; - case FM1_10GEC2: - fdt_status_okay_by_alias(fdt, "emi2_xauislot2"); - break; - case FM2_10GEC1: - fdt_status_okay_by_alias(fdt, "emi2_xauislot3"); - break; - case FM2_10GEC2: - fdt_status_okay_by_alias(fdt, "emi2_xauislot4"); - break; - default: - break; - } - break; - default: - break; - } - } -} - -static void initialize_qsgmiiphy_fix(void) -{ - int i; - unsigned short reg; - - for (i = 1; i <= 4; i++) { - /* - * Try to read if a SGMII card is used, we do it slot by slot. - * if a SGMII PHY address is valid on a slot, then we mark - * all ports on the slot, then fix the PHY address for the - * marked port when doing dtb fixup. - */ - if (miiphy_read(mdio_names[i], - SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) { - debug("Slot%d PHY ID register 2 read failed\n", i); - continue; - } - - debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg); - - if (reg == 0xFFFF) { - /* No physical device present at this address */ - continue; - } - - switch (i) { - case 1: - qsgmiiphy_fix[FM1_DTSEC5] = 1; - qsgmiiphy_fix[FM1_DTSEC6] = 1; - qsgmiiphy_fix[FM1_DTSEC9] = 1; - qsgmiiphy_fix[FM1_DTSEC10] = 1; - slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR; - slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR; - slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR; - slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR; - break; - case 2: - qsgmiiphy_fix[FM1_DTSEC1] = 1; - qsgmiiphy_fix[FM1_DTSEC2] = 1; - qsgmiiphy_fix[FM1_DTSEC3] = 1; - qsgmiiphy_fix[FM1_DTSEC4] = 1; - slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR; - slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR; - slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR; - slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR; - break; - case 3: - qsgmiiphy_fix[FM2_DTSEC5] = 1; - qsgmiiphy_fix[FM2_DTSEC6] = 1; - qsgmiiphy_fix[FM2_DTSEC9] = 1; - qsgmiiphy_fix[FM2_DTSEC10] = 1; - slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR; - slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR; - slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR; - slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR; - break; - case 4: - qsgmiiphy_fix[FM2_DTSEC1] = 1; - qsgmiiphy_fix[FM2_DTSEC2] = 1; - qsgmiiphy_fix[FM2_DTSEC3] = 1; - qsgmiiphy_fix[FM2_DTSEC4] = 1; - slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR; - slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR; - slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR; - slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR; - break; - default: - break; - } - } -} - -int board_eth_init(bd_t *bis) -{ -#if defined(CONFIG_FMAN_ENET) - int i, idx, lane, slot, interface; - struct memac_mdio_info dtsec_mdio_info; - struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - - /* Initialize the mdio_mux array so we can recognize empty elements */ - for (i = 0; i < NUM_FM_PORTS; i++) - mdio_mux[i] = EMI_NONE; - - dtsec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; - - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fm_memac_mdio_init(bis, &dtsec_mdio_info); - - tgec_mdio_info.regs = - (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; - tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; - - /* Register the 10G MDIO bus */ - fm_memac_mdio_init(bis, &tgec_mdio_info); - - /* Register the muxing front-ends to the MDIO buses */ - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); - t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); - t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); - - initialize_qsgmiiphy_fix(); - - switch (srds_prtcl_s1) { - case 1: - case 2: - case 4: - /* XAUI/HiGig in Slot1 and Slot2 */ - fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); - break; - case 27: - case 28: - case 35: - case 36: - /* SGMII in Slot1 and Slot2 */ - fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); - fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); - fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); - fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); - fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); - fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { - fm_info_set_phy_address(FM1_DTSEC9, - slot_qsgmii_phyaddr[1][3]); - fm_info_set_phy_address(FM1_DTSEC10, - slot_qsgmii_phyaddr[1][2]); - } - break; - case 37: - case 38: - fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); - fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); - fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); - fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); - fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); - fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { - fm_info_set_phy_address(FM1_DTSEC9, - slot_qsgmii_phyaddr[1][2]); - fm_info_set_phy_address(FM1_DTSEC10, - slot_qsgmii_phyaddr[1][3]); - } - break; - case 39: - case 40: - case 45: - case 46: - case 47: - case 48: - fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); - fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); - if ((srds_prtcl_s2 != 55) && (srds_prtcl_s2 != 57)) { - fm_info_set_phy_address(FM1_DTSEC10, - slot_qsgmii_phyaddr[1][2]); - fm_info_set_phy_address(FM1_DTSEC9, - slot_qsgmii_phyaddr[1][3]); - } - fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); - fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); - fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); - fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); - break; - default: - puts("Invalid SerDes1 protocol for T4240QDS\n"); - break; - } - - for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { - idx = i - FM1_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_QSGMII) { - if (idx <= 3) - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_A); - else - lane = serdes_get_first_lane(FSL_SRDS_1, - QSGMII_FM1_B); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - debug("FM1@DTSEC%u expects QSGMII in slot %u\n", - idx + 1, slot); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - SGMII_FM1_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - debug("FM1@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - } - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - switch (slot) { - case 1: - mdio_mux[i] = EMI1_SLOT1; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 2: - mdio_mux[i] = EMI1_SLOT2; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - /* FM1 DTSEC5 routes to RGMII with EC2 */ - debug("FM1@DTSEC%u is RGMII at address %u\n", - idx + 1, 2); - if (i == FM1_DTSEC5) - fm_info_set_phy_address(i, 2); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { - idx = i - FM1_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { - /* A fake PHY address to make U-Boot happy */ - fm_info_set_phy_address(i, i); - } else { - lane = serdes_get_first_lane(FSL_SRDS_1, - XAUI_FM1_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm1[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - } - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - -#if (CONFIG_SYS_NUM_FMAN == 2) - switch (srds_prtcl_s2) { - case 1: - case 2: - case 4: - /* XAUI/HiGig in Slot3 and Slot4 */ - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); - break; - case 6: - case 7: - case 12: - case 13: - case 14: - case 15: - case 16: - case 21: - case 22: - case 23: - case 24: - case 25: - case 26: - /* XAUI/HiGig in Slot3, SGMII in Slot4 */ - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - break; - case 27: - case 28: - case 35: - case 36: - /* SGMII in Slot3 and Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); - fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); - fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); - fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); - break; - case 37: - case 38: - /* QSGMII in Slot3 and Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); - fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); - fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); - fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); - break; - case 39: - case 40: - case 45: - case 46: - case 47: - case 48: - /* SGMII in Slot3 */ - fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); - fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); - fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); - fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); - /* QSGMII in Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - break; - case 49: - case 50: - case 51: - case 52: - case 53: - case 54: - fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - break; - case 55: - case 57: - /* XFI in Slot3, SGMII in Slot4 */ - fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); - fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); - fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); - fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); - break; - default: - puts("Invalid SerDes2 protocol for T4240QDS\n"); - break; - } - - for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { - idx = i - FM2_DTSEC1; - interface = fm_info_get_enet_if(i); - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - if (interface == PHY_INTERFACE_MODE_QSGMII) { - if (idx <= 3) - lane = serdes_get_first_lane(FSL_SRDS_2, - QSGMII_FM2_A); - else - lane = serdes_get_first_lane(FSL_SRDS_2, - QSGMII_FM2_B); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - debug("FM2@DTSEC%u expects QSGMII in slot %u\n", - idx + 1, slot); - } else { - lane = serdes_get_first_lane(FSL_SRDS_2, - SGMII_FM2_DTSEC1 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - debug("FM2@DTSEC%u expects SGMII in slot %u\n", - idx + 1, slot); - } - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - switch (slot) { - case 3: - mdio_mux[i] = EMI1_SLOT3; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - case 4: - mdio_mux[i] = EMI1_SLOT4; - fm_info_set_mdio(i, - mii_dev_for_muxval(mdio_mux[i])); - break; - }; - break; - case PHY_INTERFACE_MODE_RGMII: - /* - * If DTSEC5 is RGMII, then it's routed via via EC1 to - * the first on-board RGMII port. If DTSEC6 is RGMII, - * then it's routed via via EC2 to the second on-board - * RGMII port. - */ - debug("FM2@DTSEC%u is RGMII at address %u\n", - idx + 1, i == FM2_DTSEC5 ? 1 : 2); - fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); - mdio_mux[i] = EMI1_RGMII; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } - - for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { - idx = i - FM2_10GEC1; - switch (fm_info_get_enet_if(i)) { - case PHY_INTERFACE_MODE_XGMII: - if ((srds_prtcl_s2 == 55) || (srds_prtcl_s2 == 57)) { - /* A fake PHY address to make U-Boot happy */ - fm_info_set_phy_address(i, i); - } else { - lane = serdes_get_first_lane(FSL_SRDS_2, - XAUI_FM2_MAC9 + idx); - if (lane < 0) - break; - slot = lane_to_slot_fsm2[lane]; - if (QIXIS_READ(present2) & (1 << (slot - 1))) - fm_disable_port(i); - } - mdio_mux[i] = EMI2; - fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); - break; - default: - break; - } - } -#endif /* CONFIG_SYS_NUM_FMAN */ - - cpu_eth_init(bis); -#endif /* CONFIG_FMAN_ENET */ - - return pci_eth_init(bis); -} diff --git a/board/freescale/t4qds/law.c b/board/freescale/t4qds/law.c deleted file mode 100644 index cb7bdf391b..0000000000 --- a/board/freescale/t4qds/law.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), -#endif -#ifdef QIXIS_BASE_PHYS - SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - /* Limit DCSR to 32M to access NPC Trace Buffer */ - SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), -#endif -#ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), -#endif -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4qds/pci.c b/board/freescale/t4qds/pci.c deleted file mode 100644 index 26e2a0af4a..0000000000 --- a/board/freescale/t4qds/pci.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2012 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, bd_t *bd) -{ - FT_FSL_PCI_SETUP; -} diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c deleted file mode 100644 index d72d207a76..0000000000 --- a/board/freescale/t4qds/spl.c +++ /dev/null @@ -1,145 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../common/qixis.h" -#include "t4240qds_qixis.h" - -#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 - -DECLARE_GLOBAL_DATA_PTR; - -phys_size_t get_effective_memsize(void) -{ - return CONFIG_SYS_L3_SIZE; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -void board_init_f(ulong bootflag) -{ - u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; -#ifdef CONFIG_SPL_NAND_BOOT - u32 porsr1, pinctl; -#endif - -#ifdef CONFIG_SPL_NAND_BOOT - porsr1 = in_be32(&gur->porsr1); - pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); - out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); -#endif - /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ - memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); - - /* Update GD pointer */ - gd = (gd_t *)(CONFIG_SPL_GD_ADDR); - - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("" : : : "memory"); - - console_init_f(); - - /* initialize selected port with appropriate baud rate */ - sys_clk = get_board_sys_clk(); - plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; - ccb_clk = sys_clk * plat_ratio / 2; - - NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, - ccb_clk / 16 / CONFIG_BAUDRATE); - -#ifdef CONFIG_SPL_MMC_BOOT - puts("\nSD boot...\n"); -#elif defined(CONFIG_SPL_NAND_BOOT) - puts("\nNAND boot...\n"); -#endif - relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); -} - -void board_init_r(gd_t *gd, ulong dest_addr) -{ - bd_t *bd; - - bd = (bd_t *)(gd + sizeof(gd_t)); - memset(bd, 0, sizeof(bd_t)); - gd->bd = bd; - bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; - bd->bi_memsize = CONFIG_SYS_L3_SIZE; - - arch_cpu_init(); - get_clocks(); - mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, - CONFIG_SPL_RELOC_MALLOC_SIZE); - gd->flags |= GD_FLG_FULL_MALLOC_INIT; - -#ifdef CONFIG_SPL_NAND_BOOT - nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif -#ifdef CONFIG_SPL_MMC_BOOT - mmc_initialize(bd); - mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)SPL_ENV_ADDR); -#endif - - gd->env_addr = (ulong)(SPL_ENV_ADDR); - gd->env_valid = ENV_VALID; - - i2c_init_all(); - - dram_init(); - -#ifdef CONFIG_SPL_MMC_BOOT - mmc_boot(); -#elif defined(CONFIG_SPL_NAND_BOOT) - nand_boot(); -#endif -} diff --git a/board/freescale/t4qds/t4240emu.c b/board/freescale/t4qds/t4240emu.c deleted file mode 100644 index 8f2032acc7..0000000000 --- a/board/freescale/t4qds/t4240emu.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int checkboard(void) -{ - struct cpu_type *cpu = gd->arch.cpu; - - printf("Board: %sEMU\n", cpu->name); - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - - return 0; -} diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c deleted file mode 100644 index 543a2cb6e2..0000000000 --- a/board/freescale/t4qds/t4240qds.c +++ /dev/null @@ -1,929 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/qixis.h" -#include "../common/vsc3316_3308.h" -#include "t4qds.h" -#include "t4240qds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, - {8, 8}, {9, 9}, {14, 14}, {15, 15} }; - -static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, - {10, 10}, {11, 11}, {12, 12}, {13, 13} }; - -static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, - {10, 11}, {11, 10}, {12, 2}, {13, 3} }; - -static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, - {8, 9}, {9, 8}, {14, 1}, {15, 0} }; - -int checkboard(void) -{ - char buf[64]; - u8 sw; - struct cpu_type *cpu = gd->arch.cpu; - unsigned int i; - - printf("Board: %sQDS, ", cpu->name); - printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", - QIXIS_READ(id), QIXIS_READ(arch)); - - sw = QIXIS_READ(brdcfg[0]); - sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; - - if (sw < 0x8) - printf("vBank: %d\n", sw); - else if (sw == 0x8) - puts("Promjet\n"); - else if (sw == 0x9) - puts("NAND\n"); - else - printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); - - printf("FPGA: v%d (%s), build %d", - (int)QIXIS_READ(scver), qixis_read_tag(buf), - (int)qixis_read_minor()); - /* the timestamp string contains "\n" at the end */ - printf(" on %s", qixis_read_time(buf)); - - /* - * Display the actual SERDES reference clocks as configured by the - * dip switches on the board. Note that the SWx registers could - * technically be set to force the reference clocks to match the - * values that the SERDES expects (or vice versa). For now, however, - * we just display both values and hope the user notices when they - * don't match. - */ - puts("SERDES Reference Clocks: "); - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < MAX_SERDES; i++) { - static const char * const freq[] = { - "100", "125", "156.25", "161.1328125"}; - unsigned int clock = (sw >> (6 - 2 * i)) & 3; - - printf("SERDES%u=%sMHz ", i+1, freq[clock]); - } - puts("\n"); - - return 0; -} - -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; - -#ifdef CONFIG_DM_I2C - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - -/* - * read_voltage from sensor on I2C bus - * We use average of 4 readings, waiting for 532us befor another reading - */ -#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ -#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ - -static inline int read_voltage(void) -{ - int i, ret, voltage_read = 0; - u16 vol_mon; -#ifdef CONFIG_DM_I2C - struct udevice *dev; - int bus_num = 0; -#endif - - for (i = 0; i < NUM_READINGS; i++) { -#ifdef CONFIG_DM_I2C - ret = i2c_get_chip_for_busnum(bus_num, I2C_VOL_MONITOR_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - - ret = dm_i2c_read(dev, - I2C_VOL_MONITOR_BUS_V_OFFSET, - (void *)&vol_mon, 2); -#else - ret = i2c_read(I2C_VOL_MONITOR_ADDR, - I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); -#endif - if (ret) { - printf("VID: failed to read core voltage\n"); - return ret; - } - if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { - printf("VID: Core voltage sensor error\n"); - return -1; - } - debug("VID: bus voltage reads 0x%04x\n", vol_mon); - /* LSB = 4mv */ - voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; - udelay(WAIT_FOR_ADC); - } - /* calculate the average */ - voltage_read /= NUM_READINGS; - - return voltage_read; -} - -/* - * We need to calculate how long before the voltage starts to drop or increase - * It returns with the loop count. Each loop takes several readings (532us) - */ -static inline int wait_for_voltage_change(int vdd_last) -{ - int timeout, vdd_current; - - vdd_current = read_voltage(); - /* wait until voltage starts to drop */ - for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && - timeout < 100; timeout++) { - vdd_current = read_voltage(); - } - if (timeout >= 100) { - printf("VID: Voltage adjustment timeout\n"); - return -1; - } - return timeout; -} - -/* - * argument 'wait' is the time we know the voltage difference can be measured - * this function keeps reading the voltage until it is stable - */ -static inline int wait_for_voltage_stable(int wait) -{ - int timeout, vdd_current, vdd_last; - - vdd_last = read_voltage(); - udelay(wait * NUM_READINGS * WAIT_FOR_ADC); - /* wait until voltage is stable */ - vdd_current = read_voltage(); - for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && - timeout < 100; timeout++) { - vdd_last = vdd_current; - udelay(wait * NUM_READINGS * WAIT_FOR_ADC); - vdd_current = read_voltage(); - } - if (timeout >= 100) { - printf("VID: Voltage adjustment timeout\n"); - return -1; - } - - return vdd_current; -} - -static inline int set_voltage(u8 vid) -{ - int wait, vdd_last; - - vdd_last = read_voltage(); - QIXIS_WRITE(brdcfg[6], vid); - wait = wait_for_voltage_change(vdd_last); - if (wait < 0) - return -1; - debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); - wait = wait ? wait : 1; - - vdd_last = wait_for_voltage_stable(wait); - if (vdd_last < 0) - return -1; - debug("VID: Current voltage is %d mV\n", vdd_last); - - return vdd_last; -} - - -static int adjust_vdd(ulong vdd_override) -{ - int re_enable = disable_interrupts(); - ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 fusesr; - u8 vid, vid_current; - int vdd_target, vdd_current, vdd_last; - int ret; - unsigned long vdd_string_override; - char *vdd_string; - static const uint16_t vdd[32] = { - 0, /* unused */ - 9875, /* 0.9875V */ - 9750, - 9625, - 9500, - 9375, - 9250, - 9125, - 9000, - 8875, - 8750, - 8625, - 8500, - 8375, - 8250, - 8125, - 10000, /* 1.0000V */ - 10125, - 10250, - 10375, - 10500, - 10625, - 10750, - 10875, - 11000, - 0, /* reserved */ - }; - struct vdd_drive { - u8 vid; - unsigned voltage; - }; - - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0); - if (ret) { - debug("VID: I2c failed to switch channel\n"); - ret = -1; - goto exit; - } - - /* get the voltage ID from fuse status register */ - fusesr = in_be32(&gur->dcfg_fusesr); - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_VID_MASK; - if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { - vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & - FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; - } - vdd_target = vdd[vid]; - - /* check override variable for overriding VDD */ - vdd_string = env_get("t4240qds_vdd_mv"); - if (vdd_override == 0 && vdd_string && - !strict_strtoul(vdd_string, 10, &vdd_string_override)) - vdd_override = vdd_string_override; - if (vdd_override >= 819 && vdd_override <= 1212) { - vdd_target = vdd_override * 10; /* convert to 1/10 mV */ - debug("VDD override is %lu\n", vdd_override); - } else if (vdd_override != 0) { - printf("Invalid value.\n"); - } - - if (vdd_target == 0) { - debug("VID: VID not used\n"); - ret = 0; - goto exit; - } else { - /* round up and divice by 10 to get a value in mV */ - vdd_target = DIV_ROUND_UP(vdd_target, 10); - debug("VID: vid = %d mV\n", vdd_target); - } - - /* - * Check current board VID setting - * Voltage regulator support output to 6.250mv step - * The highes voltage allowed for this board is (vid=0x40) 1.21250V - * the lowest is (vid=0x7f) 0.81875V - */ - vid_current = QIXIS_READ(brdcfg[6]); - vdd_current = 121250 - (vid_current - 0x40) * 625; - debug("VID: Current vid setting is (0x%x) %d mV\n", - vid_current, vdd_current/100); - - /* - * Read voltage monitor to check real voltage. - * Voltage monitor LSB is 4mv. - */ - vdd_last = read_voltage(); - if (vdd_last < 0) { - printf("VID: Could not read voltage sensor abort VID adjustment\n"); - ret = -1; - goto exit; - } - debug("VID: Core voltage is at %d mV\n", vdd_last); - /* - * Adjust voltage to at or 8mV above target. - * Each step of adjustment is 6.25mV. - * Stepping down too fast may cause over current. - */ - while (vdd_last > 0 && vid_current < 0x80 && - vdd_last > (vdd_target + 8)) { - vid_current++; - vdd_last = set_voltage(vid_current); - } - /* - * Check if we need to step up - * This happens when board voltage switch was set too low - */ - while (vdd_last > 0 && vid_current >= 0x40 && - vdd_last < vdd_target + 2) { - vid_current--; - vdd_last = set_voltage(vid_current); - } - if (vdd_last > 0) - printf("VID: Core voltage %d mV\n", vdd_last); - else - ret = -1; - -exit: - if (re_enable) - enable_interrupts(); - return ret; -} - -/* Configure Crossbar switches for Front-Side SerDes Ports */ -int config_frontside_crossbar_vsc3316(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s1, srds_prtcl_s2; - int ret; - - ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS, 0); - if (ret) - return ret; - - srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS1_PRTCL; - srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; - switch (srds_prtcl_s1) { - case 37: - case 38: - /* swap first lane and third lane on slot1 */ - vsc3316_fsm1_tx[0][1] = 14; - vsc3316_fsm1_tx[6][1] = 0; - vsc3316_fsm1_rx[1][1] = 2; - vsc3316_fsm1_rx[6][1] = 13; - case 39: - case 40: - case 45: - case 46: - case 47: - case 48: - /* swap first lane and third lane on slot2 */ - vsc3316_fsm1_tx[2][1] = 8; - vsc3316_fsm1_tx[4][1] = 6; - vsc3316_fsm1_rx[2][1] = 10; - vsc3316_fsm1_rx[5][1] = 5; - default: - ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); - if (ret) - return ret; - break; - } - - srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS2_PRTCL; - srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; - switch (srds_prtcl_s2) { - case 37: - case 38: - /* swap first lane and third lane on slot3 */ - vsc3316_fsm2_tx[2][1] = 11; - vsc3316_fsm2_tx[5][1] = 4; - vsc3316_fsm2_rx[2][1] = 9; - vsc3316_fsm2_rx[4][1] = 7; - case 39: - case 40: - case 45: - case 46: - case 47: - case 48: - case 49: - case 50: - case 51: - case 52: - case 53: - case 54: - /* swap first lane and third lane on slot4 */ - vsc3316_fsm2_tx[6][1] = 3; - vsc3316_fsm2_tx[1][1] = 12; - vsc3316_fsm2_rx[0][1] = 1; - vsc3316_fsm2_rx[6][1] = 15; - default: - ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); - if (ret) - return ret; - ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); - if (ret) - return ret; - break; - } - - return 0; -} - -int config_backside_crossbar_mux(void) -{ - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 srds_prtcl_s3, srds_prtcl_s4; - u8 brdcfg; - - srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS3_PRTCL; - srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; - switch (srds_prtcl_s3) { - case 0: - /* SerDes3 is not enabled */ - break; - case 1: - case 2: - case 9: - case 10: - /* SD3(0:7) => SLOT5(0:7) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD3MX_MASK; - brdcfg |= BRDCFG12_SD3MX_SLOT5; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - case 17: - case 18: - case 19: - case 20: - /* SD3(4:7) => SLOT6(0:3) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD3MX_MASK; - brdcfg |= BRDCFG12_SD3MX_SLOT6; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - default: - printf("WARNING: unsupported for SerDes3 Protocol %d\n", - srds_prtcl_s3); - return -1; - } - - srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & - FSL_CORENET2_RCWSR4_SRDS4_PRTCL; - srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; - switch (srds_prtcl_s4) { - case 0: - /* SerDes4 is not enabled */ - break; - case 1: - case 2: - /* 10b, SD4(0:7) => SLOT7(0:7) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_SLOT7; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 3: - case 4: - case 5: - case 6: - case 7: - case 8: - /* x1b, SD4(4:7) => SLOT8(0:3) */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_SLOT8; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - case 9: - case 10: - case 11: - case 12: - case 13: - case 14: - case 15: - case 16: - case 18: - /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ - brdcfg = QIXIS_READ(brdcfg[12]); - brdcfg &= ~BRDCFG12_SD4MX_MASK; - brdcfg |= BRDCFG12_SD4MX_AURO_SATA; - QIXIS_WRITE(brdcfg[12], brdcfg); - break; - default: - printf("WARNING: unsupported for SerDes4 Protocol %d\n", - srds_prtcl_s4); - return -1; - } - - return 0; -} - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - /* Disable remote I2C connection to qixis fpga */ - QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); - - /* - * Adjust core voltage according to voltage ID - * This function changes I2C mux to channel 2. - */ - if (adjust_vdd(0)) - printf("Warning: Adjusting core voltage failed.\n"); - - /* Configure board SERDES ports crossbar */ - config_frontside_crossbar_vsc3316(); - config_backside_crossbar_mux(); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - - return 0; -} - -unsigned long get_board_sys_clk(void) -{ - u8 sysclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("SYS Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); - } -#endif - - switch (sysclk_conf & 0x0F) { - case QIXIS_SYSCLK_83: - return 83333333; - case QIXIS_SYSCLK_100: - return 100000000; - case QIXIS_SYSCLK_125: - return 125000000; - case QIXIS_SYSCLK_133: - return 133333333; - case QIXIS_SYSCLK_150: - return 150000000; - case QIXIS_SYSCLK_160: - return 160000000; - case QIXIS_SYSCLK_166: - return 166666666; - } - return 66666666; -} - -unsigned long get_board_ddr_clk(void) -{ - u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); -#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT - /* use accurate clock measurement */ - int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); - int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); - u32 val; - - val = freq * base; - if (val) { - debug("DDR Clock measurement is: %d\n", val); - return val; - } else { - printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); - } -#endif - - switch ((ddrclk_conf & 0x30) >> 4) { - case QIXIS_DDRCLK_100: - return 100000000; - case QIXIS_DDRCLK_125: - return 125000000; - case QIXIS_DDRCLK_133: - return 133333333; - } - return 66666666; -} - -int misc_init_r(void) -{ - u8 sw; - void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - serdes_corenet_t *srds_regs; - u32 actual[MAX_SERDES]; - u32 pllcr0, expected; - unsigned int i; - - sw = QIXIS_READ(brdcfg[2]); - for (i = 0; i < MAX_SERDES; i++) { - unsigned int clock = (sw >> (6 - 2 * i)) & 3; - switch (clock) { - case 0: - actual[i] = SRDS_PLLCR0_RFCK_SEL_100; - break; - case 1: - actual[i] = SRDS_PLLCR0_RFCK_SEL_125; - break; - case 2: - actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; - break; - case 3: - actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; - break; - } - } - - for (i = 0; i < MAX_SERDES; i++) { - srds_regs = srds_base + i * 0x1000; - pllcr0 = srds_regs->bank[0].pllcr0; - expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; - if (expected != actual[i]) { - printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", - i + 1, serdes_clock_to_string(expected), - serdes_clock_to_string(actual[i])); - } - } - - return 0; -} - -int ft_board_setup(void *blob, bd_t *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_PCI - pci_of_setup(blob, bd); -#endif - - fdt_fixup_liodn(blob); - fsl_fdt_fixup_dr_usb(blob, bd); - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif - fdt_fixup_board_enet(blob); -#endif - - return 0; -} - -/* - * This function is called by bdinfo to print detail board information. - * As an exmaple for future board, we organize the messages into - * several sections. If applicable, the message is in the format of - * = - * It should aligned with normal output of bdinfo command. - * - * Voltage: Core, DDR and another configurable voltages - * Clock : Critical clocks which are not printed already - * RCW : RCW source if not printed already - * Misc : Other important information not in above catagories - */ -void board_detail(void) -{ - int i; - u8 brdcfg[16], dutcfg[16], rst_ctl; - int vdd, rcwsrc; - static const char * const clk[] = {"66.67", "100", "125", "133.33"}; - - for (i = 0; i < 16; i++) { - brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); - dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); - } - - /* Voltage secion */ - if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR, 0)) { - vdd = read_voltage(); - if (vdd > 0) - printf("Core voltage= %d mV\n", vdd); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - } - - printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); - - /* clock section */ - printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", - clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); - - /* RCW section */ - rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); - puts("RCW source = "); - switch (rcwsrc) { - case 0x017: - case 0x01f: - puts("8-bit NOR\n"); - break; - case 0x027: - case 0x02F: - puts("16-bit NOR\n"); - break; - case 0x040: - puts("SDHC/eMMC\n"); - break; - case 0x044: - puts("SPI 16-bit addressing\n"); - break; - case 0x045: - puts("SPI 24-bit addressing\n"); - break; - case 0x048: - puts("I2C normal addressing\n"); - break; - case 0x049: - puts("I2C extended addressing\n"); - break; - case 0x108: - case 0x109: - case 0x10a: - case 0x10b: - puts("8-bit NAND, 2KB\n"); - break; - default: - if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) - puts("Hard-coded RCW\n"); - else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) - puts("8-bit NAND, 4KB\n"); - else - puts("unknown\n"); - break; - } - - /* Misc section */ - rst_ctl = QIXIS_READ(rst_ctl); - puts("HRESET_REQ = "); - switch (rst_ctl & 0x30) { - case 0x00: - puts("Ignored\n"); - break; - case 0x10: - puts("Assert HRESET\n"); - break; - case 0x30: - puts("Reset system\n"); - break; - default: - puts("N/A\n"); - break; - } -} - -/* - * Reverse engineering switch settings. - * Some bits cannot be figured out. They will be displayed as - * underscore in binary format. mask[] has those bits. - * Some bits are calculated differently than the actual switches - * if booting with overriding by FPGA. - */ -void qixis_dump_switch(void) -{ - int i; - u8 sw[9]; - - /* - * Any bit with 1 means that bit cannot be reverse engineered. - * It will be displayed as _ in binary format. - */ - static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; - char buf[10]; - u8 brdcfg[16], dutcfg[16]; - - for (i = 0; i < 16; i++) { - brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); - dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); - } - - sw[0] = dutcfg[0]; - sw[1] = (dutcfg[1] << 0x07) | - ((dutcfg[12] & 0xC0) >> 1) | - ((dutcfg[11] & 0xE0) >> 3) | - ((dutcfg[6] & 0x80) >> 6) | - ((dutcfg[1] & 0x80) >> 7); - sw[2] = ((brdcfg[1] & 0x0f) << 4) | - ((brdcfg[1] & 0x30) >> 2) | - ((brdcfg[1] & 0x40) >> 5) | - ((brdcfg[1] & 0x80) >> 7); - sw[3] = brdcfg[2]; - sw[4] = ((dutcfg[2] & 0x01) << 7) | - ((dutcfg[2] & 0x06) << 4) | - ((~QIXIS_READ(present)) & 0x10) | - ((brdcfg[3] & 0x80) >> 4) | - ((brdcfg[3] & 0x01) << 2) | - ((brdcfg[6] == 0x62) ? 3 : - ((brdcfg[6] == 0x5a) ? 2 : - ((brdcfg[6] == 0x5e) ? 1 : 0))); - sw[5] = ((brdcfg[0] & 0x0f) << 4) | - ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | - ((brdcfg[0] & 0x40) >> 5); - sw[6] = (brdcfg[11] & 0x20) | - ((brdcfg[5] & 0x02) << 3); - sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | - ((brdcfg[5] & 0x10) << 2); - sw[8] = ((brdcfg[12] & 0x08) << 4) | - ((brdcfg[12] & 0x03) << 5); - - puts("DIP switch (reverse-engineering)\n"); - for (i = 0; i < 9; i++) { - printf("SW%d = 0b%s (0x%02x)\n", - i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); - } -} - -static int do_vdd_adjust(struct cmd_tbl *cmdtp, - int flag, int argc, - char *const argv[]) -{ - ulong override; - - if (argc < 2) - return CMD_RET_USAGE; - if (!strict_strtoul(argv[1], 10, &override)) - adjust_vdd(override); /* the value is checked by callee */ - else - return CMD_RET_USAGE; - - return 0; -} - -U_BOOT_CMD( - vdd_override, 2, 0, do_vdd_adjust, - "Override VDD", - "- override with the voltage specified in mV, eg. 1050" -); diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h deleted file mode 100644 index 52e8d5a7be..0000000000 --- a/board/freescale/t4qds/t4240qds_qixis.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __T4020QDS_QIXIS_H__ -#define __T4020QDS_QIXIS_H__ - -/* Definitions of QIXIS Registers for T4020QDS */ - -/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ -#define BRDCFG4_EMISEL_MASK 0xE0 -#define BRDCFG4_EMISEL_SHIFT 5 - -/* SYSCLK */ -#define QIXIS_SYSCLK_66 0x0 -#define QIXIS_SYSCLK_83 0x1 -#define QIXIS_SYSCLK_100 0x2 -#define QIXIS_SYSCLK_125 0x3 -#define QIXIS_SYSCLK_133 0x4 -#define QIXIS_SYSCLK_150 0x5 -#define QIXIS_SYSCLK_160 0x6 -#define QIXIS_SYSCLK_166 0x7 - -/* DDRCLK */ -#define QIXIS_DDRCLK_66 0x0 -#define QIXIS_DDRCLK_100 0x1 -#define QIXIS_DDRCLK_125 0x2 -#define QIXIS_DDRCLK_133 0x3 - -#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ - -#define BRDCFG12_SD3EN_MASK 0x20 -#define BRDCFG12_SD3MX_MASK 0x08 -#define BRDCFG12_SD3MX_SLOT5 0x08 -#define BRDCFG12_SD3MX_SLOT6 0x00 -#define BRDCFG12_SD4EN_MASK 0x04 -#define BRDCFG12_SD4MX_MASK 0x03 -#define BRDCFG12_SD4MX_SLOT7 0x02 -#define BRDCFG12_SD4MX_SLOT8 0x01 -#define BRDCFG12_SD4MX_AURO_SATA 0x00 -#endif diff --git a/board/freescale/t4qds/t4_nand_rcw.cfg b/board/freescale/t4qds/t4_nand_rcw.cfg deleted file mode 100644 index 9386be0faa..0000000000 --- a/board/freescale/t4qds/t4_nand_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#serdes protocol 1_27_5_11 -1607001b 18101b16 00000000 00000000 -04362858 30548c00 e8020000 f5000000 -00000000 ee0000ee 00000000 000307fc -00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4qds/t4_pbi.cfg b/board/freescale/t4qds/t4_pbi.cfg deleted file mode 100644 index 8d460039bf..0000000000 --- a/board/freescale/t4qds/t4_pbi.cfg +++ /dev/null @@ -1,21 +0,0 @@ -#PBI commands -#Initialize CPC1 -09010000 00200400 -09138000 00000000 -091380c0 00000100 -#512KB SRAM -09010100 00000000 -09010104 fff80009 -09010f00 08000000 -#enable CPC1 -09010000 80000000 -#Configure LAW for CPC1 -09000d00 00000000 -09000d04 fff80000 -09000d08 81000012 -#Configure alternate space -09000010 00000000 -09000014 ff000000 -09000018 81000000 -#Flush PBL data -091380c0 00100000 diff --git a/board/freescale/t4qds/t4_sd_rcw.cfg b/board/freescale/t4qds/t4_sd_rcw.cfg deleted file mode 100644 index 54beb6783d..0000000000 --- a/board/freescale/t4qds/t4_sd_rcw.cfg +++ /dev/null @@ -1,7 +0,0 @@ -#PBL preamble and RCW header -aa55aa55 010e0100 -#serdes protocol 1_27_5_11 -1607001b 18101b16 00000000 00000000 -04362858 30548c00 68020000 f5000000 -00000000 ee0000ee 00000000 000307fc -00000000 00000000 00000000 00000028 diff --git a/board/freescale/t4qds/t4qds.h b/board/freescale/t4qds/t4qds.h deleted file mode 100644 index 4a8e91b58f..0000000000 --- a/board/freescale/t4qds/t4qds.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CORENET_DS_H__ -#define __CORENET_DS_H__ - -void fdt_fixup_board_enet(void *blob); -void pci_of_setup(void *blob, bd_t *bd); - -#endif diff --git a/board/freescale/t4qds/tlb.c b/board/freescale/t4qds/tlb.c deleted file mode 100644 index cd5cf48def..0000000000 --- a/board/freescale/t4qds/tlb.c +++ /dev/null @@ -1,146 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, - CONFIG_SYS_INIT_RAM_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) - /* - * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the - * SRAM is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) - /* - * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the - * space is at 0xfff00000, it covered the 0xfffff000. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 0, BOOKE_PAGESZ_1M, 1), -#else - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_4K, 1), -#endif - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_16M, 1), - - /* *I*G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), -#ifndef CONFIG_SPL_BUILD - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ -#ifdef CONFIG_SYS_BMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_16M, 1), -#endif -#ifdef CONFIG_SYS_QMAN_MEM_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 11, BOOKE_PAGESZ_16M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 12, BOOKE_PAGESZ_16M, 1), -#endif -#endif -#ifdef CONFIG_SYS_DCSRBAR_PHYS - SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 13, BOOKE_PAGESZ_32M, 1), -#endif -#ifdef CONFIG_SYS_NAND_BASE - /* - * *I*G - NAND - * entry 14 and 15 has been used hard coded, they will be disabled - * in cpu_init_f, so we use entry 16 for nand. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 16, BOOKE_PAGESZ_64K, 1), -#endif -#ifdef QIXIS_BASE_PHYS - SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 17, BOOKE_PAGESZ_4K, 1), -#endif -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE - /* - * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for - * fetching ucode and ENV from master - */ - SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, - CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, - 0, 18, BOOKE_PAGESZ_1M, 1), -#endif - -#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 19, BOOKE_PAGESZ_2G, 1) -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig deleted file mode 100644 index 0b33818008..0000000000 --- a/board/pandora/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -if TARGET_OMAP3_PANDORA - -config SYS_BOARD - default "pandora" - -config SYS_CONFIG_NAME - default "omap3_pandora" - -endif diff --git a/board/pandora/MAINTAINERS b/board/pandora/MAINTAINERS deleted file mode 100644 index e12351735c..0000000000 --- a/board/pandora/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -PANDORA BOARD -M: Grazvydas Ignotas -S: Maintained -F: board/pandora/ -F: include/configs/omap3_pandora.h -F: configs/omap3_pandora_defconfig diff --git a/board/pandora/Makefile b/board/pandora/Makefile deleted file mode 100644 index c05c8fb854..0000000000 --- a/board/pandora/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y := pandora.o diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c deleted file mode 100644 index a93848666f..0000000000 --- a/board/pandora/pandora.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2008 - * Grazvydas Ignotas - * - * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by - * Richard Woodruff - * Syed Mohammed Khasim - * Sunil Kumar - * Shashi Ranjan - * - * (C) Copyright 2004-2008 - * Texas Instruments, - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pandora.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define TWL4030_BB_CFG_BBCHEN (1 << 4) -#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2) -#define TWL4030_BB_CFG_BBISEL_500UA 2 - -#define CONTROL_WKUP_CTRL 0x48002a5c -#define GPIO_IO_PWRDNZ (1 << 6) -#define PBIASLITEVMODE1 (1 << 8) - -static const struct ns16550_platdata pandora_serial = { - .base = OMAP34XX_UART3, - .reg_shift = 2, - .clock = V_NS16550_CLK, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(pandora_uart) = { - "ns16550_serial", - &pandora_serial -}; - -/* - * Routine: board_init - * Description: Early hardware init. - */ -int board_init(void) -{ - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA; - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - - return 0; -} - -static void set_output_gpio(unsigned int gpio, int value) -{ - int ret; - - ret = gpio_request(gpio, ""); - if (ret != 0) { - printf("could not request GPIO %u\n", gpio); - return; - } - ret = gpio_direction_output(gpio, value); - if (ret != 0) - printf("could not set GPIO %u to %d\n", gpio, value); -} - -/* - * Routine: misc_init_r - * Description: Configure board specific parts - */ -int misc_init_r(void) -{ - t2_t *t2_base = (t2_t *)T2_BASE; - u32 pbias_lite; - - twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); - - /* set up dual-voltage GPIOs to 1.8V */ - pbias_lite = readl(&t2_base->pbias_lite); - pbias_lite &= ~PBIASLITEVMODE1; - pbias_lite |= PBIASLITEPWRDNZ1; - writel(pbias_lite, &t2_base->pbias_lite); - if (get_cpu_family() == CPU_OMAP36XX) - writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ, - CONTROL_WKUP_CTRL); - - /* make sure audio and BT chips are in powerdown state */ - set_output_gpio(14, 0); - set_output_gpio(15, 0); - set_output_gpio(118, 0); - - /* enable USB supply */ - set_output_gpio(164, 1); - - /* wifi needs a short pulse to enter powersave state */ - set_output_gpio(23, 1); - udelay(5000); - gpio_direction_output(23, 0); - - /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */ - twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, - TWL4030_PM_RECEIVER_BB_CFG, - TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV | - TWL4030_BB_CFG_BBISEL_500UA); - - omap_die_id_display(); - - return 0; -} - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_PANDORA(); - if (get_cpu_family() == CPU_OMAP36XX) { - MUX_PANDORA_3730(); - } -} - -#ifdef CONFIG_MMC -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} - -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h deleted file mode 100644 index 9c4c5d1cd7..0000000000 --- a/board/pandora/pandora.h +++ /dev/null @@ -1,391 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Grazvydas Ignotas - */ -#ifndef _PANDORA_H_ -#define _PANDORA_H_ - -const omap3_sysinfo sysinfo = { - DDR_STACKED, - "OMAP3 Pandora", - "NAND", -}; - -/* - * IEN - Input Enable - * IDIS - Input Disable - * PTD - Pull type Down - * PTU - Pull type Up - * DIS - Pull type selection is inactive - * EN - Pull type selection is active - * M0 - Mode 0 - * The commented string gives the final mux configuration for that pin - */ -#define MUX_PANDORA() \ - /*SDRC*/\ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ - /*GPMC*/\ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ - /*DSS*/\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\ - /*GPIO based game buttons*/\ - MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\ - MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\ - MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*GPIO_106 - B*/\ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*GPIO_107 - R2*/\ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M4)) /*GPIO_109 - X*/\ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M4)) /*GPIO_110 - UP*/\ - MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | DIS | M4)) /*GPIO_111 - A*/\ - /*Audio Interface To External DAC (Headphone, Speakers)*/\ - MUX_VAL(CP(MCBSP2_FSX), (IDIS | PTD | DIS | M0)) /*McBSP2_FSX*/\ - MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M0)) /*McBSP2_CLKX*/\ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0)) /*McBSP_CLKS*/\ - MUX_VAL(CP(MCBSP2_DR), (IDIS | PTD | DIS | M4)) /*GPIO_118*/\ - /* - nPOWERDOWN_DAC*/\ - /*Expansion card 1*/\ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\ - /*Expansion card 2*/\ - MUX_VAL(CP(MMC2_CLK), (IDIS | PTD | DIS | M0)) /*MMC2_CLK*/\ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT0*/\ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_DAT1*/\ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)) /*MMC2_DIR_CMD */\ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\ - /*SDIO Interface to WIFI Module*/\ - MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTD | DIS | M2)) /*MMC3_CLK*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\ - /*Audio Interface To Bluetooth chip*/\ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) /*McBSP3_DR*/\ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) /*McBSP3_CLKX*/\ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) /*McBSP3_FSX*/\ - /*Digital Interface to Bluetooth (UART)*/\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M0)) /*UART1_CTS*/\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ - /*Audio Interface to Triton2 chip (TPS65950)*/\ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\ - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M0)) /*McBSP4_DX*/\ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\ - /*GPIO definitions for muxed pins on AV connector*/\ - MUX_VAL(CP(UART2_CTS), (IEN | PTD | EN | M4)) /*GPIO_144,*/\ - /*UART2_CTS*/\ - MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)) /*GPIO_145,*/\ - /*UART2_RTS*/\ - MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)) /*GPIO_146,*/\ - /*UART2_TX*/\ - MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)) /*GPIO_147,*/\ - /*UART2_RX*/\ - /*Serial Interface (Peripheral boot, Linux console, on AV connector)*/\ - /*RX pulled up to avoid noise when nothing is connected to serial port*/\ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX*/\ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX*/\ - /*LEDs (Controlled by OMAP)*/\ - MUX_VAL(CP(MMC1_DAT6), (IDIS | PTD | DIS | M4)) /*GPIO_128*/\ - /* - LED_MMC1*/\ - MUX_VAL(CP(MMC1_DAT7), (IDIS | PTD | DIS | M4)) /*GPIO_129*/\ - /* - LED_MMC2*/\ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\ - /* - LED_BT*/\ - MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\ - /* - LED_WIFI*/\ - /*Switches*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\ - /* - nHOLD_SWITCH*/\ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*GPIO_108*/\ - /* - nLID_SWITCH*/\ - /*External IRQs*/\ - MUX_VAL(CP(CAM_HS), (IEN | PTD | DIS | M4)) /*GPIO_94*/\ - /* - nTOUCH_IRQ*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M4)) /*GPIO_21*/\ - /* - WIFI_IRQ*/\ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M4)) /*GPIO_161*/\ - /* - nIRQ_NUB1*/\ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M4)) /*GPIO_162*/\ - /* - nIRQ_NUB2*/\ - /*Various other stuff*/\ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | DIS | M4)) /*GPIO_163*/\ - /* - nOC_USB5*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M4)) /*GPIO_22*/\ - /* - MSECURE*/\ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M4)) /*GPIO_115*/\ - /* - POP_OVERHEAT*/\ - /*External Resets and Enables*/\ - MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_14*/\ - /* - nHDPHN_SHUTDOWN*/\ - MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_15*/\ - /* - nBT_SHUTDOWN*/\ - MUX_VAL(CP(ETK_D9_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_23*/\ - /* - nWIFI_RESET*/\ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157*/\ - /* - nLCD_RESET*/\ - MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\ - /* - RESET_NUBS*/\ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M4)) /*GPIO_164*/\ - /* - EN_USB_5V*/\ - /*Spare GPIOs*/\ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTD | EN | M4)) /*GPIO_58*/\ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTD | EN | M4)) /*GPIO_64*/\ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTD | EN | M4)) /*GPIO_65*/\ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*GPIO_95*/\ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) /*GPIO_167*/\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) /*GPIO_170*/\ - /*HS USB OTG Port (connects to HSUSB0)*/\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ - /*I2C Ports*/\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL - T2_CTRL*/\ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA - T2_CTRL*/\ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL - NUBS*/\ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA - NUBS*/\ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL - T2_SR*/\ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA - T2_SR*/\ - /*Serial Interface (Touch, LCD control)*/\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO*/\ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI*/\ - MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTU | EN | M0)) /*McSPI1_CS0 - TOUCH*/\ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTU | EN | M0)) /*McSPI1_CS1 - LCD*/\ - /*HS USB HOST Port (connects to HSUSB2)*/\ - MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\ - MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*USB_HOST_D6*/\ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*USB_HOST_D7*/\ - MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTD | DIS | M4)) /*GPIO_16*/\ - /* - nRESET_USB_HOST*/\ - /*Control and debug */\ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3*/\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ - /*JTAG*/\ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\ - /*Die to Die stuff*/\ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm*/\ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq*/\ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ - -#define MUX_PANDORA_3730() \ - MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\ - MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\ - MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\ - MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/ - -#endif diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig deleted file mode 100644 index 2cc0d8872d..0000000000 --- a/board/phytec/pcm051/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_PCM051 - -config SYS_BOARD - default "pcm051" - -config SYS_VENDOR - default "phytec" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "pcm051" - -endif diff --git a/board/phytec/pcm051/MAINTAINERS b/board/phytec/pcm051/MAINTAINERS deleted file mode 100644 index 18ea636a83..0000000000 --- a/board/phytec/pcm051/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -PCM051 BOARD -M: Lars Poeschel -S: Maintained -F: board/phytec/pcm051/ -F: include/configs/pcm051.h -F: configs/pcm051_rev1_defconfig -F: configs/pcm051_rev3_defconfig diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile deleted file mode 100644 index ff6f8b4221..0000000000 --- a/board/phytec/pcm051/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Makefile -# -# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - -ifdef CONFIG_SPL_BUILD -obj-y += mux.o -endif - -obj-y += board.o diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c deleted file mode 100644 index 6f1ada82c4..0000000000 --- a/board/phytec/pcm051/board.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board.c - * - * Board functions for Phytec phyCORE-AM335x (pcm051) based boards - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* MII mode defines */ -#define RMII_RGMII2_MODE_ENABLE 0x49 - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifdef CONFIG_SPL_BUILD - -/* DDR RAM defines */ -#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */ - -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr = { - DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1}; - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -#ifdef CONFIG_REV1 -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .cm1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .cm2ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .dt0ioctl = MT41J256M8HX15E_IOCTRL_VALUE, - .dt1ioctl = MT41J256M8HX15E_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41J256M8HX15E_RD_DQS, - .datawdsratio0 = MT41J256M8HX15E_WR_DQS, - .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, - .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41J256M8HX15E_RATIO, - .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, - - .cmd1csratio = MT41J256M8HX15E_RATIO, - .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, - - .cmd2csratio = MT41J256M8HX15E_RATIO, - .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41J256M8HX15E_EMIF_SDCFG, - .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF, - .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1, - .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, - .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, - .zq_config = MT41J256M8HX15E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#else -const struct ctrl_ioregs ioregs = { - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, -}; - -static const struct ddr_data ddr3_data = { - .datardsratio0 = MT41K256M16HA125E_RD_DQS, - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, -}; - -static const struct cmd_control ddr3_cmd_ctrl_data = { - .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, - - .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, -}; - -static struct emif_regs ddr3_emif_reg_data = { - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, - .zq_config = MT41K256M16HA125E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | - PHY_EN_DYN_PWRDN, -}; - -void sdram_init(void) -{ - config_ddr(DDR_CLK_MHZ, &ioregs, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); -} -#endif - -void set_uart_mux_conf(void) -{ - enable_uart0_pin_mux(); -} - -void set_mux_conf_regs(void) -{ - /* Initalize the board header */ - enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - enable_board_pin_mux(); -} -#endif - -/* - * Basic board specific setup. Pinmux has been handled already. - */ -int board_init(void) -{ - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ - - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; -#endif - -#if defined(CONFIG_DRIVER_TI_CPSW) || \ - (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) -int board_eth_init(bd_t *bis) -{ - int rv, n = 0; -#ifdef CONFIG_DRIVER_TI_CPSW - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - printf(" not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - else - goto try_usbether; - } - - writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - else - n += rv; -try_usbether: -#endif - -#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) - rv = usb_eth_initialize(bis); - if (rv < 0) - printf("Error %d registering USB_ETHER\n", rv); - else - n += rv; -#endif - return n; -} -#endif diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h deleted file mode 100644 index 3366e51c85..0000000000 --- a/board/phytec/pcm051/board.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * board.h - * - * Phytec phyCORE-AM335x (pcm051) boards information header - * - * Copyright (C) 2013, Lemonage Software GmbH - * Author Lars Poeschel - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/* - * We have three pin mux functions that must exist. We must be able to enable - * uart0, for initial output and i2c0 to read the main EEPROM. We then have a - * main pinmux function that can be overridden to enable all other pinmux that - * is required on the board. - */ -void enable_uart0_pin_mux(void); -void enable_i2c0_pin_mux(void); -void enable_board_pin_mux(void); -void enable_cbmux_pin_mux(void); -#endif diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c deleted file mode 100644 index 9bca8eae9f..0000000000 --- a/board/phytec/pcm051/mux.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * mux.c - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "board.h" - -static struct module_pin_mux uart0_pin_mux[] = { - {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ - {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ - {-1}, -}; - -#ifdef CONFIG_MMC -static struct module_pin_mux mmc0_pin_mux[] = { - {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ - {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ - {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ - {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ - {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ - {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ - {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ - {-1}, -}; -#endif - -#ifdef CONFIG_I2C -static struct module_pin_mux i2c0_pin_mux[] = { - {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ - {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | - PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ - {-1}, -}; -#endif - -#ifdef CONFIG_SPI -static struct module_pin_mux spi0_pin_mux[] = { - {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ - {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | - PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ - {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ - {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | - PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ - {-1}, -}; -#endif - -static struct module_pin_mux rmii1_pin_mux[] = { - {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ - {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ - {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ - {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ - {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ - {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ - {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ - {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ - {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ - {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ - {-1}, -}; - -static struct module_pin_mux cbmux_pin_mux[] = { - {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */ - {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */ - {-1}, -}; - -#ifdef CONFIG_MTD_RAW_NAND -static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ - {-1}, -}; -#endif - -void enable_uart0_pin_mux(void) -{ - configure_module_pin_mux(uart0_pin_mux); -} - -void enable_i2c0_pin_mux(void) -{ - configure_module_pin_mux(i2c0_pin_mux); -} - -void enable_board_pin_mux() -{ - configure_module_pin_mux(rmii1_pin_mux); - configure_module_pin_mux(mmc0_pin_mux); - configure_module_pin_mux(cbmux_pin_mux); -#ifdef CONFIG_MTD_RAW_NAND - configure_module_pin_mux(nand_pin_mux); -#endif -#ifdef CONFIG_SPI - configure_module_pin_mux(spi0_pin_mux); -#endif -} diff --git a/cmd/mmc.c b/cmd/mmc.c index 97e5d91859..1c252e0502 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -1004,7 +1004,7 @@ U_BOOT_CMD( "mmc part - lists available partition on current mmc device\n" "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" - "mmc wp - power on write protect booot partitions\n" + "mmc wp - power on write protect boot partitions\n" #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) "mmc hwpartition [args...] - does hardware partitioning\n" " arguments (sizes in 512-byte blocks):\n" diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig deleted file mode 100644 index 6fcb51a1cd..0000000000 --- a/configs/B4420QDS_NAND_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4420QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig deleted file mode 100644 index 5dc72cb3f2..0000000000 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4420QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig deleted file mode 100644 index 5f9a88adfa..0000000000 --- a/configs/B4420QDS_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4420QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig deleted file mode 100644 index 0874acd83e..0000000000 --- a/configs/B4860QDS_NAND_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig deleted file mode 100644 index 4d7bf5dc39..0000000000 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig deleted file mode 100644 index 566076543f..0000000000 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index 58195adcbc..0000000000 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig deleted file mode 100644 index 68ff6ed953..0000000000 --- a/configs/B4860QDS_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_B4860QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig deleted file mode 100644 index 64f6dadc22..0000000000 --- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFFE000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9131RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig deleted file mode 100644 index eda1ac428c..0000000000 --- a/configs/BSC9131RDB_NAND_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFFE000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9131RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig deleted file mode 100644 index 8ac33150f8..0000000000 --- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9131RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig deleted file mode 100644 index 10d866661b..0000000000 --- a/configs/BSC9131RDB_SPIFLASH_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9131RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_HUSH_PARSER=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -# CONFIG_PCI is not set -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig deleted file mode 100644 index 83300b204a..0000000000 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig deleted file mode 100644 index 5f85370a0a..0000000000 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFFE000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig deleted file mode 100644 index 646158bb77..0000000000 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT,SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig deleted file mode 100644 index 82f37fbf1c..0000000000 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFFE000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig deleted file mode 100644 index 25ed8dc6a7..0000000000 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig deleted file mode 100644 index e0e441de44..0000000000 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x8FF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig deleted file mode 100644 index f7181d69d2..0000000000 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig deleted file mode 100644 index 0ea77dc3a9..0000000000 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x8FF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0x8FF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig deleted file mode 100644 index 30bdc5d3d2..0000000000 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig deleted file mode 100644 index 0e93c0d1c2..0000000000 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig deleted file mode 100644 index ca119d0625..0000000000 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig deleted file mode 100644 index 288d4cf883..0000000000 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD,SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig deleted file mode 100644 index e30dd9be90..0000000000 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig deleted file mode 100644 index 8f4d4b8fbb..0000000000 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_100" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig deleted file mode 100644 index 80c51aa705..0000000000 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig deleted file mode 100644 index fb16caad9a..0000000000 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_BSC9132QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100_DDR_133" -CONFIG_BOOTDELAY=10 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=88000000.nor,nand0=ff800000.flash," -CONFIG_MTDPARTS_DEFAULT="mtdparts=88000000.nor:256k(dtb),7m(kernel),55m(fs),1m(uboot);ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig deleted file mode 100644 index cdcf50eee8..0000000000 --- a/configs/C29XPCIE_NAND_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x100000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_C29XPCIE=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=-1 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig deleted file mode 100644 index e43c72860a..0000000000 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_C29XPCIE=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=-1 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_DOS_PARTITION=y -CONFIG_DM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig deleted file mode 100644 index b7eb77e2a0..0000000000 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_C29XPCIE=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=-1 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_DOS_PARTITION=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig deleted file mode 100644 index 9bfdcd0461..0000000000 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11000000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_C29XPCIE=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=-1 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig deleted file mode 100644 index 3e7f19692a..0000000000 --- a/configs/C29XPCIE_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_C29XPCIE=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=-1 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SF=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig deleted file mode 100644 index e60890e2d0..0000000000 --- a/configs/MPC8536DS_36BIT_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8536DS=y -CONFIG_PHYS_64BIT=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_SYS_FSL_DDR2=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig deleted file mode 100644 index 9f653661f4..0000000000 --- a/configs/MPC8536DS_SDCARD_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf8f40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8536DS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_FSL_DDR2=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig deleted file mode 100644 index 866d719564..0000000000 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xf8f40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xF0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8536DS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_FSL_DDR2=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig deleted file mode 100644 index 9366e7a757..0000000000 --- a/configs/MPC8536DS_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_MPC8536DS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_CONSOLE_MUX is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_SYS_FSL_DDR2=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig deleted file mode 100644 index 2bfda3ed40..0000000000 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig deleted file mode 100644 index 9cc214088c..0000000000 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig deleted file mode 100644 index 80d3a88273..0000000000 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ /dev/null @@ -1,76 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig deleted file mode 100644 index 1048b53abb..0000000000 --- a/configs/P1022DS_36BIT_defconfig +++ /dev/null @@ -1,62 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig deleted file mode 100644 index 79754874b6..0000000000 --- a/configs/P1022DS_NAND_defconfig +++ /dev/null @@ -1,79 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig deleted file mode 100644 index 4e80b8844e..0000000000 --- a/configs/P1022DS_SDCARD_defconfig +++ /dev/null @@ -1,73 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig deleted file mode 100644 index e55f05cf56..0000000000 --- a/configs/P1022DS_SPIFLASH_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig deleted file mode 100644 index c611ce418d..0000000000 --- a/configs/P1022DS_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P1022DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=e8000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=e8000000.nor:48m(ramdisk),14m(diagnostic),2m(dink),6m(kernel),58112k(fs),512k(dtb),768k(u-boot)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig deleted file mode 100644 index 2199abcb95..0000000000 --- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig deleted file mode 100644 index 0a52af48bb..0000000000 --- a/configs/T1024QDS_DDR4_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig deleted file mode 100644 index 9db39b1b58..0000000000 --- a/configs/T1024QDS_NAND_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig deleted file mode 100644 index 679f2ad208..0000000000 --- a/configs/T1024QDS_SDCARD_defconfig +++ /dev/null @@ -1,80 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig deleted file mode 100644 index cc080c7285..0000000000 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig deleted file mode 100644 index 01bc5111e0..0000000000 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0xFFFC9000 -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig deleted file mode 100644 index 6ebffb8dd1..0000000000 --- a/configs/T1024QDS_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1024QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig deleted file mode 100644 index a575b6fbc6..0000000000 --- a/configs/T1040QDS_DDR4_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1040QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_ETHSW=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig deleted file mode 100644 index e616f0d232..0000000000 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,70 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T1040QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_ETHSW=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_DM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig deleted file mode 100644 index 0b1c7cd12d..0000000000 --- a/configs/T1040QDS_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T1040QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_SILENT_CONSOLE=y -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_ETHSW=y -CONFIG_CMD_BMP=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_SYS_FSL_DDR3=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig deleted file mode 100644 index ddff89602f..0000000000 --- a/configs/T4160QDS_NAND_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4160QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig deleted file mode 100644 index 5d253534ca..0000000000 --- a/configs/T4160QDS_SDCARD_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4160QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig deleted file mode 100644 index 8934c3edf0..0000000000 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T4160QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig deleted file mode 100644 index d0d1290631..0000000000 --- a/configs/T4160QDS_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4160QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig deleted file mode 100644 index f971cee3b0..0000000000 --- a/configs/T4240QDS_NAND_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x140000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig deleted file mode 100644 index 5e662be1d7..0000000000 --- a/configs/T4240QDS_SDCARD_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x00201000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_TEXT_BASE=0xFFFD8000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_FSL_PBL=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig deleted file mode 100644 index 807d5b5895..0000000000 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index 2bc30bbf9e..0000000000 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,49 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig deleted file mode 100644 index 84341f7579..0000000000 --- a/configs/T4240QDS_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_T4240QDS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SST=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig deleted file mode 100644 index e48454aa6c..0000000000 --- a/configs/TWR-P1025_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1_TWR=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ec000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ec000000.nor:256k(vsc7385-firmware),256k(dtb),5632k(kernel),57856k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_SATA_SIL3114=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_PANIC_HANG=y -CONFIG_OF_LIBFDT=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 2781d49daf..c92e0cc330 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -60,6 +60,7 @@ CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 238164a55f..0aeaad577e 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -52,6 +52,7 @@ CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_FAT_WRITE=y CONFIG_LZO=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index a5c301dbdb..d32c017907 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -62,6 +62,7 @@ CONFIG_SMC911X_BASE=0x2C000000 CONFIG_SMC911X_32_BIT=y CONFIG_CONS_INDEX=3 CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_OMAP3_SPI=y CONFIG_BCH=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index 644b6e5464..9f91fb9598 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2e-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 0379021c14..e2a451957b 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -34,6 +34,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2g-evm" CONFIG_OF_LIST="keystone-k2g-generic keystone-k2g-evm keystone-k2g-ice" CONFIG_DTB_RESELECT=y @@ -41,6 +42,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_MISC=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index eb5916c2c6..1cd7331653 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2hk-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 71a35e3496..ae4b26b7a9 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -36,11 +36,13 @@ CONFIG_MTDIDS_DEFAULT="nand0=davinci_nand.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=davinci_nand.0:1024k(bootloader)ro,512k(params)ro,-(ubifs)" CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="keystone-k2l-evm" CONFIG_ENV_IS_IN_NAND=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SPL_DM=y CONFIG_SYS_I2C_DAVINCI=y CONFIG_TI_AEMIF=y CONFIG_MISC=y diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig deleted file mode 100644 index d8ee7995de..0000000000 --- a/configs/omap3_pandora_defconfig +++ /dev/null @@ -1,40 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_TEXT_BASE=0x80008000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_TARGET_OMAP3_PANDORA=y -CONFIG_NR_DRAM_BANKS=2 -CONFIG_DISTRO_DEFAULTS=y -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SYS_PROMPT="Pandora # " -# CONFIG_CMD_IMI is not set -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_NET is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1920k(uboot),128k(uboot-env),10m(boot),-(rootfs)" -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_DM=y -CONFIG_TWL4030_LED=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig deleted file mode 100644 index ea7a0769f2..0000000000 --- a/configs/pcm051_rev1_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PCM051=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="REV1" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_ETH_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig deleted file mode 100644 index 43e64630ab..0000000000 --- a/configs/pcm051_rev3_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_AM33XX=y -CONFIG_TARGET_PCM051=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="REV3" -# CONFIG_USE_BOOTCOMMAND is not set -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -CONFIG_ARCH_MISC_INIT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_ETH_SUPPORT=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -# CONFIG_SPL_NAND_SUPPORT is not set -CONFIG_SPL_NET_SUPPORT=y -CONFIG_SPL_NET_VCI_STRING="pcm051 U-Boot SPL" -CONFIG_SPL_OS_BOOT=y -CONFIG_SPL_POWER_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_SPL_YMODEM_SUPPORT=y -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -CONFIG_CMD_EEPROM=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_SPI=y -CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_EXT4_WRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_MMC_OMAP_HS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=24000000 -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_PHY_SMSC=y -CONFIG_MII=y -CONFIG_DRIVER_TI_CPSW=y -CONFIG_SPI=y -CONFIG_OMAP3_SPI=y -CONFIG_USB=y -CONFIG_USB_MUSB_HOST=y -CONFIG_USB_MUSB_GADGET=y -CONFIG_USB_MUSB_DSPS=y -CONFIG_USB_GADGET=y -CONFIG_USB_ETHER=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y diff --git a/doc/README.omap3 b/doc/README.omap3 index 00bcbdba9a..8c3667b10c 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -41,11 +41,6 @@ make make omap3_evm_config make -* Pandora: - -make omap3_pandora_config -make - * Zoom MDK: make omap3_zoom1_config diff --git a/doc/api/index.rst b/doc/api/index.rst index fd3b5bdc82..b7eb5725f2 100644 --- a/doc/api/index.rst +++ b/doc/api/index.rst @@ -9,5 +9,6 @@ U-Boot API documentation dfu efi linker_lists + rng serial unicode diff --git a/doc/api/rng.rst b/doc/api/rng.rst new file mode 100644 index 0000000000..b826d4fd4a --- /dev/null +++ b/doc/api/rng.rst @@ -0,0 +1,17 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (c) 2018 Heinrich Schuchardt + +Random number generation +======================== + +Hardware random number generation +--------------------------------- + +.. kernel-doc:: include/rng.h + :internal: + +Pseudo random number generation +------------------------------- + +.. kernel-doc:: include/rand.h + :internal: diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 3c4f057373..8f56572c39 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -727,6 +727,21 @@ config FSL_ESDHC This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs. +config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND + bool "enable eSDHC workaround for 3.3v IO reliability issue" + depends on FSL_ESDHC && DM_MMC + default n + help + When eSDHC operates at 3.3v, damage can accumulate in an internal + level shifter at a higher than expected rate. The faster the interface + runs, the more damage accumulates. This issue now is found on LX2160A + eSDHC1 for only SD card. The hardware workaround is recommended to use + an on-board level shifter that is 1.8v on SoC side and 3.3v on SD card + side. For boards without hardware workaround, this option could be + enabled, ensuring 1.8v IO voltage and disabling eSDHC if no card. + This option assumes no hotplug, and u-boot has to make all the way to + to linux to use 1.8v UHS-I speed mode if has card. + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index acbc850fcb..198c41f451 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -19,6 +19,7 @@ #define SD_CLK_SEL_200MHZ (0x2) #define SD_CLK_SEL_100MHZ (0x1) +#define SD_CLK_SEL_50MHZ (0x0) #define IO_DRV_SD_DS_OFFSET (16) #define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET) @@ -44,15 +45,11 @@ static void ca_dwmci_clksel(struct dwmci_host *host) struct ca_dwmmc_priv_data *priv = host->priv; u32 val = readl(priv->sd_dll_reg); - if (host->bus_hz >= 200000000) { - val &= ~SD_CLK_SEL_MASK; + val &= ~SD_CLK_SEL_MASK; + if (host->bus_hz >= 200000000) val |= SD_CLK_SEL_200MHZ; - } else if (host->bus_hz >= 100000000) { - val &= ~SD_CLK_SEL_MASK; + else if (host->bus_hz >= 100000000) val |= SD_CLK_SEL_100MHZ; - } else { - val &= ~SD_CLK_SEL_MASK; - } writel(val, priv->sd_dll_reg); } @@ -77,14 +74,14 @@ unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq) u8 clk_div; switch (sd_clk_sel) { - case 2: - clk_div = 1; + case SD_CLK_SEL_50MHZ: + clk_div = 4; break; - case 1: + case SD_CLK_SEL_100MHZ: clk_div = 2; break; default: - clk_div = 4; + clk_div = 1; } return SD_SCLK_MAX / clk_div / (host->div + 1); @@ -100,9 +97,6 @@ static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev) host->dev_index = 0; host->buswidth = dev_read_u32_default(dev, "bus-width", 1); - if (host->buswidth != 1 && host->buswidth != 4) - return -EINVAL; - host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000); priv->ds = dev_read_u32_default(dev, "io_ds", 0x33); host->fifo_mode = dev_read_bool(dev, "fifo-mode"); @@ -118,10 +112,8 @@ static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev) return -EINVAL; host->ioaddr = dev_read_addr_ptr(dev); - if (host->ioaddr == (void *)FDT_ADDR_T_NONE) { - printf("DWMMC: base address is invalid\n"); + if (!host->ioaddr) return -EINVAL; - } host->priv = priv; @@ -140,10 +132,8 @@ static int ca_dwmmc_probe(struct udevice *dev) memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops)); dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ); - if (host->buswidth == 1) { - (&plat->cfg)->host_caps &= ~MMC_MODE_8BIT; - (&plat->cfg)->host_caps &= ~MMC_MODE_4BIT; - } + if (host->buswidth == 1) + (&plat->cfg)->host_caps &= ~(MMC_MODE_8BIT | MMC_MODE_4BIT); host->mmc = &plat->mmc; host->mmc->priv = &priv->host; @@ -164,7 +154,7 @@ static int ca_dwmmc_bind(struct udevice *dev) } static const struct udevice_id ca_dwmmc_ids[] = { - { .compatible = "snps,dw-cortina" }, + { .compatible = "cortina,ca-mmc" }, { } }; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d5d955846c..a4b923ab99 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc - * Copyright 2019 NXP Semiconductors + * Copyright 2019-2020 NXP * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -630,16 +630,15 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) { struct fsl_esdhc *regs = priv->esdhc_regs; - int timeout = 1000; #ifdef CONFIG_ESDHC_DETECT_QUIRK if (CONFIG_ESDHC_DETECT_QUIRK) return 1; #endif - while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout) - udelay(1000); + if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS) + return 1; - return timeout > 0; + return 0; } static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, @@ -724,13 +723,38 @@ __weak int esdhc_status_fixup(void *blob, const char *compat) return 0; } +#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND +static int fsl_esdhc_get_cd(struct udevice *dev); + +static void esdhc_disable_for_no_card(void *blob) +{ + struct udevice *dev; + + for (uclass_first_device(UCLASS_MMC, &dev); + dev; + uclass_next_device(&dev)) { + char esdhc_path[50]; + + if (fsl_esdhc_get_cd(dev)) + continue; + + snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx", + (unsigned long)dev_read_addr(dev)); + do_fixup_by_path(blob, esdhc_path, "status", "disabled", + sizeof("disabled"), 1); + } +} +#endif + void fdt_fixup_esdhc(void *blob, bd_t *bd) { const char *compat = "fsl,esdhc"; if (esdhc_status_fixup(blob, compat)) return; - +#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND + esdhc_disable_for_no_card(blob); +#endif do_fixup_by_compat_u32(blob, compat, "clock-frequency", gd->arch.sdhc_clk, 1); } @@ -849,6 +873,7 @@ static int fsl_esdhc_probe(struct udevice *dev) struct fsl_esdhc_priv *priv = dev_get_priv(dev); fdt_addr_t addr; struct mmc *mmc; + int ret; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) @@ -882,7 +907,15 @@ static int fsl_esdhc_probe(struct udevice *dev) upriv->mmc = mmc; - return esdhc_init_common(priv, mmc); + ret = esdhc_init_common(priv, mmc); + if (ret) + return ret; + +#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND + if (!fsl_esdhc_get_cd(dev)) + esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL); +#endif + return 0; } static int fsl_esdhc_get_cd(struct udevice *dev) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 588d6a9d76..f42e018434 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -791,7 +791,7 @@ static int esdhc_set_voltage(struct mmc *mmc) switch (mmc->signal_voltage) { case MMC_SIGNAL_VOLTAGE_330: if (priv->vs18_enable) - return -EIO; + return -ENOTSUPP; #if CONFIG_IS_ENABLED(DM_REGULATOR) if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) { ret = regulator_set_value(priv->vqmmc_dev, 3300000); @@ -972,7 +972,8 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) if (priv->signal_voltage != mmc->signal_voltage) { ret = esdhc_set_voltage(mmc); if (ret) { - printf("esdhc_set_voltage error %d\n", ret); + if (ret != -ENOTSUPP) + printf("esdhc_set_voltage error %d\n", ret); return ret; } } @@ -1455,6 +1456,7 @@ static int fsl_esdhc_probe(struct udevice *dev) if (ret) { dev_dbg(dev, "no vqmmc-supply\n"); } else { + priv->vqmmc_dev = vqmmc_dev; ret = regulator_set_enable(vqmmc_dev, true); if (ret) { dev_err(dev, "fail to enable vqmmc-supply\n"); diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 7dcb317192..da679a572c 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -466,9 +466,6 @@ static int regulator_pre_probe(struct udevice *dev) (uc_pdata->min_uA == uc_pdata->max_uA)) uc_pdata->flags |= REGULATOR_FLAG_AUTOSET_UA; - if (uc_pdata->boot_on) - regulator_set_enable(dev, uc_pdata->boot_on); - return 0; } diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 16d9412cd5..4cfcc31298 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -19,6 +19,8 @@ int regulator_common_ofdata_to_platdata(struct udevice *dev, if (!dev_read_bool(dev, "enable-active-high")) flags |= GPIOD_ACTIVE_LOW; + if (dev_read_bool(dev, "regulator-boot-on")) + flags |= GPIOD_IS_OUT_ACTIVE; /* Get optional enable GPIO desc */ gpio = &dev_pdata->gpio; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 59415209ee..09b9cb17d8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -119,6 +119,12 @@ config CF_SPI Enable the ColdFire SPI driver. This driver can be used on some m68k SoCs. +config DAVINCI_SPI + bool "Davinci & Keystone SPI driver" + depends on ARCH_DAVINCI || ARCH_KEYSTONE + help + Enable the Davinci SPI driver + config DESIGNWARE_SPI bool "Designware SPI driver" help @@ -207,6 +213,12 @@ config MVEBU_A3700_SPI used to access the SPI NOR flash on platforms embedding this Marvell IP core. +config MXS_SPI + bool "MXS SPI Driver" + help + Enable the MXS SPI controller driver. This driver can be used + on the i.MX23 and i.MX28 SoCs. + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM @@ -280,6 +292,12 @@ config SPI_SIFIVE The SiFive SPI controller driver is found on various SiFive SoCs. +config SOFT_SPI + bool "Soft SPI driver" + help + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. + config SPI_SUNXI bool "Allwinner SoC SPI controllers" default ARCH_SUNXI @@ -385,13 +403,6 @@ config ZYNQMP_GQSPI endif # if DM_SPI -config SOFT_SPI - bool "Soft SPI driver" - depends on DM_SPI || (DEPRECATED && !DM_SPI) - help - Enable Soft SPI driver. This driver is to use GPIO simulate - the SPI protocol. - config FSL_ESPI bool "Freescale eSPI driver" imply SPI_FLASH_BAR @@ -400,12 +411,6 @@ config FSL_ESPI access the SPI interface and SPI NOR flash on platforms embedding this Freescale eSPI IP core. -config DAVINCI_SPI - bool "Davinci & Keystone SPI driver" - depends on ARCH_DAVINCI || ARCH_KEYSTONE - help - Enable the Davinci SPI driver - config SH_QSPI bool "Renesas Quad SPI driver" help @@ -424,12 +429,6 @@ config MXC_SPI Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. -config MXS_SPI - bool "MXS SPI Driver" - help - Enable the MXS SPI controller driver. This driver can be used - on the i.MX23 and i.MX28 SoCs. - config OMAP3_SPI bool "McSPI driver for OMAP" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 342776404a..54881a7412 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_TI_QSPI) += ti_qspi.o else obj-y += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o -obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index f076e92a93..b120664661 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -9,217 +9,102 @@ #include #include #include - #include - #include #include -#ifdef CONFIG_DM_SPI #include -#endif #if CONFIG_IS_ENABLED(DM_GPIO) #include #endif +#include -#include "atmel_spi.h" +/* + * Register definitions for the Atmel AT32/AT91 SPI Controller + */ +/* Register offsets */ +#define ATMEL_SPI_CR 0x0000 +#define ATMEL_SPI_MR 0x0004 +#define ATMEL_SPI_RDR 0x0008 +#define ATMEL_SPI_TDR 0x000c +#define ATMEL_SPI_SR 0x0010 +#define ATMEL_SPI_IER 0x0014 +#define ATMEL_SPI_IDR 0x0018 +#define ATMEL_SPI_IMR 0x001c +#define ATMEL_SPI_CSR(x) (0x0030 + 4 * (x)) +#define ATMEL_SPI_VERSION 0x00fc -#ifndef CONFIG_DM_SPI +/* Bits in CR */ +#define ATMEL_SPI_CR_SPIEN BIT(0) +#define ATMEL_SPI_CR_SPIDIS BIT(1) +#define ATMEL_SPI_CR_SWRST BIT(7) +#define ATMEL_SPI_CR_LASTXFER BIT(24) -static int spi_has_wdrbt(struct atmel_spi_slave *slave) -{ - unsigned int ver; +/* Bits in MR */ +#define ATMEL_SPI_MR_MSTR BIT(0) +#define ATMEL_SPI_MR_PS BIT(1) +#define ATMEL_SPI_MR_PCSDEC BIT(2) +#define ATMEL_SPI_MR_FDIV BIT(3) +#define ATMEL_SPI_MR_MODFDIS BIT(4) +#define ATMEL_SPI_MR_WDRBT BIT(5) +#define ATMEL_SPI_MR_LLB BIT(7) +#define ATMEL_SPI_MR_PCS(x) (((x) & 15) << 16) +#define ATMEL_SPI_MR_DLYBCS(x) ((x) << 24) - ver = spi_readl(slave, VERSION); +/* Bits in RDR */ +#define ATMEL_SPI_RDR_RD(x) (x) +#define ATMEL_SPI_RDR_PCS(x) ((x) << 16) - return (ATMEL_SPI_VERSION_REV(ver) >= 0x210); -} +/* Bits in TDR */ +#define ATMEL_SPI_TDR_TD(x) (x) +#define ATMEL_SPI_TDR_PCS(x) ((x) << 16) +#define ATMEL_SPI_TDR_LASTXFER BIT(24) -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct atmel_spi_slave *as; - unsigned int scbr; - u32 csrx; - void *regs; +/* Bits in SR/IER/IDR/IMR */ +#define ATMEL_SPI_SR_RDRF BIT(0) +#define ATMEL_SPI_SR_TDRE BIT(1) +#define ATMEL_SPI_SR_MODF BIT(2) +#define ATMEL_SPI_SR_OVRES BIT(3) +#define ATMEL_SPI_SR_ENDRX BIT(4) +#define ATMEL_SPI_SR_ENDTX BIT(5) +#define ATMEL_SPI_SR_RXBUFF BIT(6) +#define ATMEL_SPI_SR_TXBUFE BIT(7) +#define ATMEL_SPI_SR_NSSR BIT(8) +#define ATMEL_SPI_SR_TXEMPTY BIT(9) +#define ATMEL_SPI_SR_SPIENS BIT(16) - if (!spi_cs_is_valid(bus, cs)) - return NULL; +/* Bits in CSRx */ +#define ATMEL_SPI_CSRx_CPOL BIT(0) +#define ATMEL_SPI_CSRx_NCPHA BIT(1) +#define ATMEL_SPI_CSRx_CSAAT BIT(3) +#define ATMEL_SPI_CSRx_BITS(x) ((x) << 4) +#define ATMEL_SPI_CSRx_SCBR(x) ((x) << 8) +#define ATMEL_SPI_CSRx_SCBR_MAX GENMASK(7, 0) +#define ATMEL_SPI_CSRx_DLYBS(x) ((x) << 16) +#define ATMEL_SPI_CSRx_DLYBCT(x) ((x) << 24) - switch (bus) { - case 0: - regs = (void *)ATMEL_BASE_SPI0; - break; -#ifdef ATMEL_BASE_SPI1 - case 1: - regs = (void *)ATMEL_BASE_SPI1; - break; -#endif -#ifdef ATMEL_BASE_SPI2 - case 2: - regs = (void *)ATMEL_BASE_SPI2; - break; -#endif -#ifdef ATMEL_BASE_SPI3 - case 3: - regs = (void *)ATMEL_BASE_SPI3; - break; -#endif - default: - return NULL; - } +/* Bits in VERSION */ +#define ATMEL_SPI_VERSION_REV(x) ((x) & 0xfff) +#define ATMEL_SPI_VERSION_MFN(x) ((x) << 16) - - scbr = (get_spi_clk_rate(bus) + max_hz - 1) / max_hz; - if (scbr > ATMEL_SPI_CSRx_SCBR_MAX) - /* Too low max SCK rate */ - return NULL; - if (scbr < 1) - scbr = 1; - - csrx = ATMEL_SPI_CSRx_SCBR(scbr); - csrx |= ATMEL_SPI_CSRx_BITS(ATMEL_SPI_BITS_8); - if (!(mode & SPI_CPHA)) - csrx |= ATMEL_SPI_CSRx_NCPHA; - if (mode & SPI_CPOL) - csrx |= ATMEL_SPI_CSRx_CPOL; - - as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); - if (!as) - return NULL; - - as->regs = regs; - as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS - | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); - if (spi_has_wdrbt(as)) - as->mr |= ATMEL_SPI_MR_WDRBT; - - spi_writel(as, CSR(cs), csrx); - - return &as->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - free(as); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - /* Enable the SPI hardware */ - spi_writel(as, CR, ATMEL_SPI_CR_SPIEN); - - /* - * Select the slave. This should set SCK to the correct - * initial state, etc. - */ - spi_writel(as, MR, as->mr); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - - /* Disable the SPI hardware */ - spi_writel(as, CR, ATMEL_SPI_CR_SPIDIS); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct atmel_spi_slave *as = to_atmel_spi(slave); - unsigned int len_tx; - unsigned int len_rx; - unsigned int len; - u32 status; - const u8 *txp = dout; - u8 *rxp = din; - u8 value; - - if (bitlen == 0) - /* Finish any previously submitted transfers */ - goto out; - - /* - * TODO: The controller can do non-multiple-of-8 bit - * transfers, but this driver currently doesn't support it. - * - * It's also not clear how such transfers are supposed to be - * represented as a stream of bytes...this is a limitation of - * the current SPI interface. - */ - if (bitlen % 8) { - /* Errors always terminate an ongoing transfer */ - flags |= SPI_XFER_END; - goto out; - } - - len = bitlen / 8; - - /* - * The controller can do automatic CS control, but it is - * somewhat quirky, and it doesn't really buy us much anyway - * in the context of U-Boot. - */ - if (flags & SPI_XFER_BEGIN) { - spi_cs_activate(slave); - /* - * sometimes the RDR is not empty when we get here, - * in theory that should not happen, but it DOES happen. - * Read it here to be on the safe side. - * That also clears the OVRES flag. Required if the - * following loop exits due to OVRES! - */ - spi_readl(as, RDR); - } - - for (len_tx = 0, len_rx = 0; len_rx < len; ) { - status = spi_readl(as, SR); - - if (status & ATMEL_SPI_SR_OVRES) - return -1; - - if (len_tx < len && (status & ATMEL_SPI_SR_TDRE)) { - if (txp) - value = *txp++; - else - value = 0; - spi_writel(as, TDR, value); - len_tx++; - } - if (status & ATMEL_SPI_SR_RDRF) { - value = spi_readl(as, RDR); - if (rxp) - *rxp++ = value; - len_rx++; - } - } - -out: - if (flags & SPI_XFER_END) { - /* - * Wait until the transfer is completely done before - * we deactivate CS. - */ - do { - status = spi_readl(as, SR); - } while (!(status & ATMEL_SPI_SR_TXEMPTY)); - - spi_cs_deactivate(slave); - } - - return 0; -} - -#else +/* Constants for CSRx:BITS */ +#define ATMEL_SPI_BITS_8 0 +#define ATMEL_SPI_BITS_9 1 +#define ATMEL_SPI_BITS_10 2 +#define ATMEL_SPI_BITS_11 3 +#define ATMEL_SPI_BITS_12 4 +#define ATMEL_SPI_BITS_13 5 +#define ATMEL_SPI_BITS_14 6 +#define ATMEL_SPI_BITS_15 7 +#define ATMEL_SPI_BITS_16 8 #define MAX_CS_COUNT 4 +/* Register access macros */ +#define spi_readl(as, reg) \ + readl(as->regs + ATMEL_SPI_##reg) +#define spi_writel(as, reg, value) \ + writel(value, as->regs + ATMEL_SPI_##reg) + struct atmel_spi_platdata { struct at91_spi *regs; }; @@ -507,4 +392,3 @@ U_BOOT_DRIVER(atmel_spi) = { .priv_auto_alloc_size = sizeof(struct atmel_spi_priv), .probe = atmel_spi_probe, }; -#endif diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 6167bd164b..9663cca5e6 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -79,23 +79,8 @@ #define ATMEL_SPI_BITS_15 7 #define ATMEL_SPI_BITS_16 8 -struct atmel_spi_slave { - struct spi_slave slave; - void *regs; - u32 mr; -}; - -static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) -{ - return container_of(slave, struct atmel_spi_slave, slave); -} - /* Register access macros */ #define spi_readl(as, reg) \ readl(as->regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as->regs + ATMEL_SPI_##reg) - -#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#endif diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 97ac97b1a5..e1e9b45cc9 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -55,41 +55,6 @@ /* SPIDEF */ #define SPIDEF_CSDEF0_MASK BIT(0) -#ifndef CONFIG_DM_SPI -#define SPI0_BUS 0 -#define SPI0_BASE CONFIG_SYS_SPI_BASE -/* - * Define default SPI0_NUM_CS as 1 for existing platforms that uses this - * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS - * if more than one CS is supported and by defining CONFIG_SYS_SPI0. - */ -#ifndef CONFIG_SYS_SPI0 -#define SPI0_NUM_CS 1 -#else -#define SPI0_NUM_CS CONFIG_SYS_SPI0_NUM_CS -#endif - -/* - * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and - * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus - */ -#ifdef CONFIG_SYS_SPI1 -#define SPI1_BUS 1 -#define SPI1_NUM_CS CONFIG_SYS_SPI1_NUM_CS -#define SPI1_BASE CONFIG_SYS_SPI1_BASE -#endif - -/* - * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and - * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus - */ -#ifdef CONFIG_SYS_SPI2 -#define SPI2_BUS 2 -#define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS -#define SPI2_BASE CONFIG_SYS_SPI2_BASE -#endif -#endif - DECLARE_GLOBAL_DATA_PTR; /* davinci spi register set */ @@ -122,9 +87,6 @@ struct davinci_spi_regs { /* davinci spi slave */ struct davinci_spi_slave { -#ifndef CONFIG_DM_SPI - struct spi_slave slave; -#endif struct davinci_spi_regs *regs; unsigned int freq; /* current SPI bus frequency */ unsigned int mode; /* current SPI mode used */ @@ -346,124 +308,6 @@ out: return 0; } -#ifndef CONFIG_DM_SPI - -static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) -{ - return container_of(slave, struct davinci_spi_slave, slave); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - int ret = 0; - - switch (bus) { - case SPI0_BUS: - if (cs < SPI0_NUM_CS) - ret = 1; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - if (cs < SPI1_NUM_CS) - ret = 1; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - if (cs < SPI2_NUM_CS) - ret = 1; - break; -#endif - default: - /* Invalid bus number. Do nothing */ - break; - } - return ret; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* do nothing */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* do nothing */ -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct davinci_spi_slave *ds; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); - if (!ds) - return NULL; - - switch (bus) { - case SPI0_BUS: - ds->regs = (struct davinci_spi_regs *)SPI0_BASE; - break; -#ifdef CONFIG_SYS_SPI1 - case SPI1_BUS: - ds->regs = (struct davinci_spi_regs *)SPI1_BASE; - break; -#endif -#ifdef CONFIG_SYS_SPI2 - case SPI2_BUS: - ds->regs = (struct davinci_spi_regs *)SPI2_BASE; - break; -#endif - default: /* Invalid bus number */ - return NULL; - } - - ds->freq = max_hz; - ds->mode = mode; - - return &ds->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - free(ds); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - ds->cur_cs = slave->cs; - - return __davinci_spi_xfer(ds, bitlen, dout, din, flags); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - -#ifdef CONFIG_SPI_HALF_DUPLEX - ds->half_duplex = true; -#else - ds->half_duplex = false; -#endif - return __davinci_spi_claim_bus(ds, ds->slave.cs); -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct davinci_spi_slave *ds = to_davinci_spi(slave); - - __davinci_spi_release_bus(ds); -} - -#else static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) { struct davinci_spi_slave *ds = dev_get_priv(bus); @@ -582,4 +426,3 @@ U_BOOT_DRIVER(davinci_spi) = { .ops = &davinci_spi_ops, .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), }; -#endif diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 1cdb233110..78ad61ca37 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -100,13 +100,6 @@ struct fsl_dspi_priv { struct dspi *regs; }; -#ifndef CONFIG_DM_SPI -struct fsl_dspi { - struct spi_slave slave; - struct fsl_dspi_priv priv; -}; -#endif - __weak void cpu_dspi_port_conf(void) { } @@ -414,131 +407,7 @@ static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed) return 0; } -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) - return 1; - else - return 0; -} -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_dspi *dspi; - uint mcr_cfg_val; - - dspi = spi_alloc_slave(struct fsl_dspi, bus, cs); - if (!dspi) - return NULL; - - cpu_dspi_port_conf(); - -#ifdef CONFIG_SYS_FSL_DSPI_BE - dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; -#endif - - dspi->priv.regs = (struct dspi *)MMAP_DSPI; - -#ifdef CONFIG_M68K - dspi->priv.bus_clk = gd->bus_clk; -#else - dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); -#endif - dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; - - /* default: all CS signals inactive state is high */ - mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK | - DSPI_MCR_CRXF | DSPI_MCR_CTXF; - fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); - - for (i = 0; i < FSL_DSPI_MAX_CHIPSELECT; i++) - dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; - -#ifdef CONFIG_SYS_DSPI_CTAR0 - if (FSL_DSPI_MAX_CHIPSELECT > 0) - dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR1 - if (FSL_DSPI_MAX_CHIPSELECT > 1) - dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR2 - if (FSL_DSPI_MAX_CHIPSELECT > 2) - dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR3 - if (FSL_DSPI_MAX_CHIPSELECT > 3) - dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR4 - if (FSL_DSPI_MAX_CHIPSELECT > 4) - dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR5 - if (FSL_DSPI_MAX_CHIPSELECT > 5) - dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR6 - if (FSL_DSPI_MAX_CHIPSELECT > 6) - dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR7 - if (FSL_DSPI_MAX_CHIPSELECT > 7) - dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; -#endif - - fsl_dspi_cfg_speed(&dspi->priv, max_hz); - - /* configure transfer mode */ - fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); - - /* configure active state of CSX */ - fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); - - return &dspi->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - free(slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - uint sr_val; - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - - cpu_dspi_claim_bus(slave->bus, slave->cs); - - fsl_dspi_clr_fifo(&dspi->priv); - - /* check module TX and RX status */ - sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); - if ((sr_val & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) { - debug("DSPI RX/TX not ready!\n"); - return -EIO; - } - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - - dspi_halt(&dspi->priv, 1); - cpu_dspi_release_bus(slave->bus.slave->cs); -} - -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) -{ - struct fsl_dspi *dspi = (struct fsl_dspi *)slave; - return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); -} -#else static int fsl_dspi_child_pre_probe(struct udevice *dev) { struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); @@ -745,4 +614,3 @@ U_BOOT_DRIVER(fsl_dspi) = { .child_pre_probe = fsl_dspi_child_pre_probe, .bind = fsl_dspi_bind, }; -#endif diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 50d194f614..5c76fd962e 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,7 +3,9 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2020 NXP * Author: Mingkai Hu (Mingkai.hu@freescale.com) + * Chuanhua Han (chuanhua.han@nxp.com) */ #include @@ -14,10 +16,16 @@ #include #include #include +#include +#include +#include +#include struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -31,6 +39,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL +/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32 @@ -65,116 +76,27 @@ struct fsl_spi_slave { #define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; + unsigned int com = 0; + size_t data_len = fsl->data_len; - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); - - return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); } -void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi; + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); } static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -207,7 +129,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); } -static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -239,10 +162,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -261,13 +191,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -307,7 +238,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -350,37 +281,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); } free(buffer); return 0; } +void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; } -void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len; + struct fsl_spi_slave *fsl; - com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; } -void spi_cs_deactivate(struct spi_slave *slave) +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + free(fsl); } + +int spi_claim_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_claim_bus(fsl, slave->cs); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; +} + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index 0da4a80d71..e231e96e58 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -13,7 +13,10 @@ */ #include +#include +#include #include +#include #include #include #include @@ -34,34 +37,9 @@ #define MXSSSP_SMALL_TRANSFER 512 -static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) -{ - writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); - writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); -} - -static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) -{ - writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); - writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); -} - -#if !CONFIG_IS_ENABLED(DM_SPI) -struct mxs_spi_slave { - struct spi_slave slave; - uint32_t max_khz; - uint32_t mode; - struct mxs_ssp_regs *regs; -}; - -static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave) -{ - return container_of(slave, struct mxs_spi_slave, slave); -} -#else -#include -#include -#include +/* Base numbers of i.MX2[38] clk for ssp0 IP block */ +#define MXS_SSP_IMX23_CLKID_SSP0 33 +#define MXS_SSP_IMX28_CLKID_SSP0 46 #ifdef CONFIG_MX28 #define dtd_fsl_imx_spi dtd_fsl_imx28_spi @@ -87,20 +65,24 @@ struct mxs_spi_priv { unsigned int clk_id; unsigned int mode; }; -#endif -#if !CONFIG_IS_ENABLED(DM_SPI) -static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave, - char *data, int length, int write, unsigned long flags) +static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs) { - struct mxs_ssp_regs *ssp_regs = slave->regs; -#else + writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set); + writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr); +} + +static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs) +{ + writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr); + writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set); +} + static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv, char *data, int length, int write, unsigned long flags) { struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif if (flags & SPI_XFER_BEGIN) mxs_spi_start_xfer(ssp_regs); @@ -156,17 +138,10 @@ static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv, return 0; } -#if !CONFIG_IS_ENABLED(DM_SPI) -static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave, - char *data, int length, int write, unsigned long flags) -{ - struct mxs_ssp_regs *ssp_regs = slave->regs; -#else static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, char *data, int length, int write, unsigned long flags) { struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif const int xfer_max_sz = 0xff00; const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1; struct mxs_dma_desc *dp; @@ -207,11 +182,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, /* Invalidate the area, so no writeback into the RAM races with DMA */ invalidate_dcache_range(dstart, dstart + cache_data_count); -#if !CONFIG_IS_ENABLED(DM_SPI) - dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus; -#else dmach = priv->dma_channel; -#endif dp = desc; while (length) { @@ -288,20 +259,12 @@ static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv, return ret; } -#if !CONFIG_IS_ENABLED(DM_SPI) -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; -#else int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct udevice *bus = dev_get_parent(dev); struct mxs_spi_priv *priv = dev_get_priv(bus); struct mxs_ssp_regs *ssp_regs = priv->regs; -#endif int len = bitlen / 8; char dummy; int write = 0; @@ -345,99 +308,13 @@ int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen, if (!dma || (len < MXSSSP_SMALL_TRANSFER)) { writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); -#if !CONFIG_IS_ENABLED(DM_SPI) - return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags); -#else return mxs_spi_xfer_pio(priv, data, len, write, flags); -#endif } else { writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); -#if !CONFIG_IS_ENABLED(DM_SPI) - return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags); -#else return mxs_spi_xfer_dma(priv, data, len, write, flags); -#endif } } -#if !CONFIG_IS_ENABLED(DM_SPI) -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - /* MXS SPI: 4 ports and 3 chip selects maximum */ - if (!mxs_ssp_bus_id_valid(bus) || cs > 2) - return 0; - else - return 1; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct mxs_spi_slave *mxs_slave; - - if (!spi_cs_is_valid(bus, cs)) { - printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs); - return NULL; - } - - mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs); - if (!mxs_slave) - return NULL; - - if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) - goto err_init; - - mxs_slave->max_khz = max_hz / 1000; - mxs_slave->mode = mode; - mxs_slave->regs = mxs_ssp_regs_by_bus(bus); - - return &mxs_slave->slave; - -err_init: - free(mxs_slave); - return NULL; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - - free(mxs_slave); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave); - struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; - u32 reg = 0; - - mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - - writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) | - SSP_CTRL0_BUS_WIDTH_ONE_BIT, - &ssp_regs->hw_ssp_ctrl0); - - reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS; - reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0; - reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0; - writel(reg, &ssp_regs->hw_ssp_ctrl1); - - writel(0, &ssp_regs->hw_ssp_cmd0); - - mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ -} - -#else /* CONFIG_DM_SPI */ -/* Base numbers of i.MX2[38] clk for ssp0 IP block */ -#define MXS_SSP_IMX23_CLKID_SSP0 33 -#define MXS_SSP_IMX28_CLKID_SSP0 46 - static int mxs_spi_probe(struct udevice *bus) { struct mxs_spi_platdata *plat = dev_get_platdata(bus); @@ -625,4 +502,3 @@ U_BOOT_DRIVER(mxs_spi) = { .priv_auto_alloc_size = sizeof(struct mxs_spi_priv), .probe = mxs_spi_probe, }; -#endif diff --git a/drivers/spi/soft_spi_legacy.c b/drivers/spi/soft_spi_legacy.c deleted file mode 100644 index cc5ab5f991..0000000000 --- a/drivers/spi/soft_spi_legacy.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. - * - * Influenced by code from: - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include - -#include - -/*----------------------------------------------------------------------- - * Definitions - */ - -#ifdef DEBUG_SPI -#define PRINTD(fmt,args...) printf (fmt ,##args) -#else -#define PRINTD(fmt,args...) -#endif - -struct soft_spi_slave { - struct spi_slave slave; - unsigned int mode; -}; - -static inline struct soft_spi_slave *to_soft_spi(struct spi_slave *slave) -{ - return container_of(slave, struct soft_spi_slave, slave); -} - -/*=====================================================================*/ -/* Public Functions */ -/*=====================================================================*/ - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct soft_spi_slave *ss; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - ss = spi_alloc_slave(struct soft_spi_slave, bus, cs); - if (!ss) - return NULL; - - ss->mode = mode; - - /* TODO: Use max_hz to limit the SCK rate */ - - return &ss->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct soft_spi_slave *ss = to_soft_spi(slave); - - free(ss); -} - -int spi_claim_bus(struct spi_slave *slave) -{ -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - - /* - * Make sure the SPI clock is in idle state as defined for - * this slave. - */ - if (ss->mode & SPI_CPOL) - SPI_SCL(1); - else - SPI_SCL(0); - - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Nothing to do */ -} - -/*----------------------------------------------------------------------- - * SPI transfer - * - * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks - * "bitlen" bits in the SPI MISO port. That's just the way SPI works. - * - * The source of the outgoing bits is the "dout" parameter and the - * destination of the input bits is the "din" parameter. Note that "dout" - * and "din" can point to the same memory location, in which case the - * input data overwrites the output data (since both are buffered by - * temporary variables, this is OK). - */ -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) -{ -#ifdef CONFIG_SYS_IMMR - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; -#endif - struct soft_spi_slave *ss = to_soft_spi(slave); - uchar tmpdin = 0; - uchar tmpdout = 0; - const u8 *txd = dout; - u8 *rxd = din; - int cpol = ss->mode & SPI_CPOL; - int cpha = ss->mode & SPI_CPHA; - unsigned int j; - - PRINTD("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", - slave->bus, slave->cs, *(uint *)txd, *(uint *)rxd, bitlen); - - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); - - for(j = 0; j < bitlen; j++) { - /* - * Check if it is time to work on a new byte. - */ - if ((j % 8) == 0) { - if (txd) - tmpdout = *txd++; - else - tmpdout = 0; - if(j != 0) { - if (rxd) - *rxd++ = tmpdin; - } - tmpdin = 0; - } - - if (!cpha) - SPI_SCL(!cpol); - SPI_SDA(tmpdout & 0x80); - SPI_DELAY; - if (cpha) - SPI_SCL(!cpol); - else - SPI_SCL(cpol); - tmpdin <<= 1; - tmpdin |= SPI_READ; - tmpdout <<= 1; - SPI_DELAY; - if (cpha) - SPI_SCL(cpol); - } - /* - * If the number of bits isn't a multiple of 8, shift the last - * bits over to left-justify them. Then store the last byte - * read in. - */ - if (rxd) { - if ((bitlen % 8) != 0) - tmpdin <<= 8 - (bitlen % 8); - *rxd++ = tmpdin; - } - - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); - - return(0); -} diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h index c7f62b8b3e..10e0da8eb1 100644 --- a/drivers/usb/eth/r8152.h +++ b/drivers/usb/eth/r8152.h @@ -25,6 +25,7 @@ #define PLA_BDC_CR 0xd1a0 #define PLA_TEREDO_TIMER 0xd2cc #define PLA_REALWOW_TIMER 0xd2e8 +#define PLA_EXTRA_STATUS 0xd398 #define PLA_LEDSEL 0xdd90 #define PLA_LED_FEATURE 0xdd92 #define PLA_PHYAR 0xde00 @@ -76,6 +77,7 @@ #define USB_DEV_STAT 0xb808 #define USB_CONNECT_TIMER 0xcbf8 #define USB_BURST_SIZE 0xcfc0 +#define USB_FW_FIX_EN1 0xcfcc #define USB_USB_CTRL 0xd406 #define USB_PHY_CTRL 0xd408 #define USB_TX_AGG 0xd40a @@ -285,6 +287,9 @@ /* PLA_BOOT_CTRL */ #define AUTOLOAD_DONE 0x0002 +/* PLA_EXTRA_STATUS */ +#define U3P3_CHECK_EN BIT(7) + /* USB_USB2PHY */ #define USB2PHY_SUSPEND 0x0001 #define USB2PHY_L1 0x0002 @@ -304,6 +309,9 @@ #define STAT_SPEED_HIGH 0x0000 #define STAT_SPEED_FULL 0x0002 +/* USB_FW_FIX_EN1 */ +#define FW_IP_RESET_EN BIT(9) + /* USB_TX_AGG */ #define TX_AGG_MAX_THRESHOLD 0x03 diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c index 3ebbd533cc..f953b0384b 100644 --- a/drivers/usb/eth/r8152_fw.c +++ b/drivers/usb/eth/r8152_fw.c @@ -293,7 +293,7 @@ static u8 r8152b_pla_patch_a2[] = { 0x00, 0xbe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static u16 r8152b_pla_patch_a2_bp[] = { - 0xfc28, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad, + 0xfc26, 0x8000, 0xfc28, 0x17a5, 0xfc2a, 0x13ad, 0xfc2c, 0x184d, 0xfc2e, 0x01e1 }; static u16 r8153_ram_code_a[] = { @@ -321,181 +321,150 @@ static u16 r8153_ram_code_a[] = { 0xB438, 0x3591, 0xB436, 0xB820, 0xB438, 0x0210 }; static u8 r8153_usb_patch_c[] = { - 0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x2e, 0xe0, - 0x37, 0xe0, 0x3e, 0xe0, 0x6d, 0xe0, 0x78, 0xe0, + 0x08, 0xe0, 0x0a, 0xe0, 0x14, 0xe0, 0x58, 0xe0, + 0x64, 0xe0, 0x79, 0xe0, 0xab, 0xe0, 0xb6, 0xe0, 0x02, 0xc5, 0x00, 0xbd, 0x38, 0x3b, 0xdb, 0x49, 0x04, 0xf1, 0x06, 0xc3, 0x00, 0xbb, 0x5a, 0x02, 0x05, 0xc4, 0x03, 0xc3, 0x00, 0xbb, 0xa4, 0x04, - 0x7e, 0x02, 0x30, 0xd4, 0x30, 0x18, 0x18, 0xc1, - 0x0c, 0xe8, 0x17, 0xc6, 0xc7, 0x65, 0xd0, 0x49, + 0x7e, 0x02, 0x30, 0xd4, 0x65, 0xc6, 0x66, 0x61, + 0x92, 0x49, 0x12, 0xf1, 0x3e, 0xc0, 0x02, 0x61, + 0x97, 0x49, 0x05, 0xf0, 0x3c, 0xc0, 0x00, 0x61, + 0x90, 0x49, 0x0a, 0xf1, 0xca, 0x63, 0xb0, 0x49, + 0x09, 0xf1, 0xb1, 0x49, 0x05, 0xf0, 0x32, 0xc0, + 0x00, 0x71, 0x9e, 0x49, 0x03, 0xf1, 0xb0, 0x48, + 0x05, 0xe0, 0x30, 0x48, 0xda, 0x61, 0x10, 0x48, + 0xda, 0x89, 0x4a, 0xc6, 0xc0, 0x60, 0x85, 0x49, + 0x03, 0xf0, 0x31, 0x48, 0x04, 0xe0, 0xb1, 0x48, + 0xb2, 0x48, 0x0f, 0xe0, 0x30, 0x18, 0x1b, 0xc1, + 0x0f, 0xe8, 0x1a, 0xc6, 0xc7, 0x65, 0xd0, 0x49, 0x05, 0xf0, 0x32, 0x48, 0x02, 0xc2, 0x00, 0xba, 0x3e, 0x16, 0x02, 0xc2, 0x00, 0xba, 0x48, 0x16, - 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48, - 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1, - 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40, - 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0, 0x30, 0x18, - 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7, 0x02, 0xc0, - 0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x07, 0xc3, - 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, 0x02, 0xc3, - 0x00, 0xbb, 0x9c, 0x15, 0x20, 0xd4, 0x2b, 0xc5, - 0xa0, 0x77, 0x00, 0x1c, 0xa0, 0x9c, 0x28, 0xc5, - 0xa0, 0x64, 0xc0, 0x48, 0xc1, 0x48, 0xc2, 0x48, - 0xa0, 0x8c, 0xb1, 0x64, 0xc0, 0x48, 0xb1, 0x8c, - 0x20, 0xc5, 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48, - 0xc2, 0x48, 0xa0, 0x8c, 0x19, 0xc5, 0xa4, 0x64, - 0x44, 0x48, 0xa4, 0x8c, 0xb1, 0x64, 0x40, 0x48, - 0xb1, 0x8c, 0x14, 0xc4, 0x80, 0x73, 0x13, 0xc4, - 0x82, 0x9b, 0x11, 0x1b, 0x80, 0x9b, 0x0c, 0xc5, - 0xa0, 0x64, 0x40, 0x48, 0x41, 0x48, 0x42, 0x48, - 0xa0, 0x8c, 0x05, 0xc5, 0xa0, 0x9f, 0x02, 0xc5, - 0x00, 0xbd, 0x6c, 0x3a, 0x1e, 0xfc, 0x10, 0xd8, - 0x86, 0xd4, 0xf8, 0xcb, 0x20, 0xe4, 0x0a, 0xc0, - 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0x07, 0xc0, - 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9, - 0x02, 0x06, 0x00, 0xd4, 0x40, 0xb4, 0xfe, 0xc0, - 0x16, 0x61, 0x91, 0x48, 0x16, 0x89, 0xfb, 0xc0, - 0x11, 0x19, 0x0c, 0x89, 0x02, 0xc1, 0x00, 0xb9, - 0xd2, 0x05, 0x00, 0x00 }; + 0x02, 0xc2, 0x00, 0xba, 0x4a, 0x16, 0x02, 0xb4, + 0x09, 0xc2, 0x40, 0x99, 0x0e, 0x48, 0x42, 0x98, + 0x42, 0x70, 0x8e, 0x49, 0xfe, 0xf1, 0x02, 0xb0, + 0x80, 0xff, 0xc0, 0xd4, 0xe4, 0x40, 0x20, 0xd4, + 0xca, 0xcf, 0x00, 0xcf, 0x3c, 0xe4, 0x0c, 0xc0, + 0x00, 0x63, 0xb5, 0x49, 0x09, 0xc0, 0x30, 0x18, + 0x06, 0xc1, 0xea, 0xef, 0xf5, 0xc7, 0x02, 0xc0, + 0x00, 0xb8, 0xd0, 0x10, 0xe4, 0x4b, 0x00, 0xd8, + 0x14, 0xc3, 0x60, 0x61, 0x90, 0x49, 0x06, 0xf0, + 0x11, 0xc3, 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, + 0x08, 0xe0, 0x0a, 0xc6, 0xd4, 0x61, 0x93, 0x48, + 0xd4, 0x89, 0x02, 0xc1, 0x00, 0xb9, 0x72, 0x17, + 0x02, 0xc1, 0x00, 0xb9, 0x9c, 0x15, 0x00, 0xd8, + 0xef, 0xcf, 0x20, 0xd4, 0x30, 0x18, 0xe7, 0xc1, + 0xcb, 0xef, 0x2b, 0xc5, 0xa0, 0x77, 0x00, 0x1c, + 0xa0, 0x9c, 0x28, 0xc5, 0xa0, 0x64, 0xc0, 0x48, + 0xc1, 0x48, 0xc2, 0x48, 0xa0, 0x8c, 0xb1, 0x64, + 0xc0, 0x48, 0xb1, 0x8c, 0x20, 0xc5, 0xa0, 0x64, + 0x40, 0x48, 0x41, 0x48, 0xc2, 0x48, 0xa0, 0x8c, + 0x19, 0xc5, 0xa4, 0x64, 0x44, 0x48, 0xa4, 0x8c, + 0xb1, 0x64, 0x40, 0x48, 0xb1, 0x8c, 0x14, 0xc4, + 0x80, 0x73, 0x13, 0xc4, 0x82, 0x9b, 0x11, 0x1b, + 0x80, 0x9b, 0x0c, 0xc5, 0xa0, 0x64, 0x40, 0x48, + 0x41, 0x48, 0x42, 0x48, 0xa0, 0x8c, 0x05, 0xc5, + 0xa0, 0x9f, 0x02, 0xc5, 0x00, 0xbd, 0x6c, 0x3a, + 0x1e, 0xfc, 0x10, 0xd8, 0x86, 0xd4, 0xf8, 0xcb, + 0x20, 0xe4, 0x0a, 0xc0, 0x16, 0x61, 0x91, 0x48, + 0x16, 0x89, 0x07, 0xc0, 0x11, 0x19, 0x0c, 0x89, + 0x02, 0xc1, 0x00, 0xb9, 0x02, 0x06, 0x00, 0xd4, + 0x40, 0xb4, 0xfe, 0xc0, 0x16, 0x61, 0x91, 0x48, + 0x16, 0x89, 0xfb, 0xc0, 0x11, 0x19, 0x0c, 0x89, + 0x02, 0xc1, 0x00, 0xb9, 0xd2, 0x05, 0x00, 0x00 }; static u16 r8153_usb_patch_c_bp[] = { - 0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x162c, - 0xfc2e, 0x10ce, 0xfc30, 0x0000, 0xfc32, 0x3a28, 0xfc34, 0x05f8, - 0xfc36, 0x05c8 }; + 0xfc26, 0xa000, 0xfc28, 0x3b34, 0xfc2a, 0x027c, 0xfc2c, 0x15de, + 0xfc2e, 0x10ce, 0xfc30, 0x1adc, 0xfc32, 0x3a28, 0xfc34, 0x05f8, + 0xfc36, 0x05c8, 0xfc38, 0x00f3 }; static u8 r8153_pla_patch_c[] = { - 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1, - 0x06, 0xe1, 0x08, 0xe1, 0x40, 0xe1, 0xf1, 0xe1, - 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, - 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, - 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, - 0xb1, 0x49, 0x11, 0xf0, 0xb1, 0x48, 0x40, 0x9b, - 0x02, 0xc2, 0x00, 0xba, 0xde, 0x18, 0x00, 0xe0, - 0x1e, 0xfc, 0xbc, 0xc0, 0xf0, 0xc0, 0xde, 0xe8, - 0x00, 0x80, 0x00, 0x20, 0x2c, 0x75, 0xd4, 0x49, - 0x12, 0xf1, 0x32, 0xe0, 0xf8, 0xc2, 0x46, 0x71, - 0xf7, 0xc2, 0x40, 0x73, 0xbe, 0x49, 0x03, 0xf1, - 0xf5, 0xc7, 0x02, 0xe0, 0xf2, 0xc7, 0x4f, 0x30, - 0x26, 0x62, 0xa1, 0x49, 0xf0, 0xf1, 0x22, 0x72, - 0xa0, 0x49, 0xed, 0xf1, 0x25, 0x25, 0x18, 0x1f, - 0x97, 0x30, 0x91, 0x30, 0x36, 0x9a, 0x2c, 0x75, - 0x3c, 0xc3, 0x60, 0x73, 0xb1, 0x49, 0x0d, 0xf1, - 0xdc, 0x21, 0xbc, 0x25, 0x30, 0xc6, 0xc0, 0x77, - 0x04, 0x13, 0x21, 0xf0, 0x03, 0x13, 0x22, 0xf0, - 0x02, 0x13, 0x23, 0xf0, 0x01, 0x13, 0x24, 0xf0, - 0x08, 0x13, 0x08, 0xf1, 0x2e, 0x73, 0xba, 0x21, - 0xbd, 0x25, 0x05, 0x13, 0x03, 0xf1, 0x24, 0xc5, - 0x00, 0xbd, 0xd4, 0x49, 0x03, 0xf1, 0x1c, 0xc5, - 0x00, 0xbd, 0xc4, 0xc6, 0xc6, 0x67, 0x2e, 0x75, - 0xd7, 0x22, 0xdd, 0x26, 0x05, 0x15, 0x1b, 0xf0, - 0x14, 0xc6, 0x00, 0xbe, 0x13, 0xc5, 0x00, 0xbd, - 0x12, 0xc5, 0x00, 0xbd, 0xf1, 0x49, 0xfb, 0xf1, - 0xef, 0xe7, 0xf4, 0x49, 0xfa, 0xf1, 0xec, 0xe7, - 0xf3, 0x49, 0xf7, 0xf1, 0xe9, 0xe7, 0xf2, 0x49, - 0xf4, 0xf1, 0xe6, 0xe7, 0xb6, 0xc0, 0x50, 0x14, - 0x90, 0x13, 0xbc, 0x13, 0xf2, 0x14, 0x00, 0xa0, - 0xa0, 0xd1, 0x00, 0x00, 0xc0, 0x75, 0xd0, 0x49, - 0x46, 0xf0, 0x26, 0x72, 0xa7, 0x49, 0x43, 0xf0, - 0x22, 0x72, 0x25, 0x25, 0x20, 0x1f, 0x97, 0x30, - 0x91, 0x30, 0x40, 0x73, 0xf3, 0xc4, 0x1c, 0x40, - 0x04, 0xf0, 0xd7, 0x49, 0x05, 0xf1, 0x37, 0xe0, - 0x53, 0x48, 0xc0, 0x9d, 0x08, 0x02, 0x40, 0x66, - 0x64, 0x27, 0x06, 0x16, 0x30, 0xf1, 0x46, 0x63, - 0x3b, 0x13, 0x2d, 0xf1, 0x34, 0x9b, 0x18, 0x1b, - 0x93, 0x30, 0x2b, 0xc3, 0x10, 0x1c, 0x2b, 0xe8, - 0x01, 0x14, 0x25, 0xf1, 0x00, 0x1d, 0x26, 0x1a, - 0x8a, 0x30, 0x22, 0x73, 0xb5, 0x25, 0x0e, 0x0b, - 0x00, 0x1c, 0x2c, 0xe8, 0x1f, 0xc7, 0x27, 0x40, - 0x1a, 0xf1, 0x38, 0xe8, 0x32, 0x1f, 0x8f, 0x30, - 0x08, 0x1b, 0x24, 0xe8, 0x36, 0x72, 0x46, 0x77, - 0x00, 0x17, 0x0d, 0xf0, 0x13, 0xc3, 0x1f, 0x40, - 0x03, 0xf1, 0x00, 0x1f, 0x46, 0x9f, 0x44, 0x77, - 0x9f, 0x44, 0x5f, 0x44, 0x17, 0xe8, 0x0a, 0xc7, - 0x27, 0x40, 0x05, 0xf1, 0x02, 0xc3, 0x00, 0xbb, - 0xbe, 0x1a, 0x74, 0x14, 0xff, 0xc7, 0x00, 0xbf, - 0xb8, 0xcd, 0xff, 0xff, 0x02, 0x0c, 0x54, 0xa5, - 0xdc, 0xa5, 0x2f, 0x40, 0x05, 0xf1, 0x00, 0x14, - 0xfa, 0xf1, 0x01, 0x1c, 0x02, 0xe0, 0x00, 0x1c, - 0x80, 0xff, 0xb0, 0x49, 0x04, 0xf0, 0x01, 0x0b, - 0xd3, 0xa1, 0x03, 0xe0, 0x02, 0x0b, 0xd3, 0xa5, - 0x27, 0x31, 0x20, 0x37, 0x02, 0x0b, 0xd3, 0xa5, - 0x27, 0x31, 0x20, 0x37, 0x00, 0x13, 0xfb, 0xf1, - 0x80, 0xff, 0x22, 0x73, 0xb5, 0x25, 0x18, 0x1e, - 0xde, 0x30, 0xd9, 0x30, 0x64, 0x72, 0x11, 0x1e, - 0x68, 0x23, 0x16, 0x31, 0x80, 0xff, 0x08, 0xc2, - 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, 0x06, 0xff, - 0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, 0x1e, 0xfc, - 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, 0x04, 0x13, - 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, 0x02, 0x13, - 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, 0x08, 0x13, - 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, 0x03, 0xc3, - 0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, 0x02, 0xc6, - 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, 0x00, 0xbe, - 0x00, 0x00, 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49, - 0x1f, 0xf0, 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13, - 0x04, 0xf1, 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0, - 0x28, 0xc5, 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1, - 0x26, 0xc5, 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06, - 0x20, 0x37, 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5, - 0xa2, 0x73, 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3, - 0xa0, 0x73, 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5, - 0xa0, 0x74, 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5, - 0xa0, 0x76, 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e, - 0x10, 0xc6, 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74, - 0x48, 0x48, 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e, - 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, - 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, - 0xfa, 0x01, 0xf0, 0xc0, 0x18, 0x89, 0x00, 0x1d, - 0x43, 0xc3, 0x62, 0x62, 0xa0, 0x49, 0x06, 0xf0, - 0x41, 0xc0, 0x02, 0x71, 0x60, 0x99, 0x3f, 0xc1, - 0x03, 0xe0, 0x3c, 0xc0, 0x3d, 0xc1, 0x02, 0x99, - 0x00, 0x61, 0x67, 0x11, 0x3d, 0xf1, 0x69, 0x33, - 0x34, 0xc0, 0x28, 0x40, 0xf7, 0xf1, 0x35, 0xc0, - 0x00, 0x19, 0x81, 0x1b, 0x89, 0xe8, 0x32, 0xc0, - 0x04, 0x1a, 0x84, 0x1b, 0x85, 0xe8, 0x7a, 0xe8, - 0xa3, 0x49, 0xfe, 0xf0, 0x2c, 0xc0, 0x76, 0xe8, - 0xa1, 0x48, 0x29, 0xc0, 0x84, 0x1b, 0x7c, 0xe8, - 0x00, 0x1d, 0x69, 0x33, 0x00, 0x1e, 0x01, 0x06, - 0xff, 0x18, 0x30, 0x40, 0xfd, 0xf1, 0x7f, 0xc0, - 0x00, 0x76, 0x2e, 0x40, 0xf7, 0xf1, 0x21, 0x48, - 0x1a, 0xc0, 0x84, 0x1b, 0x6d, 0xe8, 0x76, 0xc0, - 0x61, 0xe8, 0xa1, 0x49, 0xfd, 0xf0, 0x12, 0xc0, - 0x00, 0x1a, 0x84, 0x1b, 0x65, 0xe8, 0x5a, 0xe8, - 0xa5, 0x49, 0xfe, 0xf0, 0x0a, 0xc0, 0x01, 0x19, - 0x81, 0x1b, 0x5e, 0xe8, 0x48, 0xe0, 0x8c, 0xd3, - 0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, 0x82, 0x00, - 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, 0xfa, 0xc0, - 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0x06, 0x11, - 0x06, 0xf1, 0x5d, 0xc0, 0x00, 0x61, 0x11, 0x48, - 0x00, 0x89, 0x35, 0xe0, 0x00, 0x11, 0x02, 0xf1, - 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1, 0x53, 0xc0, - 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2b, 0xe0, - 0x05, 0x11, 0x08, 0xf1, 0x4c, 0xc0, 0x00, 0x61, - 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48, 0x00, 0x89, - 0x11, 0xe0, 0xdc, 0xc0, 0x00, 0x61, 0x98, 0x20, - 0x98, 0x24, 0x25, 0x11, 0x1c, 0xf1, 0x40, 0xc0, - 0x25, 0xe8, 0x95, 0x49, 0x18, 0xf0, 0xd2, 0xc0, - 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, - 0x12, 0xf1, 0x35, 0xc0, 0x00, 0x61, 0x92, 0x49, - 0x0e, 0xf1, 0x12, 0x48, 0x00, 0x89, 0x2d, 0xc0, - 0x00, 0x19, 0x00, 0x89, 0x2b, 0xc0, 0x01, 0x89, - 0x27, 0xc0, 0x10, 0xe8, 0x25, 0xc0, 0x12, 0x48, - 0x81, 0x1b, 0x16, 0xe8, 0xb9, 0xc3, 0x62, 0x62, - 0xa0, 0x49, 0x05, 0xf0, 0xb5, 0xc3, 0x60, 0x71, - 0xb5, 0xc0, 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8, - 0xd6, 0x07, 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b, - 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, - 0x80, 0x71, 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4, - 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b, - 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff, - 0x08, 0xea, 0x10, 0xd4, 0x88, 0xd3, 0x30, 0xd4, - 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x00, 0xd8, - 0x02, 0xc0, 0x00, 0xb8, 0xe0, 0x08, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 0x5d, 0xe0, 0x07, 0xe0, 0x0f, 0xe0, 0x5a, 0xe0, + 0x59, 0xe0, 0x1f, 0xe0, 0x57, 0xe0, 0x3e, 0xe1, + 0x08, 0xc2, 0x40, 0x73, 0x3a, 0x48, 0x40, 0x9b, + 0x06, 0xff, 0x02, 0xc6, 0x00, 0xbe, 0xcc, 0x17, + 0x1e, 0xfc, 0x2c, 0x75, 0xdc, 0x21, 0xbc, 0x25, + 0x04, 0x13, 0x0b, 0xf0, 0x03, 0x13, 0x09, 0xf0, + 0x02, 0x13, 0x07, 0xf0, 0x01, 0x13, 0x05, 0xf0, + 0x08, 0x13, 0x03, 0xf0, 0x04, 0xc3, 0x00, 0xbb, + 0x03, 0xc3, 0x00, 0xbb, 0x50, 0x17, 0x3a, 0x17, + 0x33, 0xc5, 0xa0, 0x74, 0xc0, 0x49, 0x1f, 0xf0, + 0x30, 0xc5, 0xa0, 0x73, 0x00, 0x13, 0x04, 0xf1, + 0xa2, 0x73, 0x00, 0x13, 0x14, 0xf0, 0x28, 0xc5, + 0xa0, 0x74, 0xc8, 0x49, 0x1b, 0xf1, 0x26, 0xc5, + 0xa0, 0x76, 0xa2, 0x74, 0x01, 0x06, 0x20, 0x37, + 0xa0, 0x9e, 0xa2, 0x9c, 0x1e, 0xc5, 0xa2, 0x73, + 0x23, 0x40, 0x10, 0xf8, 0x04, 0xf3, 0xa0, 0x73, + 0x33, 0x40, 0x0c, 0xf8, 0x15, 0xc5, 0xa0, 0x74, + 0x41, 0x48, 0xa0, 0x9c, 0x14, 0xc5, 0xa0, 0x76, + 0x62, 0x48, 0xe0, 0x48, 0xa0, 0x9e, 0x10, 0xc6, + 0x00, 0xbe, 0x0a, 0xc5, 0xa0, 0x74, 0x48, 0x48, + 0xa0, 0x9c, 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, + 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, + 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, 0xfa, 0x01, + 0xf0, 0xc0, 0x18, 0x89, 0x74, 0xc0, 0xcd, 0xe8, + 0x80, 0x76, 0x00, 0x1d, 0x6e, 0xc3, 0x66, 0x62, + 0xa0, 0x49, 0x06, 0xf0, 0x64, 0xc0, 0x02, 0x71, + 0x60, 0x99, 0x62, 0xc1, 0x03, 0xe0, 0x5f, 0xc0, + 0x60, 0xc1, 0x02, 0x99, 0x00, 0x61, 0x0f, 0x1b, + 0x59, 0x41, 0x03, 0x13, 0x18, 0xf1, 0xe4, 0x49, + 0x20, 0xf1, 0xe5, 0x49, 0x1e, 0xf0, 0x59, 0xc6, + 0xd0, 0x73, 0xb7, 0x49, 0x08, 0xf0, 0x01, 0x0b, + 0x80, 0x13, 0x03, 0xf0, 0xd0, 0x8b, 0x03, 0xe0, + 0x3f, 0x48, 0xd0, 0x9b, 0x51, 0xc0, 0x10, 0x1a, + 0x84, 0x1b, 0xb1, 0xe8, 0x4b, 0xc2, 0x40, 0x63, + 0x30, 0x48, 0x0a, 0xe0, 0xe5, 0x49, 0x09, 0xf0, + 0x47, 0xc0, 0x00, 0x1a, 0x84, 0x1b, 0xa7, 0xe8, + 0x41, 0xc2, 0x40, 0x63, 0xb0, 0x48, 0x40, 0x8b, + 0x67, 0x11, 0x3f, 0xf1, 0x69, 0x33, 0x32, 0xc0, + 0x28, 0x40, 0xd2, 0xf1, 0x33, 0xc0, 0x00, 0x19, + 0x81, 0x1b, 0x99, 0xe8, 0x30, 0xc0, 0x04, 0x1a, + 0x84, 0x1b, 0x95, 0xe8, 0x8a, 0xe8, 0xa3, 0x49, + 0xfe, 0xf0, 0x2a, 0xc0, 0x86, 0xe8, 0xa1, 0x48, + 0x84, 0x1b, 0x8d, 0xe8, 0x00, 0x1d, 0x69, 0x33, + 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40, + 0xfd, 0xf1, 0x1f, 0xc0, 0x00, 0x76, 0x2e, 0x40, + 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b, + 0x7e, 0xe8, 0x74, 0x08, 0x72, 0xe8, 0xa1, 0x49, + 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b, + 0x76, 0xe8, 0x6b, 0xe8, 0xa5, 0x49, 0xfe, 0xf0, + 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x6f, 0xe8, + 0x5a, 0xe0, 0xb8, 0x0b, 0x50, 0xe8, 0x83, 0x00, + 0x82, 0x00, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, + 0x88, 0xd3, 0x10, 0xe0, 0x00, 0xd8, 0x24, 0xd4, + 0xf9, 0xc0, 0x57, 0xe8, 0x48, 0x33, 0xf3, 0xc0, + 0x00, 0x61, 0x6a, 0xc0, 0x47, 0x11, 0x03, 0xf0, + 0x57, 0x11, 0x05, 0xf1, 0x00, 0x61, 0x17, 0x48, + 0x00, 0x89, 0x41, 0xe0, 0x9c, 0x20, 0x9c, 0x24, + 0xd0, 0x49, 0x09, 0xf0, 0x04, 0x11, 0x07, 0xf1, + 0x00, 0x61, 0x97, 0x49, 0x38, 0xf0, 0x97, 0x48, + 0x00, 0x89, 0x2b, 0xe0, 0x00, 0x11, 0x05, 0xf1, + 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, 0x2f, 0xe0, + 0x06, 0x11, 0x05, 0xf1, 0x00, 0x61, 0x11, 0x48, + 0x00, 0x89, 0x29, 0xe0, 0x05, 0x11, 0x0f, 0xf1, + 0x00, 0x61, 0x93, 0x49, 0x1a, 0xf1, 0x91, 0x49, + 0x0a, 0xf0, 0x91, 0x48, 0x00, 0x89, 0x0f, 0xe0, + 0xc6, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, + 0x25, 0x11, 0x80, 0xff, 0xfa, 0xef, 0x17, 0xf1, + 0x38, 0xc0, 0x1f, 0xe8, 0x95, 0x49, 0x13, 0xf0, + 0xf4, 0xef, 0x11, 0xf1, 0x31, 0xc0, 0x00, 0x61, + 0x92, 0x49, 0x0d, 0xf1, 0x12, 0x48, 0x00, 0x89, + 0x29, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x27, 0xc0, + 0x01, 0x89, 0x23, 0xc0, 0x0e, 0xe8, 0x12, 0x48, + 0x81, 0x1b, 0x15, 0xe8, 0xae, 0xc3, 0x66, 0x62, + 0xa0, 0x49, 0x04, 0xf0, 0x64, 0x71, 0xa3, 0xc0, + 0x02, 0x99, 0x02, 0xc0, 0x00, 0xb8, 0xd6, 0x07, + 0x13, 0xc4, 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, + 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, + 0x82, 0x72, 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, + 0x80, 0x99, 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, + 0x30, 0xd4, 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, + 0x00, 0xd8, 0x02, 0xc6, 0x00, 0xbe, 0xe0, 0x08 }; static u16 r8153_pla_patch_c_bp[] = { 0xfc26, 0x8000, 0xfc28, 0x1306, 0xfc2a, 0x17ca, 0xfc2c, 0x171e, 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x01b4, 0xfc34, 0x07d4, - 0xfc36, 0x0894, 0xfc38, 0x00e7 }; + 0xfc36, 0x0894, 0xfc38, 0x00e6 }; static u16 r8153_ram_code_bc[] = { 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000, @@ -560,7 +529,7 @@ static u16 r8153_usb_patch_b_bp[] = { static u8 r8153_pla_patch_b[] = { 0x08, 0xe0, 0xea, 0xe0, 0xf2, 0xe0, 0x04, 0xe1, - 0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf3, 0xe1, + 0x09, 0xe1, 0x0e, 0xe1, 0x46, 0xe1, 0xf7, 0xe1, 0x14, 0xc2, 0x40, 0x73, 0xba, 0x48, 0x40, 0x9b, 0x11, 0xc2, 0x40, 0x73, 0xb0, 0x49, 0x17, 0xf0, 0xbf, 0x49, 0x03, 0xf1, 0x09, 0xc5, 0x00, 0xbd, @@ -642,51 +611,51 @@ static u8 r8153_pla_patch_b[] = { 0x0b, 0xc5, 0x20, 0x1e, 0xa0, 0x9e, 0xe5, 0x48, 0xa0, 0x9e, 0xf0, 0xe7, 0xbc, 0xc0, 0xc8, 0xd2, 0xcc, 0xd2, 0x28, 0xe4, 0xe6, 0x01, 0xf0, 0xc0, - 0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x60, 0x71, + 0x18, 0x89, 0x00, 0x1d, 0x3c, 0xc3, 0x64, 0x71, 0x3c, 0xc0, 0x02, 0x99, 0x00, 0x61, 0x67, 0x11, 0x3c, 0xf1, 0x69, 0x33, 0x35, 0xc0, 0x28, 0x40, 0xf6, 0xf1, 0x34, 0xc0, 0x00, 0x19, 0x81, 0x1b, - 0x8c, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b, - 0x88, 0xe8, 0x7d, 0xe8, 0xa3, 0x49, 0xfe, 0xf0, - 0x2b, 0xc0, 0x79, 0xe8, 0xa1, 0x48, 0x28, 0xc0, - 0x84, 0x1b, 0x7f, 0xe8, 0x00, 0x1d, 0x69, 0x33, + 0x91, 0xe8, 0x31, 0xc0, 0x04, 0x1a, 0x84, 0x1b, + 0x8d, 0xe8, 0x82, 0xe8, 0xa3, 0x49, 0xfe, 0xf0, + 0x2b, 0xc0, 0x7e, 0xe8, 0xa1, 0x48, 0x28, 0xc0, + 0x84, 0x1b, 0x84, 0xe8, 0x00, 0x1d, 0x69, 0x33, 0x00, 0x1e, 0x01, 0x06, 0xff, 0x18, 0x30, 0x40, - 0xfd, 0xf1, 0x18, 0xc0, 0x00, 0x76, 0x2e, 0x40, + 0xfd, 0xf1, 0x19, 0xc0, 0x00, 0x76, 0x2e, 0x40, 0xf7, 0xf1, 0x21, 0x48, 0x19, 0xc0, 0x84, 0x1b, - 0x70, 0xe8, 0x79, 0xc0, 0x64, 0xe8, 0xa1, 0x49, + 0x75, 0xe8, 0x10, 0xc0, 0x69, 0xe8, 0xa1, 0x49, 0xfd, 0xf0, 0x11, 0xc0, 0x00, 0x1a, 0x84, 0x1b, - 0x68, 0xe8, 0x5d, 0xe8, 0xa5, 0x49, 0xfe, 0xf0, - 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x61, 0xe8, - 0x4f, 0xe0, 0x88, 0xd3, 0x8c, 0xd3, 0xb8, 0x0b, + 0x6d, 0xe8, 0x62, 0xe8, 0xa5, 0x49, 0xfe, 0xf0, + 0x09, 0xc0, 0x01, 0x19, 0x81, 0x1b, 0x66, 0xe8, + 0x54, 0xe0, 0x10, 0xd4, 0x88, 0xd3, 0xb8, 0x0b, 0x50, 0xe8, 0x20, 0xb4, 0x10, 0xd8, 0x84, 0xd4, - 0xfc, 0xc0, 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, - 0x06, 0x11, 0x06, 0xf1, 0x60, 0xc0, 0x00, 0x61, - 0x11, 0x48, 0x00, 0x89, 0x3d, 0xe0, 0x00, 0x11, - 0x02, 0xf1, 0x03, 0xe0, 0x04, 0x11, 0x06, 0xf1, - 0x56, 0xc0, 0x00, 0x61, 0x92, 0x48, 0x00, 0x89, - 0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, 0x4f, 0xc0, - 0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, 0x91, 0x48, - 0x00, 0x89, 0x11, 0xe0, 0xde, 0xc0, 0x00, 0x61, - 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, 0x24, 0xf1, - 0x45, 0xc0, 0x29, 0xe8, 0x95, 0x49, 0x20, 0xf0, - 0xd4, 0xc0, 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, - 0x25, 0x11, 0x1a, 0xf1, 0x38, 0xc0, 0x00, 0x61, - 0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, 0x00, 0x89, - 0x30, 0xc0, 0x00, 0x19, 0x00, 0x89, 0x2e, 0xc0, - 0x01, 0x89, 0x2e, 0xc0, 0x04, 0x19, 0x81, 0x1b, - 0x1c, 0xe8, 0x2b, 0xc0, 0x14, 0x19, 0x81, 0x1b, - 0x18, 0xe8, 0x22, 0xc0, 0x0c, 0xe8, 0x20, 0xc0, - 0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, 0xb3, 0xc3, - 0x62, 0x71, 0xb3, 0xc0, 0x02, 0x99, 0x02, 0xc0, - 0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, 0x84, 0x98, - 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, - 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, 0x80, 0xff, - 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, 0x82, 0x9a, - 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, 0xfe, 0xf1, - 0x80, 0xff, 0x08, 0xea, 0x10, 0xd4, 0x30, 0xd4, + 0xfd, 0xc0, 0x52, 0xe8, 0x48, 0x33, 0xf9, 0xc0, + 0x00, 0x61, 0x9c, 0x20, 0x9c, 0x24, 0xd0, 0x49, + 0x04, 0xf0, 0x04, 0x11, 0x02, 0xf1, 0x03, 0xe0, + 0x00, 0x11, 0x06, 0xf1, 0x5c, 0xc0, 0x00, 0x61, + 0x92, 0x48, 0x00, 0x89, 0x3a, 0xe0, 0x06, 0x11, + 0x06, 0xf1, 0x55, 0xc0, 0x00, 0x61, 0x11, 0x48, + 0x00, 0x89, 0x33, 0xe0, 0x05, 0x11, 0x08, 0xf1, + 0x4e, 0xc0, 0x00, 0x61, 0x91, 0x49, 0x04, 0xf0, + 0x91, 0x48, 0x00, 0x89, 0x11, 0xe0, 0xd9, 0xc0, + 0x00, 0x61, 0x98, 0x20, 0x98, 0x24, 0x25, 0x11, + 0x24, 0xf1, 0x44, 0xc0, 0x29, 0xe8, 0x95, 0x49, + 0x20, 0xf0, 0xcf, 0xc0, 0x00, 0x61, 0x98, 0x20, + 0x98, 0x24, 0x25, 0x11, 0x1a, 0xf1, 0x37, 0xc0, + 0x00, 0x61, 0x92, 0x49, 0x16, 0xf1, 0x12, 0x48, + 0x00, 0x89, 0x2f, 0xc0, 0x00, 0x19, 0x00, 0x89, + 0x2d, 0xc0, 0x01, 0x89, 0x2d, 0xc0, 0x04, 0x19, + 0x81, 0x1b, 0x1c, 0xe8, 0x2a, 0xc0, 0x14, 0x19, + 0x81, 0x1b, 0x18, 0xe8, 0x21, 0xc0, 0x0c, 0xe8, + 0x1f, 0xc0, 0x12, 0x48, 0x81, 0x1b, 0x12, 0xe8, + 0xae, 0xc3, 0x66, 0x71, 0xae, 0xc0, 0x02, 0x99, + 0x02, 0xc0, 0x00, 0xb8, 0x96, 0x07, 0x13, 0xc4, + 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, + 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, + 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, + 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, 0x30, 0xd4, 0x10, 0xc0, 0x12, 0xe8, 0x8a, 0xd3, 0x28, 0xe4, - 0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 0x2c, 0xe4, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00 }; static u16 r8153_pla_patch_b_bp[] = { 0xfc26, 0x8000, 0xfc28, 0x1154, 0xfc2a, 0x1606, 0xfc2c, 0x155a, @@ -694,33 +663,71 @@ static u16 r8153_pla_patch_b_bp[] = { 0xfc36, 0x0000, 0xfc38, 0x007f }; static u16 r8153_ram_code_d[] = { - 0xa436, 0xb820, 0xa438, 0x0290, 0xa436, 0xa012, 0xa438, 0x0000, - 0xa436, 0xa014, 0xa438, 0x2c04, 0xb438, 0x2c07, 0xb438, 0x2c07, - 0xb438, 0x2c07, 0xb438, 0xa240, 0xb438, 0xa104, 0xb438, 0x2944, - 0xa436, 0xa01a, 0xa438, 0x0000, 0xa436, 0xa006, 0xa438, 0x0fff, - 0xa436, 0xa004, 0xa438, 0x0fff, 0xa436, 0xa002, 0xa438, 0x0fff, - 0xa436, 0xa000, 0xa438, 0x1943, 0xa436, 0xb820, 0xa438, 0x0210 }; + 0xB436, 0xB820, 0xB438, 0x0290, 0xB436, 0xA012, 0xB438, 0x0000, + 0xB436, 0xA014, 0xB438, 0x2c04, 0xB438, 0x2c07, 0xB438, 0x2c07, + 0xB438, 0x2c07, 0xB438, 0xa240, 0xB438, 0xa104, 0xB438, 0x2944, + 0xB436, 0xA01A, 0xB438, 0x0000, 0xB436, 0xA006, 0xB438, 0x0fff, + 0xB436, 0xA004, 0xB438, 0x0fff, 0xB436, 0xA002, 0xB438, 0x0fff, + 0xB436, 0xA000, 0xB438, 0x1943, 0xB436, 0xB820, 0xB438, 0x0210 }; static u8 usb_patch_d[] = { - 0x08, 0xe0, 0x0a, 0xe0, 0x0c, 0xe0, 0x1f, 0xe0, - 0x28, 0xe0, 0x2a, 0xe0, 0x2c, 0xe0, 0x2e, 0xe0, - 0x02, 0xc5, 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc3, - 0x00, 0xbb, 0x00, 0x00, 0x30, 0x18, 0x11, 0xc1, - 0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, 0x00, 0xba, - 0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, 0x40, 0x99, - 0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, 0x8e, 0x49, - 0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, 0xc0, 0xd4, - 0xe4, 0x40, 0x20, 0xd4, 0xb0, 0x49, 0x04, 0xf0, - 0x30, 0x18, 0x06, 0xc1, 0xef, 0xef, 0xfa, 0xc7, - 0x02, 0xc0, 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b, - 0x02, 0xc3, 0x00, 0xbb, 0x00, 0x00, 0x02, 0xc5, - 0x00, 0xbd, 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9, - 0x00, 0x00, 0x02, 0xc1, 0x00, 0xb9, 0x00, 0x00 }; + 0x08, 0xe0, 0x0e, 0xe0, 0x11, 0xe0, 0x24, 0xe0, + 0x2b, 0xe0, 0x33, 0xe0, 0x3a, 0xe0, 0x3c, 0xe0, + 0x1e, 0xc3, 0x70, 0x61, 0x12, 0x48, 0x70, 0x89, + 0x02, 0xc3, 0x00, 0xbb, 0x02, 0x17, 0x32, 0x19, + 0x02, 0xc3, 0x00, 0xbb, 0x44, 0x14, 0x30, 0x18, + 0x11, 0xc1, 0x05, 0xe8, 0x10, 0xc6, 0x02, 0xc2, + 0x00, 0xba, 0x94, 0x17, 0x02, 0xb4, 0x09, 0xc2, + 0x40, 0x99, 0x0e, 0x48, 0x42, 0x98, 0x42, 0x70, + 0x8e, 0x49, 0xfe, 0xf1, 0x02, 0xb0, 0x80, 0xff, + 0xc0, 0xd4, 0xe4, 0x40, 0x20, 0xd4, 0x30, 0x18, + 0x06, 0xc1, 0xf1, 0xef, 0xfc, 0xc7, 0x02, 0xc0, + 0x00, 0xb8, 0x38, 0x12, 0xe4, 0x4b, 0x0c, 0x61, + 0x92, 0x48, 0x93, 0x48, 0x95, 0x48, 0x96, 0x48, + 0x0c, 0x89, 0x02, 0xc0, 0x00, 0xb8, 0x0e, 0x06, + 0x30, 0x18, 0xf5, 0xc1, 0xe0, 0xef, 0x04, 0xc5, + 0x02, 0xc4, 0x00, 0xbc, 0x76, 0x3c, 0x1e, 0xfc, + 0x02, 0xc6, 0x00, 0xbe, 0x00, 0x00, 0x02, 0xc6, + 0x00, 0xbe, 0x00, 0x00 }; static u16 r8153_usb_patch_d_bp[] = { - 0xfc26, 0xa000, 0xfc28, 0x0000, 0xfc2a, 0x0000, 0xfc2c, 0x1792, - 0xfc2e, 0x1236, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000, - 0xfc36, 0x0000, 0xfc38, 0x000c }; + 0xfc26, 0xa000, 0xfc28, 0x16de, 0xfc2a, 0x1442, 0xfc2c, 0x1792, + 0xfc2e, 0x1236, 0xfc30, 0x0606, 0xfc32, 0x3c74, 0xfc34, 0x0000, + 0xfc36, 0x0000, 0xfc38, 0x003e }; + +static u8 pla_patch_d[] = { + 0x03, 0xe0, 0x16, 0xe0, 0x30, 0xe0, 0x12, 0xc2, + 0x40, 0x73, 0xb0, 0x49, 0x08, 0xf0, 0xb8, 0x49, + 0x06, 0xf0, 0xb8, 0x48, 0x40, 0x9b, 0x0b, 0xc2, + 0x40, 0x76, 0x05, 0xe0, 0x02, 0x61, 0x02, 0xc3, + 0x00, 0xbb, 0x54, 0x08, 0x02, 0xc3, 0x00, 0xbb, + 0x64, 0x08, 0x98, 0xd3, 0x1e, 0xfc, 0xfe, 0xc0, + 0x02, 0x62, 0xa0, 0x48, 0x02, 0x8a, 0x00, 0x72, + 0xa0, 0x49, 0x11, 0xf0, 0x13, 0xc1, 0x20, 0x62, + 0x2e, 0x21, 0x2f, 0x25, 0x00, 0x71, 0x9f, 0x24, + 0x0a, 0x40, 0x09, 0xf0, 0x00, 0x71, 0x18, 0x48, + 0xa0, 0x49, 0x03, 0xf1, 0x9f, 0x48, 0x02, 0xe0, + 0x1f, 0x48, 0x00, 0x99, 0x02, 0xc2, 0x00, 0xba, + 0xac, 0x0c, 0x08, 0xe9, 0x36, 0xc0, 0x00, 0x61, + 0x9c, 0x20, 0x9c, 0x24, 0x33, 0xc0, 0x07, 0x11, + 0x05, 0xf1, 0x00, 0x61, 0x17, 0x48, 0x00, 0x89, + 0x0d, 0xe0, 0x04, 0x11, 0x0b, 0xf1, 0x00, 0x61, + 0x97, 0x49, 0x08, 0xf0, 0x97, 0x48, 0x00, 0x89, + 0x23, 0xc0, 0x0e, 0xe8, 0x12, 0x48, 0x81, 0x1b, + 0x15, 0xe8, 0x1f, 0xc0, 0x00, 0x61, 0x67, 0x11, + 0x04, 0xf0, 0x02, 0xc0, 0x00, 0xb8, 0x42, 0x09, + 0x02, 0xc0, 0x00, 0xb8, 0x90, 0x08, 0x13, 0xc4, + 0x84, 0x98, 0x00, 0x1b, 0x86, 0x8b, 0x86, 0x73, + 0xbf, 0x49, 0xfe, 0xf1, 0x80, 0x71, 0x82, 0x72, + 0x80, 0xff, 0x09, 0xc4, 0x84, 0x98, 0x80, 0x99, + 0x82, 0x9a, 0x86, 0x8b, 0x86, 0x73, 0xbf, 0x49, + 0xfe, 0xf1, 0x80, 0xff, 0x08, 0xea, 0x30, 0xd4, + 0x50, 0xe8, 0x8a, 0xd3 }; + +static u16 r8153_pla_patch_d_bp[] = { + 0xfc26, 0x8000, 0xfc28, 0x0852, 0xfc2a, 0x0c92, 0xfc2c, 0x088c, + 0xfc2e, 0x0000, 0xfc30, 0x0000, 0xfc32, 0x0000, 0xfc34, 0x0000, + 0xfc36, 0x0000, 0xfc38, 0x0007 }; static void rtl_clear_bp(struct r8152 *tp) { @@ -956,10 +963,19 @@ void r8153_firmware(struct r8152 *tp) ocp_write_word(tp, MCU_TYPE_PLA, 0xd388, 0x08ca); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, + U3P3_CHECK_EN | 4); + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcfca); ocp_data |= 0x4000; ocp_write_word(tp, MCU_TYPE_USB, 0xcfca, ocp_data); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); } else if (tp->version == RTL_VER_06) { + u32 ocp_data; + r8153_pre_ram_code(tp, 0x7002); for (i = 0; i < ARRAY_SIZE(r8153_ram_code_d); i += 2) @@ -979,5 +995,22 @@ void r8153_firmware(struct r8152 *tp) ocp_write_word(tp, MCU_TYPE_USB, r8153_usb_patch_d_bp[i], r8153_usb_patch_d_bp[i+1]); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, 0x0000); + generic_ocp_write(tp, 0xf800, 0xff, sizeof(pla_patch_d), + pla_patch_d, MCU_TYPE_PLA); + + for (i = 0; i < ARRAY_SIZE(r8153_pla_patch_d_bp); i += 2) + ocp_write_word(tp, MCU_TYPE_PLA, + r8153_pla_patch_d_bp[i], + r8153_pla_patch_d_bp[i + 1]); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); + ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; + ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); + ocp_data |= FW_IP_RESET_EN; + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); } } diff --git a/env/Kconfig b/env/Kconfig index ca7fef682b..38e7fadbb9 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -562,7 +562,7 @@ config ENV_UBI_VID_OFFSET UBI VID offset for environment. If 0, no custom VID offset is used. config SYS_RELOC_GD_ENV_ADDR - bool "Relocate gd->en_addr" + bool "Relocate gd->env_addr" help Relocate the early env_addr pointer so we know it is not inside the binary. Some systems need this and for the rest, it doesn't hurt. diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h deleted file mode 100644 index a515bf9530..0000000000 --- a/include/configs/B4860QDS.h +++ /dev/null @@ -1,759 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * B4860 QDS board configuration file - */ -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg -#ifndef CONFIG_MTD_RAW_NAND -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif -#endif -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifndef CONFIG_ARCH_B4420 -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#endif - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR 0x77 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define I2C_CH_DEFAULT 0x8 -#define I2C_CH_VSC3316 0xc -#define I2C_CH_VSC3308 0xd - -#define VSC3316_TX_ADDRESS 0x70 -#define VSC3316_RX_ADDRESS 0x71 -#define VSC3308_TX_ADDRESS 0x02 -#define VSC3308_RX_ADDRESS 0x03 - -/* IDT clock synthesizers */ -#define CONFIG_IDT8T49N222A -#define I2C_CH_IDT 0x9 - -#define IDT_SERDES1_ADDRESS 0x6E -#define IDT_SERDES2_ADDRESS 0x6C - -/* Voltage monitor on channel 2*/ -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_ZM7300 -#define I2C_MUX_CH_DPM 0xa -#define I2C_DPM_ADDR 0x28 - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#if 0 -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#endif - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_DDR_RAW_TIMING - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x53 - -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ - FTIM0_NOR_TEADC(0x04) | \ - FTIM0_NOR_TEAHC(0x20)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ - FTIM2_NOR_TCH(0x0E) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define CONFIG_FSL_QIXIS_V2 -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x01 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x02 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * RapidIO - */ -#ifdef CONFIG_SYS_SRIO -#ifdef CONFIG_SRIO1 -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#endif - -#ifdef CONFIG_SRIO2 -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -#endif -#endif - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * MAPLE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull -#else -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 -#endif - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -#define CONFIG_SYS_DPAA_RMAN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 -#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 - -/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ -#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE ulpi - -#ifdef CONFIG_ARCH_B4860 -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ - "en_cpc:cpc2;" -#else -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - HWCONFIG \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=b4860qds/b4860qds.dtb\0" \ - "bdev=sda3\0" - -/* For emulation this causes u-boot to jump to the start of the proof point - app code automatically */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x01e00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h deleted file mode 100644 index 879173f6f2..0000000000 --- a/include/configs/BSC9131RDB.h +++ /dev/null @@ -1,337 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * BSC9131 RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_NAND_FSL_IFC - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ -#if defined(CONFIG_SYS_CLK_100) -#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ -#else -#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -/* DDR Setup */ -#undef CONFIG_SYS_DDR_RAW_TIMING -#undef CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#ifndef __ASSEMBLY__ -extern unsigned long get_sdram_size(void); -#endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * Memory map - * - * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable - * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M - * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M - * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K - * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K - * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M - * - */ - -/* - * IFC Definitions - */ - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ - | FTIM1_NAND_TWBE(0x1E) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NAND */ -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -/* I2C EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 - -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "BSC9131rdb" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9131rdb.dtb\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ - "bootm_size=0x37000000\0" \ - "othbootargs=ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h deleted file mode 100644 index ac37ae7cb8..0000000000 --- a/include/configs/BSC9132QDS.h +++ /dev/null @@ -1,548 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * BSC9132 QDS board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_NAND_SECBOOT -#define CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SYS_CLK_100_DDR_100) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#elif defined(CONFIG_SYS_CLK_100_DDR_133) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133000000 -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -/* DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ -#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_SIZE (1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* DDR3 Controller Settings */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 -#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 -#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 - -#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 -#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 -#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 - -#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 -#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 -#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 -#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 -#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 -#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 - -/*FIXME: the following params are constant w.r.t diff freq -combinations. this should be removed later -*/ -#if CONFIG_DDR_CLK_FREQ == 100000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#elif CONFIG_DDR_CLK_FREQ == 133000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 -#else -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#endif - -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ - -#define CONFIG_SYS_FLASH_BASE 0x88000000 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR_CSPR 0x88000101 -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) -/* NOR Flash Timing Params */ - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ - | FTIM0_NOR_TEADC(0x03) \ - | FTIM0_NOR_TAVDS(0x00) \ - | FTIM0_NOR_TEAHC(0x0f)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ - | FTIM1_NOR_TRAD_NOR(0x09) \ - | FTIM1_NOR_TSEQRAD_NOR(0x09)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ - | FTIM2_NOR_TCH(0x4) \ - | FTIM2_NOR_TWPH(0x7) \ - | FTIM2_NOR_TWP(0x1e)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ - | FTIM1_NAND_TWBE(0x1e) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* NAND */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_FSL_QIXIS -#endif -#ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_FPGA_BASE 0xffb00000 -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_BASE CONFIG_SYS_FPGA_BASE -#define QIXIS_LBMAP_SWITCH 9 -#define QIXIS_LBMAP_MASK 0x07 -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 -#endif - -/* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 - -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* I2C FPGA */ -#define CONFIG_I2C_FPGA -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 - -#define CONFIG_RTC_DS3231 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * SPI interface will not be available in case of NAND boot SPI CS0 will be - * used for SLIC - */ -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "BSC9132qds" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_SDCARD -#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -#else -#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9132qds.dtb\0" \ - "bdev=sda1\0" \ - CONFIG_DEF_HWCONFIG\ - "othbootargs=mem=880M ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ - "isolcpus=0\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "debug_halt_off=mw ff7e0e30 0xf0000000;" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h deleted file mode 100644 index 9a8cba6b7c..0000000000 --- a/include/configs/C29XPCIE.h +++ /dev/null @@ -1,443 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * C29XPCIE board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_TPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#ifdef CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "Slot 1" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 100000000 -#define CONFIG_SYS_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SYS_DDR_RAW_TIMING - -/* DDR ECC Setup*/ -#define CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - -#define CONFIG_SYS_SDRAM_SIZE 512 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* Platform SRAM setting */ -#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 -#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ - (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) -#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ - -/* 16Bit NOR Flash - S29GL512S10TFI01 */ -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) - -/* 8Bit NAND Flash - K9F1G08U0B */ -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ - | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ - | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ - FTIM0_NAND_TWP(0x0c) | \ - FTIM0_NAND_TWCHT(0x08) | \ - FTIM0_NAND_TWH(0x06)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ - FTIM1_NAND_TWBE(0x1d) | \ - FTIM1_NAND_TRR(0x08) | \ - FTIM1_NAND_TRP(0x0c)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x18)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NOR/NAND */ -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -/* CPLD on IFC, selected by CS2 */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ - | CONFIG_SYS_CPLD_BASE) - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* - * Config the L2 Cache as L2 SRAM - */ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -/* Default mode is RGMII mode */ -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define CONFIG_ETHPRIME "eTSEC1" -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_SYS_RAMBOOT) -#elif defined(CONFIG_MTD_RAW_NAND) -#ifdef CONFIG_TPL_BUILD -#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE -#endif -#endif - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=name/of/device-tree.dtb\0" \ - "othbootargs=ramdisk_size=600000\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h deleted file mode 100644 index 340574a985..0000000000 --- a/include/configs/MPC8536DS.h +++ /dev/null @@ -1,642 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. - */ - -/* - * mpc8536ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI1 1 /* Enable PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map -- xxx -this is wrong, needs updating - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ - CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ -#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ -#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ -#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ -#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ -#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ -#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ - CONFIG_SYS_NAND_BASE + 0x40000, \ - CONFIG_SYS_NAND_BASE + 0x80000, \ - CONFIG_SYS_NAND_BASE + 0xC0000} -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< PHY1 */ -#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ - -#if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=8536ds/mpc8536ds.dtb\0" \ -"bdev=sda3\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h deleted file mode 100644 index 2b761078bc..0000000000 --- a/include/configs/P1022DS.h +++ /dev/null @@ -1,593 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_MAX_OOBFREE 5 - -#ifdef CONFIG_MTD_RAW_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -/* High Level Configuration Options */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM - -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 2048 -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x40110104 -#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca -#define CONFIG_SYS_DDR_MODE_1 0x00441221 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0a280100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000008 -#define CONFIG_SYS_DDR_CONTROL_2 0x24401041 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#endif - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -#ifndef CONFIG_SYS_MONITOR_BASE -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Nand Flash */ -#if defined(CONFIG_NAND_FSL_ELBC) -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) -#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DEEP_SLEEP - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 -#endif -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 -#endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* PCIe Boot - Slave */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -/* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif -#endif - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#else -#define CONFIG_I2C_SET_DEFAULT_BUS_NUM -#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 -#endif - -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCIe - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - *SATA - */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -/* Default address of microcode for the Linux FMan driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 -#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 -#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ - "ramdiskfile=t1024qds/ramdisk.uboot\0" \ - "fdtfile=t1024qds/t1024qds.dtb\0" \ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "fdtaddr=d00000\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __T1024QDS_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h deleted file mode 100644 index 7ad018b6d7..0000000000 --- a/include/configs/T1040QDS.h +++ /dev/null @@ -1,667 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * T1040 QDS board configuration file - */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -/* support deep sleep */ -#define CONFIG_DEEP_SLEEP - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_MTD_NOR_FLASH -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* - * TDM Definition - */ -#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -/* I2C */ - -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 -#define CONFIG_SYS_FSL_I2C3_SPEED 50000 -#define CONFIG_SYS_FSL_I2C4_SPEED 50000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#endif - -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 4, Base address 203000 */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_FSL_ESDHC_ADAPTER_IDENT -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* Enable VSC9953 L2 Switch driver */ -#define CONFIG_VSC9953 -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t1040qds/t1040qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h deleted file mode 100644 index d92af7202b..0000000000 --- a/include/configs/T4240QDS.h +++ /dev/null @@ -1,555 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * T4240 QDS board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg -#if !defined(CONFIG_MTD_RAW_NAND) && !defined(CONFIG_SDCARD) -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 - -#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#endif -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_DDR_ECC - -#include "t4qds.h" - -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RST_FORCE_MEM 0x1 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_BRDCFG5 0x55 -#define QIXIS_MUX_SDHC 2 -#define QIXIS_MUX_SDHC_WIDTH8 1 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#else -#undef CONFIG_SYS_I2C -#undef CONFIG_SYS_FSL_I2C2_OFFSET -#undef CONFIG_SYS_FSL_I2C2_SLAVE -#undef CONFIG_SYS_FSL_I2C2_SPEED -#undef CONFIG_SYS_FSL_I2C_SLAVE -#undef CONFIG_SYS_FSL_I2C_SPEED -#undef CONFIG_SYS_FSL_I2C_OFFSET -#endif - -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ - -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_MUX_CH_VSC3316_FS 0xc -#define I2C_MUX_CH_VSC3316_BS 0xd - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define VSC3316_FSM_TX_ADDR 0x70 -#define VSC3316_FSM_RX_ADDR 0x71 - -/* - * RapidIO - */ - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif -/* - * eSPI - Enhanced SPI - */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#define FM1_10GEC1_PHY_ADDR 0x0 -#define FM1_10GEC2_PHY_ADDR 0x1 -#define FM2_10GEC1_PHY_ADDR 0x2 -#define FM2_10GEC2_PHY_ADDR 0x3 -#endif - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* -* USB -*/ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_ESDHC_DETECT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ - IS_SVR_REV(get_svr(), 1, 0)) -#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) -#endif - - -#define __USB_PHY_TYPE utmi - -/* - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way - * interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_ARCH_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t4240qds/t4240qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h deleted file mode 100644 index ecf308e381..0000000000 --- a/include/configs/omap3_pandora.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2010 - * GraÅžvydas Ignotas - * - * Configuration settings for the OMAP3 Pandora. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* override base for compatibility with MLO the device ships with */ - -#include - -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 - - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd; " \ - "setenv bootargs ${bootargs_ubi}; " \ - "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \ - "source ${loadaddr}; " \ - "fi; " \ - "ubi part boot && ubifsmount ubi:boot && " \ - "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "usbtty=cdc_acm\0" \ - "bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ - "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - -/* memtest works on */ - -#if defined(CONFIG_MTD_RAW_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h deleted file mode 100644 index d731f9c8fa..0000000000 --- a/include/configs/p1_twr.h +++ /dev/null @@ -1,480 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ P1 Tower boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#if defined(CONFIG_TWR_P1025) -#define CONFIG_BOARDNAME "TWR-P1025" -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ -#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ - -#define CONFIG_DDR_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ - -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00220004 -#define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa880de -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x80461320 -#define CONFIG_SYS_DDR_MODE_2 0x00008000 -#define CONFIG_SYS_DDR_INTERVAL 0x09480000 - -/* - * Memory map - * - * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus - * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable - * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable - * - * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable - * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 - -#define CONFIG_SYS_SSD_BASE 0xe0000000 -#define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE -#define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ - BR_PS_16 | BR_V) -#define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) - -#define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM -#define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -/* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -/* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ - -/* Serial Port - * open - index 2 - * shorted - index 1 - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 - -/* - * I2C2 EEPROM - */ -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 - -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#if defined(CONFIG_PCI) -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#undef CONFIG_TSEC2 -#undef CONFIG_TSEC2_NAME -#define CONFIG_TSEC3 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#undef CONFIG_HAS_ETH2 -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_QE -/* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xefec0000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#endif /* CONFIG_QE */ - -#ifdef CONFIG_TWR_P1025 -/* - * QE UEC ethernet configuration - */ -#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) - -#undef CONFIG_UEC_ETH -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* ETH1 */ -#define CONFIG_HAS_ETH0 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH1 */ - -#define CONFIG_UEC_ETH5 /* ETH5 */ -#define CONFIG_HAS_ETH1 - -#ifdef CONFIG_UEC_ETH5 -#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ -#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ -#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ -#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_TWR-P1025 */ - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#ifdef CONFIG_SYS_RAMBOOT -#ifdef CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"loadaddr=1000000\0" \ -"bootfile=uImage\0" \ -"dtbfile=twr-p1025twr.dtb\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ -"kernelflash=tftpboot $loadaddr $bootfile; " \ - "protect off 0xefa80000 +$filesize; " \ - "erase 0xefa80000 +$filesize; " \ - "cp.b $loadaddr 0xefa80000 $filesize; " \ - "protect on 0xefa80000 +$filesize; " \ - "cmp.b $loadaddr 0xefa80000 $filesize\0" \ -"dtbflash=tftpboot $loadaddr $dtbfile; " \ - "protect off 0xefe80000 +$filesize; " \ - "erase 0xefe80000 +$filesize; " \ - "cp.b $loadaddr 0xefe80000 $filesize; " \ - "protect on 0xefe80000 +$filesize; " \ - "cmp.b $loadaddr 0xefe80000 $filesize\0" \ -"ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ - "protect off 0xeeb80000 +$filesize; " \ - "erase 0xeeb80000 +$filesize; " \ - "cp.b $loadaddr 0xeeb80000 $filesize; " \ - "protect on 0xeeb80000 +$filesize; " \ - "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ -"qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ - "protect off 0xefec0000 +$filesize; " \ - "erase 0xefec0000 +$filesize; " \ - "cp.b $loadaddr 0xefec0000 $filesize; " \ - "protect on 0xefec0000 +$filesize; " \ - "cmp.b $loadaddr 0xefec0000 $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=1e00000\0" \ -"bdev=sda1\0" \ -"norbootaddr=ef080000\0" \ -"norfdtaddr=ef040000\0" \ -"ramdisk_size=120000\0" \ -"usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ -"console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" - -#define CONFIG_NFSBOOTCOMMAND \ -"setenv bootargs root=/dev/nfs rw " \ -"nfsroot=$serverip:$rootpath " \ -"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile&&" \ -"tftp $fdtaddr $fdtfile&&" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ -"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"usb start;" \ -"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ -"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_USB_FAT_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"fatload usb 0:2 $loadaddr $bootfile;" \ -"fatload usb 0:2 $fdtaddr $fdtfile;" \ -"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_USB_EXT2_BOOT \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"usb start;" \ -"ext2load usb 0:4 $loadaddr $bootfile;" \ -"ext2load usb 0:4 $fdtaddr $fdtfile;" \ -"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NORBOOT \ -"setenv bootargs root=/dev/mtdblock3 rw " \ -"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ -"bootm $norbootaddr - $norfdtaddr" - -#define CONFIG_RAMBOOTCOMMAND_TFTP \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"tftp $ramdiskaddr $ramdiskfile;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs " \ -"ramdisk_size=$ramdisk_size;" \ -"bootm 0xefa80000 0xeeb80000 0xefe80000" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h deleted file mode 100644 index 706a8a2a87..0000000000 --- a/include/configs/pcm051.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * pcm051.h - * - * Phytec phyCORE-AM335x (pcm051) boards information header - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_PCM051_H -#define __CONFIG_PCM051_H - -#include - -#define CONFIG_MACH_TYPE MACH_TYPE_PCM051 - -/* set to negative value for no autoboot */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" \ - "run nandboot\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(NAND, nand, 0) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include - -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootfile=uImage\0" \ - "fdtfile=am335x-wega-rdk.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run args_mmc; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - BOOTENV - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - -/* - * USB configuration - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -#endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 1b014c1022..b632ae010d 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -53,10 +53,6 @@ /* UART Configuration */ #define CONFIG_SYS_NS16550_MEM32 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE @@ -68,19 +64,6 @@ /* SPI Configuration */ #define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) -#define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE -#define CONFIG_SYS_SPI0_NUM_CS 4 -#define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE -#define CONFIG_SYS_SPI1_NUM_CS 4 -#define CONFIG_SYS_SPI2 -#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE -#define CONFIG_SYS_SPI2_NUM_CS 4 -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif /* Network Configuration */ #define CONFIG_BOOTP_DEFAULT diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000000..812933f51c --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 8e8cd2cc1a..e148eaa880 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -4,6 +4,7 @@ *------------------------------------------------------------------- * * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc + * Copyright 2020 NXP */ #ifndef __FSL_ESDHC_H__ @@ -98,6 +99,7 @@ #define PROCTL_DTW_4 0x00000002 #define PROCTL_DTW_8 0x00000004 #define PROCTL_D3CD 0x00000008 +#define PROCTL_VOLT_SEL 0x00000400 #define CMDARG 0x0002e008 diff --git a/include/rand.h b/include/rand.h index c9d15f50a1..4c54fbbd10 100644 --- a/include/rand.h +++ b/include/rand.h @@ -22,7 +22,7 @@ void srand(unsigned int seed); /** * rand() - Get a 32-bit pseudo-random number * - * @returns next random number in the sequence + * Return: next random number in the sequence */ unsigned int rand(void); @@ -32,8 +32,8 @@ unsigned int rand(void); * This version of the function allows multiple sequences to be used at the * same time, since it requires the caller to store the seed value. * - * @seed value to use, updated on exit - * @returns next random number in the sequence + * @seedp: seed value to use, updated on exit + * Return: next random number in the sequence */ unsigned int rand_r(unsigned int *seedp); diff --git a/include/rng.h b/include/rng.h index d2c0f9af62..37af554363 100644 --- a/include/rng.h +++ b/include/rng.h @@ -10,22 +10,32 @@ struct udevice; /** * dm_rng_read() - read a random number seed from the rng device - * @buffer: input buffer to put the read random seed into - * @size: number of bytes of random seed read * - * Return: 0 if OK, -ve on error + * The function blocks until the requested number of bytes is read. + * + * @dev: random number generator device + * @buffer: input buffer to put the read random seed into + * @size: number of random bytes to read + * Return: 0 if OK, -ve on error */ int dm_rng_read(struct udevice *dev, void *buffer, size_t size); -/* struct dm_rng_ops - Operations for the hwrng uclass */ +/** + * struct dm_rng_ops - operations for the hwrng uclass + * + * This structures contains the function implemented by a hardware random + * number generation device. + */ struct dm_rng_ops { /** - * @read() - read a random number seed + * @read: read a random bytes * - * @data: input buffer to read the random seed - * @max: total number of bytes to read + * The function blocks until the requested number of bytes is read. * - * Return: 0 if OK, -ve on error + * @read.dev: random number generator device + * @read.data: input buffer to read the random seed into + * @read.max: number of random bytes to read + * @read.Return: 0 if OK, -ve on error */ int (*read)(struct udevice *dev, void *data, size_t max); }; diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 478aaf50d3..230d41ae5e 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -369,7 +369,7 @@ bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp, /* 3. Extra data excluding Certificates Table */ if (bytes_hashed + authsz < len) { - debug("extra data for hash: %lu\n", + debug("extra data for hash: %zu\n", len - (bytes_hashed + authsz)); efi_image_region_add(regs, efi + bytes_hashed, efi + len - authsz, 0); diff --git a/lib/optee/optee.c b/lib/optee/optee.c index e59b5766e7..457d4cca8a 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -156,8 +156,9 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) /* optee inserts its memory regions as reserved-memory nodes */ nodeoffset = fdt_subnode_offset(old_blob, 0, "reserved-memory"); if (nodeoffset >= 0) { - subnode = fdt_first_subnode(old_blob, nodeoffset); - while (subnode >= 0) { + for (subnode = fdt_first_subnode(old_blob, nodeoffset); + subnode >= 0; + subnode = fdt_next_subnode(old_blob, subnode)) { const char *name = fdt_get_name(old_blob, subnode, NULL); if (!name) @@ -197,8 +198,6 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) if (ret < 0) return ret; } - - subnode = fdt_next_subnode(old_blob, subnode); } } diff --git a/lib/strto.c b/lib/strto.c index 3d77115d4d..c00bb5895d 100644 --- a/lib/strto.c +++ b/lib/strto.c @@ -22,25 +22,9 @@ static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) *base = 16; else *base = 8; - } else { - int i = 0; - char var; - + } else *base = 10; - - do { - var = tolower(s[i++]); - if (var >= 'a' && var <= 'f') { - *base = 16; - break; - } - - if (!(var >= '0' && var <= '9')) - break; - } while (var); - } } - if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x') s += 2; return s; diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2210f46e44..f6bf6f2474 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -3810,7 +3810,6 @@ CONFIG_SYS_SPI_MXC_WAIT CONFIG_SYS_SPI_RTC_DEVID CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE -CONFIG_SYS_SPI_WRITE_TOUT CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE