brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1

Browse Source 
Sync the device tree with 5.8-rc1.

It basically contains the following extra kernel commit:

commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date:   Wed Apr 15 16:44:17 2020 +0100

    ARM: dts: imx6-sr-som: add ethernet PHY configuration

    Add ethernet PHY configuration ahead of removing the quirk that
    configures the clocking mode for the PHY.  The RGMII delay is
    already set correctly.

    Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
    Reviewed-by: Fabio Estevam <festevam@gmail.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>

, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Fabio Estevam 2020-06-18 20:21:19 -03:00 committed by Stefano Babic
parent 89b5bd54c1
commit db86e6c66a
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
arch/arm/dts/imx6qdl-sr-som.dtsi
View File

@ -53,10 +53,21 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-handle = <&phy>;
phy-mode = "rgmii-id";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
reg = <0>;
qca,clk-out-frequency = <125000000>;
};
};
};
&iomuxc {