This function is no more used, and replaced by psci_save
which save also context id as requested by PSCI requirements.
Even if the context id is not used by Linux, it should be saved
and restored in r0 when the CPU_ON is performed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Replace the psci_save_target_pc call by the new function
psci_save(cpu, pc,context_id)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Add PSCI v1.0 support for Linux and manage PSCI state
for each CPU (affinity 0 level) with all mandatory functions:
- PSCI_VERSION
- CPU_SUSPEND
- CPU_OFF
- CPU_ON
- AFFINITY_INFO
- SYSTEM_OFF
- SYSTEM_RESET
- PSCI_FEATURES
and 1 optional to avoid Linux warning
- MIGRATE_INFO_TYPE
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: CITOOLS <smet-aci-reviews@lists.codex.cro.st.com>
The added function psci_arch_cpu_entry() is called
during psci_cpu_entry() and can be used by arch to handle
PSCI state transition from ON_PENDING to ON.
The default weak function is empty: not behavior change.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Save and use the 3rd parameter of PSCI CPU_ON request: context_id.
The context_id parameter is only meaningful to the caller.
U-Boot PSCI preserves a copy of the value passed in this parameter.
Following wakeup from a powerdown state, U-BOOT PSCI places
this value in R0 when it first enters the OS.
NB: this context id is not (yet?) used by Linux but it is mandatory
to be PSCI compliant.
update armv7 psci functions:
- psci_save_target_pc(): keep for backward compatibility with
current platform (only save PC and force context id to 0)
=> should be removed when all platform migrate to the new API
- psci_save(): new API to use by ARMv7 platform with PSCI,
save pc (= entry_point_address) and context_id
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have multiple licenses (in
these cases, dual license) declared in the SPDX-License-Identifier tag.
In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A
or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B"
as per the Linux Kernel style document. Note that parenthesis are
allowed so when they were used before we continue to use them.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
Banana Pi BPI-M2 Berry is a quad-core mini single board computer
built with Allwinner V40 SoC. It features
- Quad Core ARM Cortex A7 CPU V40
- 1GB of RAM .
- microSD/SATA port..
- onboard WiFi and BT
- 4 USB A 2.0 ports
- 1 USB OTG port
- 1 HDMI port
- 1 audio jack
- DC power port
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
omap-common cache enabling sequence relies on cpu_init_cp15()
(inside start.S) for enabling I-caches. But cpu_init_cp15()
can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So
enable I-caches if not enabled already.
Debugged-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Pull the symbol from the boards and zap struct rmobile_sysinfo as they
are rather useless. The entire purpose of that whole machinery was to
print board name in the CONFIG_ARCH_RMOBILE_BOARD_STRING. Do that in a
far simpler and more contained manner.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Convert the symbol to Kconfig, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The dts Makefile entries for the H3 are not ordered correctly.
Move the Nano Pi entries before the Orange Pi so they are.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds a device tree file for the H5 version of the Libre
Computer Board ALL-H3-CC. It is the same board first introduced in
commit afe2754412 ("sunxi: Add support for Libre Computer Board
ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H5 SoC, and
has 4Gb DDR3 chips instead of 2Gb ones.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This patch adds a device tree file for the H2+ version of the Libre
Computer Board ALL-H3-CC. It is the same board first introduced in
commit afe2754412 ("sunxi: Add support for Libre Computer Board
ALL-H3-CC H3 ver."), with the H3 SoC replaced with the H2+ SoC, and
has only two 2Gb DDR3 chips instead of four.
The device tree utilizes the common board design file for ALL-H3-CC,
providing just the model strings and SoC specifics.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The Libre Computer Project ALL-H3-CC has three models, all using the
same board design, but with different pin compatible SoCs and amount of
DRAM.
Currently only the H3 1GB DRAM variant is supported. To support the two
other variants, first split the original device tree into a common board
design part and an SoC specific part.
The SoC part only defines which SoC is used and model name, and includes
the SoC specific dtsi file and the common design dtsi file.
Also fix up the SPDX identifier line to use the correct comment style,
and place it on the first line.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
If CONFIG_SPL_SERIAL_SUPPORT is disabled then the build fails because
serial_init is undefined. Guard preloader_console_init() appropriately
to fix this.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
SYS_ARCH_TIMER guards the usage of the ARM Generic Timer (aka arch
timer) in U-Boot.
At the moment it is mandatory for ARMv8 and used by a few ARMv7 boards.
Add a proper Kconfig symbol to express this dependency properly,
allowing certain board configuration to later disable arch timer in case
there are any problems with it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[tuomas: rebase + fix conflicts and resync with moveconfig & use select]
Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
The default of DISTRO_DEFAULTS is messy. Using the 'imply' keyword
is equivalent and cleaner.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
As of clang-5.0, things have changed a bit. First, we cannot
automatically guess -target values as if we do not pass one with CC then
cc-option will fail. Second, to disable movt/movw relocations the
argument has become -mno-movt.
Related to the target part, we cannot use arm-none-eabi as that ends up
being too generic of an ARM target for things like say rpi_3_32b to
work.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_SPI
This partly involves updating code that assumes that CONFIG_SPI implies
things that are specific to the MPC8xx SPI driver. For now, just update
the CONFIG tests. This also involves reworking the default for
CONFIG_SYS_DEF_EEPROM_ADDR so that we don't set it when we cannot make a
reasonable default, as it does not cause any compile failures.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This allows using the full SPL framework on mxs devices. In this
mode, the u-boot.sb image loaded by the boot ROM contains only the
SPL which then loads U-Boot proper or a kernel in falcon mode.
Signed-off-by: Mans Rullgard <mans@mansr.com>
With full SPL enabled, the loaded image overwrites the mxs_spl_data
location. Moving it a slightly lower address fixes this.
Signed-off-by: Mans Rullgard <mans@mansr.com>
When building in Thumb mode, the linker might generate mode switching
stubs in .glue sections. Include these in the final link.
Signed-off-by: Mans Rullgard <mans@mansr.com>
The code attempts to preserve the value of LR by storing it in R12/IP
across the lowevel_init() call. However, this register is not saved
by the callee. Use a register that guaranteed to be preserved instead.
Signed-off-by: Mans Rullgard <mans@mansr.com>
With the full SPL framework enabled, lowlevel_init() is required.
Make the empty stub weak so boards can override it.
Signed-off-by: Mans Rullgard <mans@mansr.com>
The E2 Alt port was broken since some time. This patch updates
the E2 Alt port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The M2-N Gose port was broken since some time. This patch updates
the M2-N Gose port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The H2 Lager port was broken since some time. This patch updates
the H2 Lager port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.
Version-changes: 2
- use imply instead of select
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The MACRO has been update after:
ee14d29 rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
We need to update the C code for it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
These imports are entirely unused in the entire script.
Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org>
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Disable rk_timer as SYS timer and use DM timer instead,
so that we can get a better timer framework, the rk_timer
is going to be clean after we conver to use DM timer or
ARM arch/generic timer.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add dts node for timer3.
Because of the rockchip timer can only KNOWN "dtd_rockchip_rk3368_timer"
with OF_PLATDATA enable, so we override its compatible to
"rockchip,rk3368-timer".
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
We should a -u-boot.dtsi for those config need by U-Boot only,
and other part sync with kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Now that the SD/eMMC driver does not use the clock driver in SPL,
remove u-boot,dm-pre-reloc properties to let the fdtgrep tool drop
the unnecessary nodes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There is no need to use zynq name as SYS_BOARD for all boards.
The patch is adding an option to change it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.
Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.
This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f9)
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The E2 Silk port was broken since some time. This patch updates
the E2 Silk port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---
NOTE: The port is missing support for I2C1 for DA9063 reset, since the
I2C driver needs to be converted to DM and DT probing. That's not
an issue for this patch though, since the reset was broken on Silk
since forever.
The M2 Koelsch port was broken since some time. This patch updates
the M2 Koelsch port to use modern frameworks, DM, DT probing, SPL
for the preloading and puts it on par with the M2 Porter board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add all the appropriate i2c alias in the base socfpga dtsi and enables
the i2c node on the DE0 NANO board.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Enable the RPC QSPI driver on R8A77970 V3M Eagle and configure
the environment layout to match that used by old U-Boot.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add device tree nodes for the Renesas RPC HF/QSPI controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Each imx image is created by a separate sub-make and during this process
the mkimage config file is run though cpp.
The cpp output is to the same file no matter what imx image is being
created.
This means if two imx images are generated in parallel they will attempt
to independently produce the same pre-processed mkimage config file at
the same time.
Avoid the problem by making the pre-processed config file name unique
based on the imx image it will be used in. This way each image will
create a unique config file and they won't clobber each other when run
in parallel.
This should fixed the build bug referenced in b5b0e4e3 ("imximage:
Remove failure when no IVT offset is found").
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Working with HAB on the i.MX7 we've encountered a case where a board that
successfully authenticates u-boot when booting Linux via OPTEE subsequently
fails to properly bring up the RTC.
The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.
The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero. In ordinary
circumstances this is OK since we typically do not run in TZ mode, however
when we boot via HAB and enablng TrustZone, it is required to set
HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have
sufficient permissions to manipulate the SNVS-LP block.
On our reference board it is the difference between Linux doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered
30370000.snvs:snvs-rtc-lp as rtc0
snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864)
and doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110
snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110
hctosys: unable to open rtc device (rtc0)
Note bit 1 of LPCR is not set in the second case and is set in the first
case and that bit 31 of HPCOMR is set in the second case but not in the
first.
Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone
and continue onto the kernel. The kernel then has the necessary permissions
to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in
contrast - in the failing case the non-privileged kernel cannot do so.
This patch adds a simple init_snvs() call which sets the permission-bit
called from soc.c for the i.MX7. It may be possible, safe and desirable to
perform this on other i.MX processors but for now this is only tested on
i.MX7 as working.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
This patch adds hab_auth_img_or_fail() a command line function that
encapsulates a common usage of authenticate and failover, namely if
authenticate image fails, then drop to BootROM USB recovery mode.
For secure-boot systems, this type of locked down behavior is important to
ensure no unsigned images can be run.
It's possible to script this logic but, when done over and over again the
environment starts get very complex and repetitive, reducing that script
repetition down to a command line function makes sense.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Breno Lima <breno.lima@nxp.com>
The tester registers provide a unique chip-level identifier which
get_board_serial() returns in a "struct tag_serialnr".
This patch documents the properties of the registers; in summary.
31:0 OCOTP_TESTER0 (most significant)
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
OCOTP_TESTER1 (least significant)
31:24
- The X-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
ID
23:16
- The Y-coordinate of the die location on the wafer/SJC CHALLENGE/ Unique
ID
15:11
- The wafer number of the wafer on which the device was fabricated/SJC
CHALLENGE/ Unique ID
10:0
- FSL-wide unique, encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
The 64 bits of data generate a unique serial number per-chip.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Currently when we define CONFIG_SERIAL_TAG we will barf with a failure to
define "struct tag_serialnr".
This structure is defined in <asm/setup.h>, this patch includes
<asm/setup.h> to fix.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
When the DDR calibration is enabled, a situation may happen that it
will fail on a few select boards out of a whole production lot. In
particular, after the first write leveling stage, the MPWLDECTRLx
registers will contain a value 0x1nn , for nn usually being 0x7f or
slightly lower.
What this means is that the HW write leveling detected that the DQS
rising edge on one or more bundles arrives slightly _after_ CLK and
therefore when the DDR DRAM samples CLK on the DQS rising edge, the
CLK signal is already high (cfr. AN4467 rev2 Figure 7 on page 18).
The HW write leveling then ends up adding almost an entire cycle (thus
the 0x17f) to the DQS delay, which indeed aligns it, but also triggers
subsequent calibration failure in DQS gating due to this massive offset.
There are two observations here:
- If the MPWLDECTRLx value is corrected from 0x17f to 0x0 , then the
DQS gating passes, the entire calibration passes as well and the
DRAM is perfectly stable even under massive load.
- When using the NXP DRAM calibrator for iMX6/7, the value 0x17f or so
in MPWLDECTRx register is not there, but it is replaced by 0x0 as one
would expect.
Someone from NXP finally explains why, quoting [1]:
"
Having said all that, the DDR Stress Test does something that we
do not advertise to the users. The Stress Test iself looks at the
values of the MPWLDECTRL0/1 fields before reporting results, and
if it sees any filed with a value greater than 200/256 delay
(reported as half-cycle = 0x1 and ABS_OFFSET > 0x48), the DDR
Stress test will reset the Write Leveling delay for this lane
to 0x000 and not report it in the log.
The reason that the DDR Stress test does this is because a delay
of more than 78% a clock cycle means that the DQS edge is arriving
within the JEDEC tolerence of 25% of the clock edge. In most cases,
DQS is arriving < 5% tCK of the SDCLK edge in the early case, and
it does not make sense to delay the DQS strobe almost a full clock
cycle and add extra latency to each Write burst just to make the
two edges align exactly. In this case, we are guilty of making a
decision for the customer without telling them we are doing it so
that we don't have to provide the above explanation to every customer.
They don't need to know it.
"
This patch adds the correction described above, that is if the MPWLDECTRx
value is over 0x148, the value is corrected back to 0x0.
[1] https://community.nxp.com/thread/456246
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
There is currently no use for building the SPL anymore, since the
SPI loader can easily be replaced by TPL and TPL does load U-Boot
directly. Upgrade TPL to SPL and replace what used to be SPL with
it. This way we build the U-Boot sources only twice, not thrice.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Shrink the TPL by using tiny printf and tiny memset by default.
This removes the biggest symbol -- vsnprintf_internal -- from
the TPL and reduces the text segment by about 2 kiB.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The H2 Stout port was broken since some time. This patch updates
the H2 Stout port to use modern frameworks, DM, DT probing, SPL
and TPL for the preloading and puts it on par with the M2 Porter
board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The H2 Stout uses SCIFA0 for serial console, make sure it is
available very early on when probing from DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Without armv8_setup_psci register VBAR_EL3 is not set up property which
makes SMC calls jump to invalid location.
smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
Without this they will never pursue booting process.
Fix was applied to the two ways of booting VxWorks: bootvx and bootm commands.
This implementation is very similar to what is done in boot_jump_linux
in arch/arm/lib/bootm.c file.
Tested on VxWorks 7 release SR0520 2017-12-08 Intel Stratix 10 SX SoC
Development Kit board.
Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@globallogic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix up the memory map on Gen3 to match datasheet properly.
This simplifies the memory map setup as well, since we do
no longer need this massive complexity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add JTAG recovery support into the M2 Porter TPL. This allows the
TPL to be loaded over JTAG, initialize the system, wait for the
JTAG debugger to load U-Boot image into RAM and then resume and
start U-Boot from RAM.
The procedure is as follows:
1) Load u-boot-tpl.bin to 0xe6300000
2) Write magic number 0x1337c0de to 0xe6300020
TPL checks for this particular magic and starts JTAG recovery
if this number is present. This is not present by default.
3) Start U-Boot TPL from 0xe6300000
4) Wait for a message from TPL on UART indicating JTAG boot:
"JTAG boot detected!"
5) Halt the system in JTAG debugger
6) Load U-Boot image (u-boot.img) to 0x4fffffc0
7) Write magic number 0xb33fc0de to 0xe6300024
TPL checks for this particular magic to verify that the U-Boot
image was loaded into DRAM by the JTAG debugger.
8) Resume the system in JTAG debugger
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due
to the Gen2 BootROM restriction. The TPL is running from MERAM and
is capable of performing the initial initialization of PFC, Clock,
GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up
the DDR DRAM access. The TPL is capable of loading the next stage,
U-Boot, from either SPI NOR or UART as a fallback. If either does
provide a valid U-Boot uImage, the system stops, which allows the
operator to load U-Boot ie. via JTAG and start it manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Skip the cache initialization, which can be done later on in U-Boot
proper, since this interferes with early DRAM initialization in TPL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The tiny variants of memset and memcpy implementations can be
built for TPL as well, check whether a TPL build is in progress
and avoid including the default variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Similarly to ARMV7, on ARMV7M instruction cache memory needs
to be disabled before running linux kernel to avoid kernel to
be stuck.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Highlights this time around:
- Lots of minor spec compliance fixes
- Support full range of GOP BLT commands
- More fine grained error checking
- Network fixes (init, DP)
- Lots of other bug fixes...
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJay2U6AAoJECszeR4D/txgE8UP/A5xHq707fv4CcQez/cZj/KE
Twv4HoSY28by71VWS+SjXXTKkx+XGM/2tLzl6dQCB9V1aFUwtB12zu4mXpplfT8R
K+dJU9PgkPKJzWRvn08JgeuXs1RQnfSgXz5J2pvSnJ4mySMlZKuVRGwHxw7DLFPf
EZOqkd2+NI90fogGFoZ2l/aAzbDssBI45jDmH0KcPO49/+7XRVYJqpg0s7TQYmhY
BeoJ0mAp12Ybpb4E7XDIGKKgCTjOGnftoRmzZyPZPfHPrmVWo2srmtycDbz0f/N0
tEiXIOAo72DzmhL6aPPNJtt1mjXTGU2iavkV74JVqXODCd3bRJxz7TF6R30Nmvfz
WMaKM+69Ahior9YJnGv2GUe8ebThxivWUUCB6HmfRh07sGCes6eV3HfklY5Fnglu
Gw5pRl9+YBOywuUuyMg/yBPpPyA7b1HaTjwhsYWAB+q7htB6JkPhQruMxdiMaQnC
gvOEoguW1XZo4MSudfC/SUOdayGp+KsQiEivi8gUh11uBPA2nj1Bh028Pj7tTET3
J4C527uF/ivKwhx2hUHq2YkkgxHWz0Z98LFG3Xkj3q3fZFRwSEzugik1TswT8z3l
qPxWgwX7Q9dxNYLW4ogvnlXU/09APRg9fVeaXxOfqJTHCCn9PHehbKKpkJ9g3cOt
lPr1Q/4C5daK8dnxDzYo
=fzbe
-----END PGP SIGNATURE-----
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-04-09
Highlights this time around:
- Lots of minor spec compliance fixes
- Support full range of GOP BLT commands
- More fine grained error checking
- Network fixes (init, DP)
- Lots of other bug fixes...
Add support for zc12xx boards. All of them are internal boards for
silicon validation and share very similar base platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This part hasn't been pushed to mainline yet that's why remove it.
The patch can be reverted in future when this is pushed there.
Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
This part hasn't been pushed to mainline yet that's why remove it.
The patch can be reverted in future when this is pushed there.
Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Latest xilfpga expects to set BIT5 of flags for nonsecure
bitsream and also expects length in bytes instead of words
This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The patch fixing issues reported by DTC:
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have
leading "0x"
zynq-cc108.dtb: Warning (unit_address_format): Node
/amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have
leading "0x"
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Using different node name and label partitions as data.
Also use latest compatible strings based on mainline review.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Mainline Linux kernel has adopted SPDX header license in a different
format then was used before. This patch is syncing it up.
Also update years in License text and remove Nathalie's email because it
is no longer valid.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sync pcie and lpd_dma nodes with mainline version.
Incorrect locations are causing diff in statistics that's why
synchronizations are needed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Delete devices implemented in PL, stylistic changes.
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
In order that we can use eth_env_* even when CONFIG_NET isn't set, move
these functions to environment code from net code.
This fixes failures such as:
board/ti/am335x/built-in.o: In function `board_late_init':
board/ti/am335x/board.c:752: undefined reference to `eth_env_set_enetaddr'
u-boot/board/ti/am335x/board.c:766: undefined reference to `eth_env_set_enetaddr'
which caters for use cases such as:
commit f411b5cca4 ("board: am335x: Always set eth/eth1addr environment
variable")
when Ethernet is required in Linux, but not U-Boot.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
With U-boot runtime board detect for DTB selection a "default" dtb needs
to be created. This will be used temporarily until the "proper" dtb is
selected.
Also, add -u-boot.dtsi for AM437x SK and IDK to enable I2C for
board detection via DM_I2C.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Add support of sysreset with generic driver "syscon-reboot"
provided by RCC, for U-boot and for SPL.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
No more use static frequency HSI = 64MHz for STGEN clock
but HSE (with higher accurency) by default.
Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency
is provided at boot by BootRom and cp15 cntfrq and modified
during clock tree initialization if needed.
When HSI is no more used by any device, this internal
oscillator can be switched off to reduce consumption.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Manage dynamic value for armv7 arch clock timer,
when CONFIG_SYS_HZ_CLOCK is not defined.
Get frequency from CP15 cntfrq information, initialized for example
by first boot stage, clock driver or by BootRom.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Bootrom loads SPL from SDCARD or eMMC
according BootPin selection.
Then SPL loads U-Boot on the same mmc device
with the following predefined GPT partitioning:
on SDCARD: gpt partitioning
1: SPL
2: SPL#2
3: U-Boot
4: bootable partition
on eMMC:
The 2 boot partitions are used for SPL (2 copy)
boot1: SPL
boot2: SPL#2
The user partition use gpt partitioning
1: U-Boot
2: bootable partition
This patch select the correct SPL partition
(3 for SDCARD on mmc0 and 1 for eMMC on mmc1)
according the BootRom information saved in TAMP register
and based on configuration flasg:
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
=> for BOOT_DEVICE_MMC1 or mmc 0 in U-Boot
- CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 (new)
=> for BOOT_DEVICE_MMC2 or mmc 1 in U-Boot
And the correct boot_targets is selected according the environment
variables boot_device and boot_instance, with preboot command,
to search the bootable partition with kernel on this device
(generic distro support).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
SPL copy BootRom boot mode information
in TAMP register 21.
This TAMP register information is used
after relocation to set 2 env variables
- boot_device
- boot_instance
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add command GPT support
Add EMMC boot support
Add the 2 other SDMMC instances for ED1:
- SDMMC2 = mmc 1, eMMC on the ED1 board
- SDMMC3 = extension connector, deactivated by default
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This inhibits the re-inititialization of DDR during an RTC-only resume. If
this is not done, an L3 NOC error is produced as the DDR gets accessed
before the re-init has time to complete. Tested on AM437x GP EVM.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
[j-keerthy@ti.com Ported to Latest Master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for
am43xx_evm_rtconly_config. Without this DDR is unstable and can become
corrupted after multiple iterations of RTC+DDR mode.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[j-keerthy@ti.com Ported to latest master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Kernel stores information to the RTC_SCRATCH0 and RTC_SCRATCH1 registers
for wakeup from RTC-only mode with DDR in self-refresh. Parse these
registers during SPL boot and jump to the kernel resume vector if the
device is waking up from RTC-only modewith DDR in Self-refresh.
The RTC scratch register layout used is:
SCRATCH0 : bits00-31 : kernel resume address
SCRATCH1 : bits00-15 : RTC magic value used to detect valid config
SCRATCH1 : bits16-31 : board type information populated by bootloader
During the normal boot path the SCRATCH1 : bits16-31 are updated with
the eeprom read board type data. In the rtc_only boot path the rtc
scratchpad register is read and the board type is determined and
correspondingly ddr dpll parameters are set. This is done so as to avoid
costly i2c read to eeprom.
RTC-only +DRR in self-refresh mode support is currently only enabled for
am43xx_evm_rtconly_config.
This is not to be used with epos evm builds.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
[j-keerthy@ti.com Rebased to latest u-boot master branch]
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
AT91 ma5d4evk board uses atmel spi driver, enable DM_SPI to
use dm functionality.
Kept few functions related to non-dm and gpio on board
files for reference and will be remove once code moved
to relevant drivers.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync DTS from Linux and add FDT support for AT91 ma5d4evk board.
usb0, usb1, usb2 and hlcdc_pwm nodes removed, since there is no support it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Sync DTS from Linux and add FDT support for AT91 vinco board.
usb0, usb1, and usb2 nodes removed, since there is no support it.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Enable Driver model for AT91 Vinco boards.
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Enable DM_SPI for atmel SPI driver on taurus board.
Kept few functions related to non-dm and gpio on board
files for reference and will be remove once code moved
to relevant drivers.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Highlights this time around:
- Support for new RPi3 B+ model
- Fix for some SD cards on newer RPi firmware
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJaxzkSAAoJECszeR4D/txg8LsQALXv0VwSROVMeneJn98ItB8I
J2bF4vnGlGw3tdekogwOSh+lZ1MgNAM/nmu3qHVfJ1cnytMfAYtZaTL1FhD9gRxQ
OnZFiYFpqX4j1yER6RFf403dnYAUw8S595kOzCy6zeArFuHQ+Ilxl+68PaYnktq/
ICKnGDyv6zYz9WHACOqPcXRSIXEbbmGNW1krqeqGlOkoJiqWvKiET1PCL6qdz2UK
MurM21XOwbTbDlcFmcie+UjBWliCLBGsJx6riPqvM75bkz5ex3yqhGOlWvqiAKvq
Dt0ZTF4PIqXPmmMm5JLnMIFCLKPTS+W+ZwY+a1VyYXWhJXmo2UhOJI4ap5lsn1MR
rinu+oNBC4FAIVhFEk/itGf1p1Diuuwxur4NsJKtLZqeIA1RqGqVSMipia0Wa+K9
hhamltQoHQ7jNnjSEj0iRT11uTrwLxSKaqfbRtvTaovkF0r5pAJU3qJvTgea72lG
3eUSfUOnVv8ez8Oy/B/sEK9/hKhZnKN1pM6jr7HVaWXy2XdqSMlTr9wZndDYKHtA
FQSrjRMet1X8nZWDFGrS8AocFQ8AwGYZL7NBh7Gu8EphFAm0lF0UovkNpqdxnuOx
buVDkfAKYwS9+GI3GPs8zIKz4aI4UD5pZmybHyQk3NjKXS1YrTEeeDYEVPBRWgC0
3aXQ7FPcUyfdrIyAPByZ
=jqq6
-----END PGP SIGNATURE-----
Merge tag 'signed-rpi-next' of git://github.com/agraf/u-boot
Patch queue for rpi - 2018-04-06
Highlights this time around:
- Support for new RPi3 B+ model
- Fix for some SD cards on newer RPi firmware
If an exception occurs in a UEFI loaded image we need the start address of
the image to determine the relocation offset.
This patch adds the necessary lines after the registers in the crash dump.
A possible output would be:
UEFI image [0xbffe6000:0xbffe631f] pc=0x138 '/\snp.efi'
With the offset 0x138 we can now find the relevant instruction in the
disassembled 'snp.efi' binary.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
In raspberrypi-firmware 7fdcd00e00a42a1c91e8bd6f5eb8352fe9358557 and
later start.elf now sets the EMMC clock to 200 MHz.
According to Phil Elwell in
https://github.com/raspberrypi/firmware/issues/953
the SDHost controller shares the core/VPU clock and doesn't use
the EMMC clock.
Use the core clock id when determining the frequency to allow
U-Boot to work with recent versions of raspberrypi-firmware.
Otherwise U-Boot hangs at:
U-Boot 2018.03 (Mar 14 2018 - 20:36:00 +1100)
DRAM: 948 MiB
RPI 3 Model B (0xa02082)
MMC: mmc@7e202000: 0, sdhci@7e300000: 1
Loading Environment from FAT...
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the
EFI service ResetSystem. The missing definition is added. The value has to
handled in efi_reset_system().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
efi_reset_system_init provides the architecture or board specific
initialization of the EFI subsystem. Errors should be caught and
signalled by a return code.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
OrangePi PC2 over to the new bindings used by the kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used by the
various H3 boards over to the new bindings used by the kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
The U-Boot driver for the sun8i-emac was using some preliminary DT
binding. Now since Linux got its own driver in v4.15 and our driver
can now cope with both bindings, let's convert the DT nodes used for the
Pine64+ board over to the new bindings used by the kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Let the Nintendo NES Classic use the Macronix NAND chip on it.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This patch enabled PCIe port on both devel-board
and espressobin board.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch added a new region of 32MiB AT 0xe800.0000
to Armada37x0's memory map. This region is supposed to
be mapped in MMU in order to enable the access to the
PCI I/O or MEM resources.
Signed-off-by: Wilson Ding <dingwei@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38724
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Victor Gu <xigu@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has
added new pinctrl nodes.
This reverts commit f7cab0f95b.
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch corrects below mpp definitions for armada 3720 DB board
and ESPRESSOBin board:
- "smi" pins group is added and "smi" function is set for eth0;
- Now pcie pins are used as gpio to implement PCIe function in
hardware, so "pcie" group function is changed to "gpio".
Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43286
Reviewed-by: Hua Jing <jinghua@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add mmc pins, pcie pins and sdio pins definition and do these pins'
configuration for DB board and espressobin board;
Add uart2 pins configuration for DB board.
Reviewed-on: http://vgitil04.il.marvell.com:8080/40914
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913
Reviewed-by: Wilson Ding <dingwei@marvell.com>
Tested-by: Wilson Ding <dingwei@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Similarly to imx6, before reading the boot device, first check
bmode to see if the serial downloader has been selected
explicitly, then check whether the serial downloader has been
activated due to unbootable primary boot devices (e.g. empty eMMC).
If the serial downloader is activated, return BOOT_DEVICE_BOARD.
This allows SPL with SDP support to wait for the U-Boot image
to be loaded via the serial download protocol using imx_usb_loader.
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
The i.MX6ULL has a WDOG3 located at start address 0x021E0000 in the
AIPS-2 memory region [1].
[1] i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017,
Table 2-3. AIPS-2 memory map, p. 178
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
The i.MX6UL has a WDOG3 located at start address 0x021E0000 in the
AIPS-2 memory region [1].
[1] i.MX 6UltraLite Applications Processor Reference Manual, Rev. 1,
04/2016, Table-2-3 AIPS-2 memory map, p. 166
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
HW accelerated "hash sha256 ..." command doesn't work on i.MX6UL, we get
"CAAM was not setup properly or it is faulty" error message.
This is due to wrong CAAM base 0x02100000, on i.MX6UL the CAAM base
address is 0x02140000. Fix it.
Note: with this patch applied the "hash sha256" commant still has some
issues on i.MX6UL ("Invalid KEY Command" or other errors). With data
cache off the "hash sha256" command works as expected.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
NXP layerscape platforms like ls1088a, ls2088a
uses MXC I2C Controller.
-Remove dependency of MX6 for the same.
Update related configs to use Kconfig file.
-Add SYS_I2C_MXC_I2C1,_I2C2,_I2C3,_I2C4 in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SPEED,_I2C2_,_I2C3_,_I2C4_ in Kconfig
-Add CONFIG_SYS_MXC_I2C1_SLAVE,_I2C2_,_I2C3_,_I2C4_ in Kconfig
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Clean the iomux definitions at grf_rk3188.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Clean the iomux definitions at grf_rk3036.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This adds support for the (to date unsupported) I2C controllers 1~4
and 6~7 (i.e. now all controllers except I2C5, which is not accessible
on the RK3399-Q7, are supported by pinctrl).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The shift values for GPIO2B1 and GPIO2B2 had in fact referred to
GPIO2B0 and GPIO2B1, respectively. This substitutes the correct
values.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Watchdog is only enabled in full u-boot. Adoption for SPL should be also
done because that's the right place where watchdog should be enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As of now newer pmufw is keeping old interfaces. That's why permit
u-boot to run on newer version. Recommended version will be setup later.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sync dts from Linux 4.16 and also add u-boot specific
dtsi for OMAPl138 board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for
SOC_DA8XX, which broke OMAPL138 to boot.
Commit 2e87980580 ("davinci: Fix omapl138_lcdk builds") disabled
DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot
as ddr is not being initialized.
Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138
will have ddr initialized
Fixes: 2e87980580 ("davinci: Fix omapl138_lcdk builds")
Fixes: 6aa4ad8e38 ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
Reported-by: Sekhar Nori <nsekhar@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable all types of non-secure access to PFE block registers.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
IFC-NOR and QSPI-NOR pins are multiplexed on SoC, so they cannot be
accessed simultaneously. IFC-NOR can be accessed along with SD-BOOT.
Ls1088aqds_sdcard_ifc_defconfig is default config for SD boot and
IFC-NOR to be used as flash. This allows writing to IFC-NOR flash.
QSPI and DSPI cannot be accessed in this defconfig.
IFC-NOR image is generated using ls1088aqds_defconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add first support for STM32MP157C-ED1 board with "Basic" boot chain
1/ Boot Rom: load SPL with STM32 image header in SYSRAM
2/ SPL: power up and initialize the DDR and load U-Boot image
from SDCARD in DDR
3/ U-Boot: search and load extlinux.conf in SDCARD
(DISTRO activated)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard
Waiting Kernel upstream for alignment.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
- add new arch stm32mp for STM32 MPU/Soc based on Cortex A
- support for stm32mp157 SOC
- SPL is used as first boot stage loader
- using driver model for all the drivers, even in SPL
- all security feature are deactivated (ETZC and TZC)
- reused STM32 MCU drivers when it is possible
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
The current value timer_rate_hz causes a problem with function
timer_get_us() from lib time and then an issue with
readx_poll_timeout() function.
With corrected value for tbclk() = timer_rate_hz = CONFIG_SYS_HZ_CLOCK
the weak functions in lib timer can be used:
- get_timer()
- __udelay()
So the specific function in this file are removed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add proper and simple kconfig option for dram_sun8i_a83t.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun8i_a33.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun8i_a23.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun9i.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun4i.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add proper and simple kconfig option for dram_sun6i.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add simple and meaningful kconfig option for pmic_bus.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add simple and meaningful kconfig option for rsb.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
SUN6I_PRCM is also used for SUN8I and SUN9I, so
select the same on respective MACH types.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add simple and meaningful kconfig option for p2wi.c
instead of using MACH type on Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Add simple and meaningful kconfig option for prcm.c
instead of using MACH type on Makefile.
PRCM (Power/Reset/Clock Management) is considered as a
Multi-Functional Device, so used the same on Kconfig definition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Enable the display controller, panel & backlight.
Set panel display timings & set the RGB data bus.
Signed-off-by: yannick fertre <yannick.fertre@st.com>
This converts the following to Kconfig:
CONFIG_CONS_INDEX
We have existing entries for this option in a number of places, with
different guards on them. They're also sometimes used for things not
directly inside of the serial driver. First, introduce a new symbol to
guard the use of CONFIG_CONS_INDEX, so that in the case where we don't
need this for the serial driver, but for some other use, we can still do
it. Next, consolidate all of these into the single entry in
drivers/serial/Kconfig. Finally, introduce CONS_INDEX_[023456] so that
we can imply a correct value here to make the defconfig side of this
smaller.
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rework a lot of the logic here, such that I took authorship from
Adam, but kept his S-o-B line]
Signed-off-by: Tom Rini <trini@konsulko.com>
Add USB clock driver to configure the input clock and the divider
in the PMC_USB register to generate a 48MHz and a 12MHz signal to
the USB Host OHCI.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
When enabling CONFIG_FASTBOOT_FLASH in am335x_boneblack_defconfig, next
build errors and warnings occur:
arch/arm/mach-omap2/utils.c: In function ‘omap_set_fastboot_cpu’:
arch/arm/mach-omap2/utils.c:26:16: warning: implicit declaration of
function ‘omap_revision’ [-Wimplicit-function-declaration]
u32 cpu_rev = omap_revision();
^~~~~~~~~~~~~
arch/arm/mach-omap2/utils.c:29:7: error: ‘DRA762_ES1_0’ undeclared
(first use in this function)
Include asm/omap_common.h explicitly to avoid those.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SPL can't use high speed MMC modes if the associated pinctrl and
IOdelays are described in the DTS.
Make them available in SPL by tagging the nodes with 'u-boot,dm-spl;'
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Now that we have a device-tree include file with common
MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree
file to using that.
Also fix the name of the IO voltage regulator for mmc1.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add a common device-tree include file with MMC/SD IOdelay data
for DRA76x SoC based on the linux DTSI file.
In the most common case, IOdelay data available in datamanual
can directly be used. This file caters to that common case.
Data is based on DRA76x datamanual, SPRS993A, revised July 2017.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
On linux kernel side, on STM32F7 and STM32H7 SoCs, DMA requires
uncachable regions. These regions are defined in DT.
Since kernel linux v4.15, on ARMv7-M Cortex, kernel is able
to configure MPU regions depending on DT settings.
As kernel is able to configure MPU, this allows to remove
MPU region settings in bootloader.
On Cortex M processors, MPU allows to use a default memory map.
(see B3.5.4 MPU Control Register, MPU_CTRL in
https://developer.arm.com/products/architecture/m-profile/docs/ddi0403/latest/armv7-m-architecture-reference-manual)
Use the default memory map as background region for all STM32 SoCs
family with an additional MPU region corresponding to the SDRAM area.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This board offers:
_ STM32F746NGH6 microcontroller with 1 Mbyte Flash and 320+4 Kbytes RAM
_ Six 5 V power supply options:
Power jack
ST-LINK/V2-1 USB connector
User USB HS connector
User USB FS1 connector
User USB FS2 connector
Daughterboard
_ SAI Audio DAC, stereo audio jack which supports headset with microphone
_ Stereo digital microphone, audio jack connector used to connect
external speakers
_ 2 Gbytes (or more) SDMMC interface microSD card
_ RF-EEPROM on I2C compatible serial interface
_ RS-232 communication
_ IrDA transceiver
_ JTAG/SWD and ETM trace debug support, ST-LINK/V2-1 embedded
_ IEEE-802.3-2002 compliant Ethernet connector
_ Camera module
_ 8Mx32 bit SDRAM, 1Mx16 bit SRAM & 8Mx16 bit Nor Flash
_ 512 Mbits QuadSPI Nor Flash
_ 5.7 inch 640x480 pixel TFT color LCD with capacitive touch panel
_ Joystick with 4-direction control and selector
_ Reset, WakeUp/Tamper or key button
_ 4 color user LEDs
_ Extension connectors & memory connectors for daughterboard or
wrapping board
_ USB OTG HS and FS with Micro-AB connectors
_ RTC with backup battery
_ CAN 2.0A/B compliant connection
_ Potentiometer
_ Motor control connector
More detailed information are available here :
http://www.st.com/en/evaluation-tools/stm32746g-eval.html
To compile stm32f746-eval board, use same defconfig as
stm32f746-disco, the only difference is to pass
"DEVICE_TREE=stm32746g-eval".
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
Remove arch/arm/include/asm/arch-stm32fx/stm32_periph.h
as all defines or enums are no more used.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
Some common defines are duplicated or even unused in each of
these stm32.h.
Factorize all common definition in arch/arm/include/asm/stm32f.h and keep
specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Instead to have 3 identical gpio.h for all STM32 SoCs,
migrate them in one file in include/asm.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
fmc.h file is no more used, remove it.
All FMC related defines are declared in drivers/ram/stm32_sdram.c
which is common to all STM32 SoCs.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This avoids the following errors while reading on mmc:
Read data bytes CRC error: 0x2
switch to partitions #0, OK
mmc0 is current device
Read data bytes CRC error: 0x82002
** Unrecognized filesystem type **
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.
Remove all defines or files previously used for timer usage in
arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx
Enable DM STM32_TIMER for STM32F4/F7 and H7.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
RK3288 Vyasa has eMMC boot support, with JP4 open.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add usb otg support for rk3288-vyasa, board support usb1 otg
power through otg_vbus_drv and naming conversion followed
as per schematic.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add usb host support for rk3288-vyasa, board support hub power
through phy_pwr_en and usb2 host power through usb2_pwr_en and
naming conversion followed as per schematic.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sync gmac dts node from Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add supporting regulators for rk3288-vyasa board, dc12_vbat is
parent regulatorand followed regulators as are child regulators.
regulator naming conversion followed as per schematic for better
readability and easy for identification.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
rk808, SWITCH_REG1 has configured for sdmmc regulator as vcc_sd,
so use the same by renaming vcc33_sd to vcc_sd(as per schematic)
and drop explicit regulator definition from root.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
vdd_log, never used on DCDC_REG1 of rk808 from latest schematic so
remove the same and update the regulator-name as 'vdd_arm' to sync
with existing rk3288 board dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sync rk3288-vyasa board dts from Linux for proper updates and maintenance
- rk3288-vyasa.dts: Similar to Linux dts
- rk3288-vyasa-u-boot.dtsi: u-boot dts changes
Also updated MAINTAINERS for these dts files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
A20-SOM204 board has option with onboard 16GB eMMC. The chip is wired
to MMC2 slot.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
This is new System-On-Module platform with universal dimm socket for
easy insertation. The EVB board is designed to be universal with
future modules.
Base features of A20-SOM204 board includes:
* 1GB DDR3 RAM
* AXP209 PMU
* KSZ9031 Gigabit PHY
* AT24C16 EEPROM
* Status LED
* LCD connector
* GPIO connector
There will be variants with the following options:
* Second LAN8710A Megabit PHY
* 16MB SPI Flash memory
* eMMC card
* ATECC508 crypto device
The EVB board has:
* Debug UART
* MicroSD card connector
* USB-OTG connector
* Two USB host
* RTL8723BS WiFi/BT combo
* IrDA transceiver/receiver
* HDMI connector
* VGA connector
* Megabit ethernet transceiver
* Gigabit ethernet transceiver
* SATA connector
* CAN driver
* CSI camera
* MIC and HP connectors
* PCIe x4 connector
* USB3 connector
* Two UEXT connectors
* Two user LEDs
Some of the features are multiplexed and cannot be used the same time:
CAN and Megabit PHY. Others are not usable with A20 SoC: PCIe and USB3.
This patch adds defconfig and dts files for this board. The dts is same
with mainline kernel, except some nodes are removed to make file
compatible with existing dtsi file.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
We're going to need this logic for 64-bit builds as well, so move it
out from under arch/arm/cpu/armv7.
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
When the OTG node was added, its reg property for its address space was
missing. With commit f4f9896ac3 ("musb: sunxi: Use base address from
device tree"), the OTG controller's address is derived from the device
tree exclusively. The missing property results in U-boot crashing when
MUSB is initialized.
Fixes: b0bea66789 ("sunxi: Add USB and R_PIO nodes to sun8i-a83t.dtsi")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@openedev.com>
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.
And also renamed the file according to kconfig which resembles
proper name.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
commit 8c4037a09a ("imx: hab: Ensure the IVT DCD pointer is Null prior
to calling HAB authenticate function.") makes the DCD field being NULL a
dependency.
This change though will break loading and executing of existing pre-signed
binaries on a u-boot update i.e. if this change is deployed on a board you
will be forced to redo all images on that board to NULL out the DCD.
There is no prior guidance from NXP that the DCD must be NULL similarly
public guidance on usage of the HAB doesn't call out this NULL dependency
(see boundary devices link).
Since later SoCs will reject a non-NULL DCD there's no reason to make a
NULL DCD a requirement, however if there is an actual dependency for later
SoCs the appropriate fix would be to do SoC version checking.
Earlier SoCs are capable (and happy) to authenticate images with non-NULL
DCDs, we should not be forcing this change on downstream users -
particularly if it means those users now must rewrite their build systems
and/or redeploy signed images in the field.
Fixes: 8c4037a09a ("imx: hab: Ensure the IVT DCD pointer is Null prior
to calling HAB authenticate function.")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Link: https://boundarydevices.com/high-assurance-boot-hab-dummies
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
commit ed286bc80e ("imx: hab: Check if CSF is valid before authenticating
image") makes use of "__packed" as a prefix to the "struct hab_hdr"
declaration.
With my compiler "gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)" we
get:
./arch/arm/include/asm/mach-imx/hab.h:42:25: error: expected ‘=’, ‘,’, ‘;’,
‘asm’ or ‘__attribute__’ before ‘{’ token
struct __packed hab_hdr {
Fix this problem by including <linux/compiler.h>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Cc: Utkarsh Gupta <utkarsh.gupta@nxp.com>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This patch fixes the wrongly included dtsi file which was
breaking mainline support for Engicam i.CoreM6 DualLite/Solo RQS.
Linux commit details for the same change as
"ARM: dts: imx6dl: Include correct dtsi file for Engicam i.CoreM6
DualLite/Solo RQS"
(sha1: c0c6bb2322964bd264b4ddedaa5776f40c709f0c)
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
usdhc4 node need to update pinctrl, bus-width and non-removable
properties, sync the same from Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Without the volatile attribute, compilers are entitled to optimize out
the same asm(). In the case of __udelay() in syscounter.c, it calls
`get_ticks()` twice, one for the starting time and the second in the
loop to check the current time. When compilers inline `get_ticks()`
they see the same `mrrc` instructions and optimize out the second one.
This leads to infinite loop since we don't get updated value from the
system counter.
Here is a portion of the disassembly of __udelay:
88: 428b cmp r3, r1
8a: f8ce 20a4 str.w r2, [lr, #164] ; 0xa4
8e: bf08 it eq
90: 4282 cmpeq r2, r0
92: f8ce 30a0 str.w r3, [lr, #160] ; 0xa0
96: d3f7 bcc.n 88 <__udelay+0x88>
98: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
Note that final jump / loop at 96 to 88, we don't have any `mrrc`.
With a volatile attribute, the above changes to this:
8a: ec53 2f0e mrrc 15, 0, r2, r3, cr14
8e: 42ab cmp r3, r5
90: f8c1 20a4 str.w r2, [r1, #164] ; 0xa4
94: bf08 it eq
96: 42a2 cmpeq r2, r4
98: f8c1 30a0 str.w r3, [r1, #160] ; 0xa0
9c: d3f5 bcc.n 8a <__udelay+0x8a>
9e: e8bd 8cf0 ldmia.w sp!, {r4, r5, r6, r7, sl, fp, pc}
a2: bf00 nop
I'm advised[1] to put volatile on all asm(), so this commit also adds it
to the asm() in timer_init().
[1]: https://lists.denx.de/pipermail/u-boot/2018-March/322062.html
Signed-off-by: Yasushi SHOJI <yasushi.shoji@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.
This commit moves the header code:
include/libfdt.h -> include/linux/libfdt.h
include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives:
#include <libfdt.h> -> #include <linux/libfdt.h>
#include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Rename CONFIG_SPL_USBETH_SUPPORT to CONFIG_SPL_USB_ETHER.
This enables users to block text using CONFIG_IS_ENABLED() instead
of resorting to #if ladders with SPL and non-SPL cases.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
This patch got dropped during the update of DTs to 4.14, re-add it
back. This adds reset GPIOs to the ethernet PHYs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
These do not need to be available early on Gen3 , so move them to
the respective DT files.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add R8A77965 M3N Salvator-XS development kit support. This kit is
similar to the other Salvator-X(S) ones, except is has M3N SoC on
it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
