dts: add device tree for STM32MP157C-ED1 board

Add minimal devicetree for STM32MP157C-ED1 board,
with only the devices to allow boot from SDCARD:
- RCC for clock and reset
- UART4 for console
- I2C and PMIC
- DDR
- SDMMC0 for SDCard

Waiting Kernel upstream for alignment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2018-03-12 10:46:17 +01:00 committed by Tom Rini
parent 266fa4df00
commit 3d2d115a30
9 changed files with 1357 additions and 0 deletions

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@ -500,6 +500,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ed1.dtb
targets += $(dtb-y)
# Add any required device tree compiler flags here

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@ -0,0 +1,155 @@
/*
* Copyright : STMicroelectronics 2018
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
/ {
soc {
ddr: ddr@0x5A003000{
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
clocks = <&rcc_clk AXIDCG>,
<&rcc_clk DDRC1>,
<&rcc_clk DDRC2>,
<&rcc_clk DDRPHYC>,
<&rcc_clk DDRCAPB>,
<&rcc_clk DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
st,mem-name = DDR_MEM_NAME;
st,mem-speed = <DDR_MEM_SPEED>;
st,mem-size = <DDR_MEM_SIZE>;
st,ctl-reg = <
DDR_MSTR
DDR_MRCTRL0
DDR_MRCTRL1
DDR_DERATEEN
DDR_DERATEINT
DDR_PWRCTL
DDR_PWRTMG
DDR_HWLPCTL
DDR_RFSHCTL0
DDR_RFSHCTL3
DDR_CRCPARCTL0
DDR_ZQCTL0
DDR_DFITMG0
DDR_DFITMG1
DDR_DFILPCFG0
DDR_DFIUPD0
DDR_DFIUPD1
DDR_DFIUPD2
DDR_DFIPHYMSTR
DDR_ODTMAP
DDR_DBG0
DDR_DBG1
DDR_DBGCMD
DDR_POISONCFG
DDR_PCCFG
>;
st,ctl-timing = <
DDR_RFSHTMG
DDR_DRAMTMG0
DDR_DRAMTMG1
DDR_DRAMTMG2
DDR_DRAMTMG3
DDR_DRAMTMG4
DDR_DRAMTMG5
DDR_DRAMTMG6
DDR_DRAMTMG7
DDR_DRAMTMG8
DDR_DRAMTMG14
DDR_ODTCFG
>;
st,ctl-map = <
DDR_ADDRMAP1
DDR_ADDRMAP2
DDR_ADDRMAP3
DDR_ADDRMAP4
DDR_ADDRMAP5
DDR_ADDRMAP6
DDR_ADDRMAP9
DDR_ADDRMAP10
DDR_ADDRMAP11
>;
st,ctl-perf = <
DDR_SCHED
DDR_SCHED1
DDR_PERFHPR1
DDR_PERFLPR1
DDR_PERFWR1
DDR_PCFGR_0
DDR_PCFGW_0
DDR_PCFGQOS0_0
DDR_PCFGQOS1_0
DDR_PCFGWQOS0_0
DDR_PCFGWQOS1_0
DDR_PCFGR_1
DDR_PCFGW_1
DDR_PCFGQOS0_1
DDR_PCFGQOS1_1
DDR_PCFGWQOS0_1
DDR_PCFGWQOS1_1
>;
st,phy-reg = <
DDR_PGCR
DDR_ACIOCR
DDR_DXCCR
DDR_DSGCR
DDR_DCR
DDR_ODTCR
DDR_ZQ0CR1
DDR_DX0GCR
DDR_DX1GCR
DDR_DX2GCR
DDR_DX3GCR
>;
st,phy-timing = <
DDR_PTR0
DDR_PTR1
DDR_PTR2
DDR_DTPR0
DDR_DTPR1
DDR_DTPR2
DDR_MR0
DDR_MR1
DDR_MR2
DDR_MR3
>;
st,phy-cal = <
DDR_DX0DLLCR
DDR_DX0DQTR
DDR_DX0DQSTR
DDR_DX1DLLCR
DDR_DX1DQTR
DDR_DX1DQSTR
DDR_DX2DLLCR
DDR_DX2DQTR
DDR_DX2DQSTR
DDR_DX3DLLCR
DDR_DX3DQTR
DDR_DX3DQSTR
>;
status = "okay";
};
};
};

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@ -0,0 +1,122 @@
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
/* STM32MP157C ED1 and ED2 BOARD configuration
* 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
* Reference used NT5CC256M16DP-DI from NANYA
*
* DDR type / Platform DDR3/3L
* freq 533MHz
* width 32
* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
* DDR density 8
* timing mode optimized
* Scheduling/QoS options : type = 2
* address mapping : RBC
*/
#define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36"
#define DDR_MEM_SPEED 533
#define DDR_MEM_SIZE 0x40000000
#define DDR_MSTR 0x00040401
#define DDR_MRCTRL0 0x00000010
#define DDR_MRCTRL1 0x00000000
#define DDR_DERATEEN 0x00000000
#define DDR_DERATEINT 0x00800000
#define DDR_PWRCTL 0x00000000
#define DDR_PWRTMG 0x00400010
#define DDR_HWLPCTL 0x00000000
#define DDR_RFSHCTL0 0x00210000
#define DDR_RFSHCTL3 0x00000000
#define DDR_RFSHTMG 0x0081008B
#define DDR_CRCPARCTL0 0x00000000
#define DDR_DRAMTMG0 0x121B2414
#define DDR_DRAMTMG1 0x000A041C
#define DDR_DRAMTMG2 0x0608090F
#define DDR_DRAMTMG3 0x0050400C
#define DDR_DRAMTMG4 0x08040608
#define DDR_DRAMTMG5 0x06060403
#define DDR_DRAMTMG6 0x02020002
#define DDR_DRAMTMG7 0x00000202
#define DDR_DRAMTMG8 0x00001005
#define DDR_DRAMTMG14 0x000000A0
#define DDR_ZQCTL0 0xC2000040
#define DDR_DFITMG0 0x02060105
#define DDR_DFITMG1 0x00000202
#define DDR_DFILPCFG0 0x07000000
#define DDR_DFIUPD0 0xC0400003
#define DDR_DFIUPD1 0x00000000
#define DDR_DFIUPD2 0x00000000
#define DDR_DFIPHYMSTR 0x00000000
#define DDR_ADDRMAP1 0x00080808
#define DDR_ADDRMAP2 0x00000000
#define DDR_ADDRMAP3 0x00000000
#define DDR_ADDRMAP4 0x00001F1F
#define DDR_ADDRMAP5 0x07070707
#define DDR_ADDRMAP6 0x0F070707
#define DDR_ADDRMAP9 0x00000000
#define DDR_ADDRMAP10 0x00000000
#define DDR_ADDRMAP11 0x00000000
#define DDR_ODTCFG 0x06000600
#define DDR_ODTMAP 0x00000001
#define DDR_SCHED 0x00001201
#define DDR_SCHED1 0x00000000
#define DDR_PERFHPR1 0x01000001
#define DDR_PERFLPR1 0x08000200
#define DDR_PERFWR1 0x08000400
#define DDR_DBG0 0x00000000
#define DDR_DBG1 0x00000000
#define DDR_DBGCMD 0x00000000
#define DDR_POISONCFG 0x00000000
#define DDR_PCCFG 0x00000010
#define DDR_PCFGR_0 0x00010000
#define DDR_PCFGW_0 0x00000000
#define DDR_PCFGQOS0_0 0x02100B03
#define DDR_PCFGQOS1_0 0x00800100
#define DDR_PCFGWQOS0_0 0x01100B03
#define DDR_PCFGWQOS1_0 0x01000200
#define DDR_PCFGR_1 0x00010000
#define DDR_PCFGW_1 0x00000000
#define DDR_PCFGQOS0_1 0x02100B03
#define DDR_PCFGQOS1_1 0x00800100
#define DDR_PCFGWQOS0_1 0x01100B03
#define DDR_PCFGWQOS1_1 0x01000200
#define DDR_PGCR 0x01442E02
#define DDR_PTR0 0x0022AA5B
#define DDR_PTR1 0x04841104
#define DDR_PTR2 0x042DA068
#define DDR_ACIOCR 0x10400812
#define DDR_DXCCR 0x00000C40
#define DDR_DSGCR 0xF200001F
#define DDR_DCR 0x0000000B
#define DDR_DTPR0 0x38D488D0
#define DDR_DTPR1 0x098B00D8
#define DDR_DTPR2 0x10023600
#define DDR_MR0 0x00000840
#define DDR_MR1 0x00000000
#define DDR_MR2 0x00000208
#define DDR_MR3 0x00000000
#define DDR_ODTCR 0x00010000
#define DDR_ZQ0CR1 0x0000005B
#define DDR_DX0GCR 0x0000CE81
#define DDR_DX0DLLCR 0x40000000
#define DDR_DX0DQTR 0xFFFFFFFF
#define DDR_DX0DQSTR 0x3DB02000
#define DDR_DX1GCR 0x0000CE81
#define DDR_DX1DLLCR 0x40000000
#define DDR_DX1DQTR 0xFFFFFFFF
#define DDR_DX1DQSTR 0x3DB02000
#define DDR_DX2GCR 0x0000CE81
#define DDR_DX2DLLCR 0x40000000
#define DDR_DX2DQTR 0xFFFFFFFF
#define DDR_DX2DQSTR 0x3DB02000
#define DDR_DX3GCR 0x0000CE81
#define DDR_DX3DLLCR 0x40000000
#define DDR_DX3DQTR 0xFFFFFFFF
#define DDR_DX3DQSTR 0x3DB02000
#include "stm32mp15-ddr.dtsi"

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@ -0,0 +1,134 @@
/*
* Copyright : STMicroelectronics 2018
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
gpio25 = &gpioz;
};
config {
u-boot,dm-pre-reloc;
};
clocks {
u-boot,dm-pre-reloc;
};
soc {
u-boot,dm-pre-reloc;
};
};
&clk_hsi {
u-boot,dm-pre-reloc;
};
&clk_hse {
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&clk_lsi {
u-boot,dm-pre-reloc;
};
&clk_csi {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
};
&rcc_clk {
u-boot,dm-pre-reloc;
};
&rcc_rst {
u-boot,dm-pre-reloc;
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_z {
u-boot,dm-pre-reloc;
};
&gpioa {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiob {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioc {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiod {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioe {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiof {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiog {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioh {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioi {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioj {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpiok {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};
&gpioz {
compatible = "st,stm32-gpio";
u-boot,dm-pre-reloc;
};

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@ -0,0 +1,303 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset-controller/stm32mp1-resets.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
};
};
aliases {
serial3 = &uart4;
};
intc: interrupt-controller@a0021000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xa0021000 0x1000>,
<0xa0022000 0x2000>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_csi: clk-csi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <4000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
uart4: serial@40010000 {
compatible = "st,stm32h7-uart";
reg = <0x40010000 0x400>;
clocks = <&rcc_clk UART4_K>;
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "syscon", "simple-mfd";
reg = <0x50000000 0x1000>;
rcc_clk: rcc-clk@50000000 {
#clock-cells = <1>;
compatible = "st,stm32mp1-rcc-clk";
};
rcc_rst: rcc-reset@50000000 {
#reset-cells = <1>;
compatible = "st,stm32mp1-rcc-rst";
};
};
pinctrl: pin-controller {
compatible = "st,stm32mp157-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50002000 0xa400>;
pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc_clk GPIOA>;
st,bank-name = "GPIOA";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 0 16>;
status = "disabled";
};
gpiob: gpio@50003000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc_clk GPIOB>;
st,bank-name = "GPIOB";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 16 16>;
status = "disabled";
};
gpioc: gpio@50004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc_clk GPIOC>;
st,bank-name = "GPIOC";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 32 16>;
status = "disabled";
};
gpiod: gpio@50005000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x3000 0x400>;
clocks = <&rcc_clk GPIOD>;
st,bank-name = "GPIOD";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 48 16>;
status = "disabled";
};
gpioe: gpio@50006000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x4000 0x400>;
clocks = <&rcc_clk GPIOE>;
st,bank-name = "GPIOE";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 64 16>;
status = "disabled";
};
gpiof: gpio@50007000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000 0x400>;
clocks = <&rcc_clk GPIOF>;
st,bank-name = "GPIOF";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 80 16>;
status = "disabled";
};
gpiog: gpio@50008000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x6000 0x400>;
clocks = <&rcc_clk GPIOG>;
st,bank-name = "GPIOG";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 96 16>;
status = "disabled";
};
gpioh: gpio@50009000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x7000 0x400>;
clocks = <&rcc_clk GPIOH>;
st,bank-name = "GPIOH";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 112 16>;
status = "disabled";
};
gpioi: gpio@5000a000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x8000 0x400>;
clocks = <&rcc_clk GPIOI>;
st,bank-name = "GPIOI";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 128 16>;
status = "disabled";
};
gpioj: gpio@5000b000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x9000 0x400>;
clocks = <&rcc_clk GPIOJ>;
st,bank-name = "GPIOJ";
ngpios = <16>;
gpio-ranges = <&pinctrl 0 144 16>;
status = "disabled";
};
gpiok: gpio@5000c000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa000 0x400>;
clocks = <&rcc_clk GPIOK>;
st,bank-name = "GPIOK";
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
status = "disabled";
};
};
pinctrl_z: pin-controller-z {
compatible = "st,stm32mp157-z-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x54004000 0x400>;
pins-are-numbered;
gpioz: gpio@54004000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc_clk GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
ngpios = <8>;
gpio-ranges = <&pinctrl_z 0 400 8>;
status = "disabled";
};
};
sdmmc1: sdmmc@58005000 {
compatible = "st,stm32-sdmmc2";
reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
reg-names = "sdmmc", "delay";
clocks = <&rcc_clk SDMMC1_K>;
resets = <&rcc_rst SDMMC1_R>;
st,idma = <1>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
status = "disabled";
};
i2c4: i2c@5c002000 {
compatible = "st,stm32f7-i2c";
reg = <0x5c002000 0x400>;
interrupt-names = "event", "error", "wakeup";
clocks = <&rcc_clk I2C4_K>;
resets = <&rcc_rst I2C4_R>;
#address-cells = <1>;
#size-cells = <0>;
wakeup-source;
status = "disabled";
};
};
};

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@ -0,0 +1,133 @@
/*
* Copyright : STMicroelectronics 2018
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp157-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
i2c3 = &i2c4;
};
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&i2c4 {
u-boot,dm-pre-reloc;
};
&pmic {
u-boot,dm-pre-reloc;
};
/* CLOCK init */
&rcc_clk {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_DISABLED
CLK_SDMMC12_PLL3R
CLK_I2C46_PCLK5
CLK_I2C12_PCLK1
CLK_I2C35_PCLK1
CLK_UART1_PCLK5
CLK_UART24_PCLK1
CLK_UART35_PCLK1
CLK_UART6_PCLK2
CLK_UART78_PCLK1
>;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
pll3: st,pll@2 {
cfg = < 3 128 3 20 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
pll4: st,pll@3 {
cfg = < 5 126 8 8 8 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
/* SPL part **************************************/
/* MMC1 boot */
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc1 {
u-boot,dm-spl;
};

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@ -0,0 +1,167 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
model = "STMicroelectronics STM32MP157C pmic eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
chosen {
bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram";
stdout-path = "serial3:115200n8";
};
memory {
reg = <0xC0000000 0x40000000>;
};
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&gpiof {
status = "okay";
};
&gpiog {
status = "okay";
};
&gpioh {
status = "okay";
};
&gpioi {
status = "okay";
};
&gpioj {
status = "okay";
};
&gpiok {
status = "okay";
};
&gpioz {
status = "okay";
};
&pinctrl {
uart4_pins_a: uart4@0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
bias-disable;
};
};
sdmmc1_b4_pins_a: sdmmc1-b4@0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
slew-rate = <3>;
drive-push-pull;
bias-disable;
};
};
sdmmc1_dir_pins_a: sdmmc1-dir@0 {
pins {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
<STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
<STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
slew-rate = <3>;
drive-push-pull;
bias-pull-up;
};
};
};
&pinctrl_z {
i2c4_pins_a: i2c4@0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
bias-disable;
drive-open-drain;
slew-rate = <0>;
};
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins_a>;
i2c-scl-rising-time-ns = <185>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
pmic: stpmu1@33 {
compatible = "st,stpmu1";
reg = <0x33>;
interrupts = <0 2>;
interrupt-parent = <&gpioa>;
interrupt-controller;
#interrupt-cells = <2>;
status = "okay";
};
};
&sdmmc1 {
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
broken-cd;
st,dirpol;
st,negedge;
st,pin-ckin;
bus-width = <4>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-ddr50;
sd-uhs-sdr104;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins_a>;
status = "okay";
};

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/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
/* OSCILLATOR clocks */
#define CK_HSE 0
#define CK_CSI 1
#define CK_LSI 2
#define CK_LSE 3
#define CK_HSI 4
#define CK_HSE_DIV2 5
/* Bus clocks */
#define TIM2 6
#define TIM3 7
#define TIM4 8
#define TIM5 9
#define TIM6 10
#define TIM7 11
#define TIM12 12
#define TIM13 13
#define TIM14 14
#define LPTIM1 15
#define SPI2 16
#define SPI3 17
#define USART2 18
#define USART3 19
#define UART4 20
#define UART5 21
#define UART7 22
#define UART8 23
#define I2C1 24
#define I2C2 25
#define I2C3 26
#define I2C5 27
#define SPDIF 28
#define CEC 29
#define DAC12 30
#define MDIO 31
#define TIM1 32
#define TIM8 33
#define TIM15 34
#define TIM16 35
#define TIM17 36
#define SPI1 37
#define SPI4 38
#define SPI5 39
#define USART6 40
#define SAI1 41
#define SAI2 42
#define SAI3 43
#define DFSDM 44
#define FDCAN 45
#define LPTIM2 46
#define LPTIM3 47
#define LPTIM4 48
#define LPTIM5 49
#define SAI4 50
#define SYSCFG 51
#define VREF 52
#define TMPSENS 53
#define PMBCTRL 54
#define HDP 55
#define LTDC 56
#define DSI 57
#define IWDG2 58
#define USBPHY 59
#define STGENRO 60
#define SPI6 61
#define I2C4 62
#define I2C6 63
#define USART1 64
#define RTCAPB 65
#define TZC 66
#define TZPC 67
#define IWDG1 68
#define BSEC 69
#define STGEN 70
#define DMA1 71
#define DMA2 72
#define DMAMUX 73
#define ADC12 74
#define USBO 75
#define SDMMC3 76
#define DCMI 77
#define CRYP2 78
#define HASH2 79
#define RNG2 80
#define CRC2 81
#define HSEM 82
#define IPCC 83
#define GPIOA 84
#define GPIOB 85
#define GPIOC 86
#define GPIOD 87
#define GPIOE 88
#define GPIOF 89
#define GPIOG 90
#define GPIOH 91
#define GPIOI 92
#define GPIOJ 93
#define GPIOK 94
#define GPIOZ 95
#define CRYP1 96
#define HASH1 97
#define RNG1 98
#define BKPSRAM 99
#define MDMA 100
#define DMA2D 101
#define GPU 102
#define ETHCK 103
#define ETHTX 104
#define ETHRX 105
#define ETHMAC 106
#define FMC 107
#define QSPI 108
#define SDMMC1 109
#define SDMMC2 110
#define CRC1 111
#define USBH 112
#define ETHSTP 113
/* Kernel clocks */
#define SDMMC1_K 114
#define SDMMC2_K 115
#define SDMMC3_K 116
#define FMC_K 117
#define QSPI_K 118
#define ETHMAC_K 119
#define RNG1_K 120
#define RNG2_K 121
#define GPU_K 122
#define USBPHY_K 123
#define STGEN_K 124
#define SPDIF_K 125
#define SPI1_K 126
#define SPI2_K 127
#define SPI3_K 128
#define SPI4_K 129
#define SPI5_K 130
#define SPI6_K 131
#define CEC_K 132
#define I2C1_K 133
#define I2C2_K 134
#define I2C3_K 135
#define I2C4_K 136
#define I2C5_K 137
#define I2C6_K 138
#define LPTIM1_K 139
#define LPTIM2_K 140
#define LPTIM3_K 141
#define LPTIM4_K 142
#define LPTIM5_K 143
#define USART1_K 144
#define USART2_K 145
#define USART3_K 146
#define UART4_K 147
#define UART5_K 148
#define USART6_K 149
#define UART7_K 150
#define UART8_K 151
#define DFSDM_K 152
#define FDCAN_K 153
#define SAI1_K 154
#define SAI2_K 155
#define SAI3_K 156
#define SAI4_K 157
#define ADC12_K 158
#define DSI_K 159
#define ADFSDM_K 160
#define USBO_K 161
#define LTDC_K 162
/* PLL */
#define PLL1 163
#define PLL2 164
#define PLL3 165
#define PLL4 166
/* ODF */
#define PLL1_P 167
#define PLL1_Q 168
#define PLL1_R 169
#define PLL2_P 170
#define PLL2_Q 171
#define PLL2_R 172
#define PLL3_P 173
#define PLL3_Q 174
#define PLL3_R 175
#define PLL4_P 176
#define PLL4_Q 177
#define PLL4_R 178
/* AUX */
#define RTC 179
/* MCLK */
#define CK_PER 180
#define CK_MPU 181
#define CK_AXI 182
#define CK_MCU 183
/* Time base */
#define TIM2_K 184
#define TIM3_K 185
#define TIM4_K 186
#define TIM5_K 187
#define TIM6_K 188
#define TIM7_K 189
#define TIM12_K 190
#define TIM13_K 191
#define TIM14_K 192
#define TIM1_K 193
#define TIM8_K 194
#define TIM15_K 195
#define TIM16_K 196
#define TIM17_K 197
/* MCO clocks */
#define CK_MCO1 198
#define CK_MCO2 199
/* TRACE & DEBUG clocks */
#define DBG 200
#define CK_DBG 201
#define CK_TRACE 202
/* DDR */
#define DDRC1 203
#define DDRC1LP 204
#define DDRC2 205
#define DDRC2LP 206
#define DDRPHYC 207
#define DDRPHYCLP 208
#define DDRCAPB 209
#define DDRCAPBLP 210
#define AXIDCG 211
#define DDRPHYCAPB 212
#define DDRPHYCAPBLP 213
#define DDRPERFM 214
#define STM32MP1_LAST_CLK 215

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#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
#define USBPHY_R 3088
#define SPI6_R 3136
#define I2C4_R 3138
#define I2C6_R 3139
#define USART1_R 3140
#define STGEN_R 3156
#define GPIOZ_R 3200
#define CRYP1_R 3204
#define HASH1_R 3205
#define RNG1_R 3206
#define AXIM_R 3216
#define GPU_R 3269
#define ETHMAC_R 3274
#define FMC_R 3276
#define QSPI_R 3278
#define SDMMC1_R 3280
#define SDMMC2_R 3281
#define CRC1_R 3284
#define USBH_R 3288
#define MDMA_R 3328
#define MCU_R 8225
#define TIM2_R 19456
#define TIM3_R 19457
#define TIM4_R 19458
#define TIM5_R 19459
#define TIM6_R 19460
#define TIM7_R 19461
#define TIM12_R 16462
#define TIM13_R 16463
#define TIM14_R 16464
#define LPTIM1_R 19465
#define SPI2_R 19467
#define SPI3_R 19468
#define USART2_R 19470
#define USART3_R 19471
#define UART4_R 19472
#define UART5_R 19473
#define UART7_R 19474
#define UART8_R 19475
#define I2C1_R 19477
#define I2C2_R 19478
#define I2C3_R 19479
#define I2C5_R 19480
#define SPDIF_R 19482
#define CEC_R 19483
#define DAC12_R 19485
#define MDIO_R 19847
#define TIM1_R 19520
#define TIM8_R 19521
#define TIM15_R 19522
#define TIM16_R 19523
#define TIM17_R 19524
#define SPI1_R 19528
#define SPI4_R 19529
#define SPI5_R 19530
#define USART6_R 19533
#define SAI1_R 19536
#define SAI2_R 19537
#define SAI3_R 19538
#define DFSDM_R 19540
#define FDCAN_R 19544
#define LPTIM2_R 19584
#define LPTIM3_R 19585
#define LPTIM4_R 19586
#define LPTIM5_R 19587
#define SAI4_R 19592
#define SYSCFG_R 19595
#define VREF_R 19597
#define TMPSENS_R 19600
#define PMBCTRL_R 19601
#define DMA1_R 19648
#define DMA2_R 19649
#define DMAMUX_R 19650
#define ADC12_R 19653
#define USBO_R 19656
#define SDMMC3_R 19664
#define CAMITF_R 19712
#define CRYP2_R 19716
#define HASH2_R 19717
#define RNG2_R 19718
#define CRC2_R 19719
#define HSEM_R 19723
#define MBOX_R 19724
#define GPIOA_R 19776
#define GPIOB_R 19777
#define GPIOC_R 19778
#define GPIOD_R 19779
#define GPIOE_R 19780
#define GPIOF_R 19781
#define GPIOG_R 19782
#define GPIOH_R 19783
#define GPIOI_R 19784
#define GPIOJ_R 19785
#define GPIOK_R 19786