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Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti 

- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver
This commit is contained in:
Tom Rini 2021-05-12 10:07:21 -04:00
parent 59a2b9e605 bbc9da58b3
commit ea184cbff9
121 changed files with 57484 additions and 23611 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/Makefile
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@ -1060,6 +1060,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
k3-am642-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \

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arch/arm/dts/k3-am64-ddr.dtsi Normal file
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arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi Normal file
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arch/arm/dts/k3-am64-main.dtsi Normal file
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@ -0,0 +1,567 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC Family Main Domain peripherals
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
reg = <0x00 0x70000000 0x00 0x200000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x200000>;
atf-sram@0 {
reg = <0x0 0x1a000>;
};
};
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
<0x00 0x01840000 0x00 0xC0000>; /* GICR */
/*
* vcpumntirq:
* virtual CPU interface maintenance interrupt
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: msi-controller@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
msi-controller;
#msi-cells = <1>;
};
};
dmss: dmss {
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges;
ti,sci-dev-id = <25>;
secure_proxy_main: mailbox@4d000000 {
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
reg = <0x00 0x4d000000 0x00 0x80000>,
<0x00 0x4a600000 0x00 0x80000>,
<0x00 0x4a400000 0x00 0x80000>;
interrupt-names = "rx_012";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
};
inta_main_dmss: interrupt-controller@48000000 {
compatible = "ti,sci-inta";
reg = <0x00 0x48000000 0x00 0x100000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <28>;
ti,interrupt-ranges = <4 68 36>;
ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
};
main_bcdma: dma-controller@485c0100 {
compatible = "ti,am64-dmss-bcdma";
reg = <0x00 0x485c0100 0x00 0x100>,
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <26>;
ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
};
main_pktdma: dma-controller@485c0000 {
compatible = "ti,am64-dmss-pktdma";
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <30>;
ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
<0x24>, /* CPSW_TX_CHAN */
<0x25>, /* SAUL_TX_0_CHAN */
<0x26>, /* SAUL_TX_1_CHAN */
<0x27>, /* ICSSG_0_TX_CHAN */
<0x28>; /* ICSSG_1_TX_CHAN */
ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
<0x11>, /* RING_CPSW_TX_CHAN */
<0x12>, /* RING_SAUL_TX_0_CHAN */
<0x13>, /* RING_SAUL_TX_1_CHAN */
<0x14>, /* RING_ICSSG_0_TX_CHAN */
<0x15>; /* RING_ICSSG_1_TX_CHAN */
ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
<0x2b>, /* CPSW_RX_CHAN */
<0x2d>, /* SAUL_RX_0_CHAN */
<0x2f>, /* SAUL_RX_1_CHAN */
<0x31>, /* SAUL_RX_2_CHAN */
<0x33>, /* SAUL_RX_3_CHAN */
<0x35>, /* ICSSG_0_RX_CHAN */
<0x37>; /* ICSSG_1_RX_CHAN */
ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
<0x2c>, /* FLOW_CPSW_RX_CHAN */
<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
};
};
dmsc: dmsc@44043000 {
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 12>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x00 0x44043000 0x00 0xfe0>;
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <2>;
};
k3_clks: clocks {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
k3_reset: reset-controller {
compatible = "ti,sci-reset";
#reset-cells = <2>;
};
};
main_pmx0: pinctrl@f4000 {
compatible = "pinctrl-single";
reg = <0x00 0xf4000 0x00 0x2d0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_conf: syscon@43000000 {
compatible = "syscon", "simple-mfd";
reg = <0x00 0x43000000 0x00 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x43000000 0x20000>;
chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x00000014 0x4>;
};
phy_gmii_sel: phy@4044 {
compatible = "ti,am654-phy-gmii-sel";
reg = <0x4044 0x8>;
#phy-cells = <1>;
};
};
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
};
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 152 0>;
clock-names = "fclk";
};
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 0>;
clock-names = "fclk";
};
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 154 0>;
clock-names = "fclk";
};
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 155 0>;
clock-names = "fclk";
};
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 156 0>;
clock-names = "fclk";
};
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 158 0>;
clock-names = "fclk";
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20000000 0x00 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 102 2>;
clock-names = "fck";
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20010000 0x00 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 103 2>;
clock-names = "fck";
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x00 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 104 2>;
clock-names = "fck";
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x00 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 105 2>;
clock-names = "fck";
};
main_spi0: spi@20100000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x20100000 0x00 0x400>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 141 0>;
dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
dma-names = "tx0", "rx0";
};
main_spi1: spi@20110000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20110000 0x00 0x400>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 142 0>;
};
main_spi2: spi@20120000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20120000 0x00 0x400>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 143 0>;
};
main_spi3: spi@20130000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20130000 0x00 0x400>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 144 0>;
};
main_spi4: spi@20140000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x20140000 0x00 0x400>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 145 0>;
};
sdhci0: mmc@fa10000 {
compatible = "ti,am64-sdhci-8bit";
reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
clock-names = "clk_ahb", "clk_xin";
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x7>;
ti,otap-del-sel-hs400 = <0x4>;
};
sdhci1: mmc@fa00000 {
compatible = "ti,am64-sdhci-4bit";
reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
clock-names = "clk_ahb", "clk_xin";
ti,trm-icp = <0x2>;
ti,otap-del-sel-legacy = <0x0>;
ti,otap-del-sel-sd-hs = <0xf>;
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,clkbuf-sel = <0x7>;
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0x8000000 0x0 0x200000>;
reg-names = "cpsw_nuss";
ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
clocks = <&k3_clks 13 0>;
assigned-clocks = <&k3_clks 13 1>;
assigned-clock-parents = <&k3_clks 13 9>;
clock-names = "fck";
power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
dmas = <&main_pktdma 0xC500 15>,
<&main_pktdma 0xC501 15>,
<&main_pktdma 0xC502 15>,
<&main_pktdma 0xC503 15>,
<&main_pktdma 0xC504 15>,
<&main_pktdma 0xC505 15>,
<&main_pktdma 0xC506 15>,
<&main_pktdma 0xC507 15>,
<&main_pktdma 0x4500 15>;
dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
"tx7", "rx";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
cpsw_port1: port@1 {
reg = <1>;
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
mac-address = [00 00 de ad be ef];
};
cpsw_port2: port@2 {
reg = <2>;
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
mac-address = [00 01 de ad be ef];
};
};
cpsw3g_mdio: mdio@f00 {
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
reg = <0x0 0xf00 0x0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 13 0>;
clock-names = "fck";
bus_freq = <1000000>;
};
cpts@3d000 {
compatible = "ti,j721e-cpts";
reg = <0x0 0x3d000 0x0 0x400>;
clocks = <&k3_clks 13 1>;
clock-names = "cpts";
interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "cpts";
ti,cpts-ext-ts-inputs = <4>;
ti,cpts-periodic-outputs = <2>;
};
};
main_gpio0: gpio@600000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00600000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
<77 1 IRQ_TYPE_EDGE_RISING>,
<77 2 IRQ_TYPE_EDGE_RISING>,
<77 3 IRQ_TYPE_EDGE_RISING>,
<77 4 IRQ_TYPE_EDGE_RISING>,
<77 5 IRQ_TYPE_EDGE_RISING>,
<77 6 IRQ_TYPE_EDGE_RISING>,
<77 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
clock-names = "gpio";
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;
gpio-controller;
#gpio-cells = <2>;
interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
<78 1 IRQ_TYPE_EDGE_RISING>,
<78 2 IRQ_TYPE_EDGE_RISING>,
<78 3 IRQ_TYPE_EDGE_RISING>,
<78 4 IRQ_TYPE_EDGE_RISING>,
<78 5 IRQ_TYPE_EDGE_RISING>,
<78 6 IRQ_TYPE_EDGE_RISING>,
<78 7 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
clock-names = "gpio";
};
main_i2c0: i2c@20000000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20000000 0x0 0x100>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 102 2>;
power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@20010000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x0 0x20010000 0x0 0x100>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 103 2>;
power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@20020000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20020000 0x0 0x100>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 104 2>;
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@20030000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x20030000 0x0 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 105 2>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
};
};

76
arch/arm/dts/k3-am64-mcu.dtsi Normal file
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@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM64 SoC Family MCU Domain peripherals
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
&cbass_mcu {
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 160 0>;
clock-names = "fclk";
};
mcu_i2c0: i2c@4900000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04900000 0x00 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 106 2>;
clock-names = "fck";
};
mcu_i2c1: i2c@4910000 {
compatible = "ti,am64-i2c", "ti,omap4-i2c";
reg = <0x00 0x04910000 0x00 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 107 2>;
clock-names = "fck";
};
mcu_spi0: spi@4b00000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x04b00000 0x00 0x400>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 147 0>;
};
mcu_spi1: spi@4b10000 {
compatible = "ti,am654-mcspi","ti,omap4-mcspi";
reg = <0x00 0x04b10000 0x00 0x400>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 148 0>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC Family
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM642 SoC";
compatible = "ti,am642";
interrupt-parent = <&gic500>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &mcu_uart0;
serial1 = &mcu_uart1;
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
serial5 = &main_uart3;
serial6 = &main_uart4;
serial7 = &main_uart5;
serial8 = &main_uart6;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
};
chosen { };
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
a53_timer0: timer-cl0-cpu0 {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
};
pmu: pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
cbass_main: bus@f4000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
<0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
<0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
<0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
<0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
<0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
<0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
<0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
<0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
<0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
/* MCU Domain Range */
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
cbass_mcu: bus@4000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
};
/* Now include the peripherals for each bus segments */
#include "k3-am64-main.dtsi"
#include "k3-am64-mcu.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
};
&cbass_main{
u-boot,dm-spl;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
};
&main_conf {
u-boot,dm-spl;
chipid@14 {
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_i2c0_pins_default: main-i2c0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
};
&main_i2c0 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_uart0 {
u-boot,dm-spl;
};
&dmss {
u-boot,dm-spl;
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&sdhci0 {
u-boot,dm-spl;
};
&sdhci1 {
u-boot,dm-spl;
};
&cpsw3g {
reg = <0x0 0x8000000 0x0 0x200000>,
<0x0 0x43000200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@04044 {
compatible = "ti,am64-phy-gmii-sel";
reg = <0x0 0x43004044 0x0 0x8>;
};
};
&cpsw_port2 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
};
vddb: fixedregulator-vddb {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
led-0 {
label = "am64-evm:red:heartbeat";
gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
};
mdio_mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
};
mdio-mux-1 {
compatible = "mdio-mux-multiplexer";
mux-controls = <&mdio_mux>;
mdio-parent-bus = <&cpsw3g_mdio>;
#address-cells = <1>;
#size-cells = <0>;
mdio@1 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy3: ethernet-phy@3 {
reg = <3>;
};
};
};
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
>;
};
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
status = "reserved";
};
&main_uart2 {
status = "disabled";
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "disabled";
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
exp1: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
"GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
"GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
"MMC1_SD_EN", "FSI_FET_SEL",
"MCAN0_STB_3V3", "MCAN1_STB_3V3",
"CPSW_FET_SEL", "CPSW_FET2_SEL",
"PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
"GPIO_OLED_RESETn", "VPP_LDO_EN",
"TEST_LED1", "TP92", "TP90", "TP88",
"TP87", "TP86", "TP89", "TP91";
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
vbat-supply = <&vddb>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy3>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
&sdhci0 {
/* emmc */
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am642.dtsi"
#include "k3-am64-evm-ddr4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
vtt_supply: vtt-supply {
compatible = "regulator-gpio";
regulator-name = "vtt";
regulator-min-microvolt = <0>;
regulator-max-microvolt = <3300000>;
gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
states = <0 0x0 3300000 0x1>;
u-boot,dm-spl;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main-uart0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_mmc0_pins_default: main-mmc0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
>;
};
ddr_vtt_pins_default: ddr-vtt-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
&main_uart1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&memorycontroller {
vtt-supply = <&vtt_supply>;
pinctrl-names = "default";
pinctrl-0 = <&ddr_vtt_pins_default>;
};
&sdhci0 {
/delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
ti,driver-strength-ohm = <50>;
disable-wp;
pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
/delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
ti,driver-strength-ohm = <50>;
disable-wp;
pinctrl-0 = <&main_mmc1_pins_default>;
};
&main_gpio0 {
u-boot,dm-spl;
/delete-property/ power-domains;
};
/* EEPROM might be read before SYSFW is available */
&main_i2c0 {
/delete-property/ power-domains;
};
#include "k3-am642-evm-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am642.dtsi"
#include "k3-am64-sk-lp4-1333MTs.dtsi"
#include "k3-am64-ddr.dtsi"
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
u-boot,dm-spl;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main-uart0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_mmc1_pins_default: main-mmc1-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
>;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};
&main_uart1 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
&sdhci1 {
/delete-property/ power-domains;
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
ti,driver-strength-ohm = <50>;
disable-wp;
pinctrl-0 = <&main_mmc1_pins_default>;
};
#include "k3-am642-sk-u-boot.dtsi"

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/ {
chosen {
stdout-path = "serial2:115200n8";
tick-timer = &timer1;
};
};
&cbass_main{
u-boot,dm-spl;
timer1: timer@2400000 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x2400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
};
&main_conf {
u-boot,dm-spl;
chipid@14 {
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_i2c0_pins_default: main-i2c0-pins-default {
u-boot,dm-spl;
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
>;
};
};
&main_i2c0 {
u-boot,dm-spl;
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_uart0 {
u-boot,dm-spl;
};
&dmss {
u-boot,dm-spl;
};
&secure_proxy_main {
u-boot,dm-spl;
};
&dmsc {
u-boot,dm-spl;
};
&k3_pds {
u-boot,dm-spl;
};
&k3_clks {
u-boot,dm-spl;
};
&k3_reset {
u-boot,dm-spl;
};
&sdhci0 {
u-boot,dm-spl;
};
&sdhci1 {
u-boot,dm-spl;
};
&main_mmc1_pins_default {
u-boot,dm-spl;
};
&cpsw3g {
reg = <0x0 0x8000000 0x0 0x200000>,
<0x0 0x43000200 0x0 0x8>;
reg-names = "cpsw_nuss", "mac_efuse";
/delete-property/ ranges;
cpsw-phy-sel@04044 {
compatible = "ti,am64-phy-gmii-sel";
reg = <0x0 0x43004044 0x0 0x8>;
};
};
&cpsw_port2 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
compatible = "ti,am642-sk", "ti,am642";
model = "Texas Instruments AM642 SK";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
};
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio1_pins_default: mdio1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
>;
};
rgmii1_pins_default: rgmii1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
rgmii2_pins_default: rgmii2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
};
&main_uart1 {
/* main_uart1 is reserved for firmware usage */
status = "reserved";
};
&main_uart2 {
status = "disabled";
};
&main_uart3 {
status = "disabled";
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
status = "disabled";
};
&main_uart6 {
status = "disabled";
};
&sdhci1 {
/* SD/MMC */
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
&rgmii2_pins_default>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM642 SoC family in Dual core configuration
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include "k3-am64.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
cache-line-size = <64>;
cache-sets = <512>;
};
};

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arch/arm/mach-k3/Kconfig
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@ -10,6 +10,9 @@ config SOC_K3_AM6
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
config SOC_K3_AM642
bool "TI's K3 based AM642 SoC Family Support"
endchoice
config SYS_SOC
@ -19,16 +22,18 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E
default 0x1c0000 if SOC_K3_AM642
help
Describes the total size of the MCU MSRAM. This doesn't
specify the total size of SPL as ROM can use some part
of this RAM. Once ROM gives control to SPL then this
complete size can be usable.
Describes the total size of the MCU or OCMC MSRAM present on
the SoC in use. This doesn't specify the total size of SPL as
ROM can use some part of this RAM. Once ROM gives control to
SPL then this complete size can be usable.
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E
default 0x180000 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
from any boot media.
@ -51,6 +56,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@ -142,5 +148,6 @@ config SYS_K3_SPL_ATF
after SPL from R5.
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
endif

1
arch/arm/mach-k3/Makefile
View File

@ -5,6 +5,7 @@
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o

315
arch/arm/mach-k3/am642_init.c Normal file
View File

@ -0,0 +1,315 @@
// SPDX-License-Identifier: GPL-2.0
/*
* AM642: SoC specific initialization
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
* Dave Gerlach <d-gerlach@ti.com>
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sysfw-loader.h>
#include <asm/arch/sys_proto.h>
#include "common.h"
#include <asm/arch/sys_proto.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#include <mmc.h>
#include <dm/root.h>
#if defined(CONFIG_SPL_BUILD)
static void ctrl_mmr_unlock(void)
{
/* Unlock all PADCFG_MMR1 module registers */
mmr_unlock(PADCFG_MMR1_BASE, 1);
/* Unlock all CTRL_MMR0 module registers */
mmr_unlock(CTRL_MMR0_BASE, 0);
mmr_unlock(CTRL_MMR0_BASE, 1);
mmr_unlock(CTRL_MMR0_BASE, 2);
mmr_unlock(CTRL_MMR0_BASE, 3);
mmr_unlock(CTRL_MMR0_BASE, 5);
mmr_unlock(CTRL_MMR0_BASE, 6);
}
/*
* This uninitialized global variable would normal end up in the .bss section,
* but the .bss is cleared between writing and reading this variable, so move
* it to the .data section.
*/
u32 bootindex __section(".data");
static struct rom_extended_boot_data bootdata __section(.data);
static void store_boot_info_from_rom(void)
{
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
sizeof(struct rom_extended_boot_data));
}
#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
void k3_mmc_stop_clock(void)
{
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
struct mmc *mmc = find_mmc_device(0);
if (!mmc)
return;
mmc->saved_clock = mmc->clock;
mmc_set_clock(mmc, 0, true);
}
}
void k3_mmc_restart_clock(void)
{
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
struct mmc *mmc = find_mmc_device(0);
if (!mmc)
return;
mmc_set_clock(mmc, mmc->saved_clock, false);
}
}
#else
void k3_mmc_stop_clock(void) {}
void k3_mmc_restart_clock(void) {}
#endif
#ifdef CONFIG_SPL_OF_LIST
void do_dt_magic(void)
{
int ret, rescan;
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
do_board_detect();
/*
* Board detection has been done.
* Let us see if another dtb wouldn't be a better match
* for our board
*/
if (IS_ENABLED(CONFIG_CPU_V7R)) {
ret = fdtdec_resetup(&rescan);
if (!ret && rescan) {
dm_uninit();
dm_init_and_scan(true);
}
}
}
#endif
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
struct udevice *dev;
int ret;
#endif
#if defined(CONFIG_CPU_V7R)
setup_k3_mpu_regions();
#endif
/*
* Cannot delay this further as there is a chance that
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
*/
store_boot_info_from_rom();
ctrl_mmr_unlock();
/* Init DM early */
spl_early_init();
preloader_console_init();
do_dt_magic();
#if defined(CONFIG_K3_LOAD_SYSFW)
/*
* Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
* regardless of the result of pinctrl. Do this without probing the
* device, but instead by searching the device that would request the
* given sequence number if probed. The UART will be used by the system
* firmware (SYSFW) image for various purposes and SYSFW depends on us
* to initialize its pin settings.
*/
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
if (!ret)
pinctrl_select_state(dev, "default");
/*
* Load, start up, and configure system controller firmware.
* This will determine whether or not ROM has already loaded
* system firmware and if so, will only perform needed config
* and not attempt to load firmware again.
*/
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
k3_mmc_restart_clock);
#endif
/* Output System Firmware version info */
k3_sysfw_print_ver();
#if defined(CONFIG_K3_AM64_DDRSS)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
}
u32 spl_boot_mode(const u32 boot_device)
{
switch (boot_device) {
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC2:
return MMCSD_MODE_FS;
default:
return MMCSD_MODE_RAW;
}
}
static u32 __get_backup_bootmedia(u32 main_devstat)
{
u32 bkup_bootmode =
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
u32 bkup_bootmode_cfg =
(main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
switch (bkup_bootmode) {
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_USB;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
case BACKUP_BOOT_DEVICE_MMC:
if (bkup_bootmode_cfg)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BACKUP_BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BACKUP_BOOT_DEVICE_I2C:
return BOOT_DEVICE_I2C;
};
return BOOT_DEVICE_RAM;
}
static u32 __get_primary_bootmedia(u32 main_devstat)
{
u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
u32 bootmode_cfg =
(main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
switch (bootmode) {
case BOOT_DEVICE_OSPI:
fallthrough;
case BOOT_DEVICE_QSPI:
fallthrough;
case BOOT_DEVICE_XSPI:
fallthrough;
case BOOT_DEVICE_SPI:
return BOOT_DEVICE_SPI;
case BOOT_DEVICE_ETHERNET_RGMII:
fallthrough;
case BOOT_DEVICE_ETHERNET_RMII:
return BOOT_DEVICE_ETHERNET;
case BOOT_DEVICE_EMMC:
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_MMC:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_NOBOOT:
return BOOT_DEVICE_RAM;
}
return bootmode;
}
u32 spl_boot_device(void)
{
u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
if (bootindex == K3_PRIMARY_BOOTMODE)
return __get_primary_bootmedia(devstat);
else
return __get_backup_bootmedia(devstat);
}
#endif
#if defined(CONFIG_SYS_K3_SPL_ATF)
#define AM64X_DEV_RTI8 127
#define AM64X_DEV_RTI9 128
#define AM64X_DEV_R5FSS0_CORE0 121
#define AM64X_DEV_R5FSS0_CORE1 122
void release_resources_for_core_shutdown(void)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
int ret;
u32 i;
const u32 put_device_ids[] = {
AM64X_DEV_RTI9,
AM64X_DEV_RTI8,
};
/* Iterate through list of devices to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
u32 id = put_device_ids[i];
ret = dev_ops->put_device(ti_sci, id);
if (ret)
panic("Failed to put device %u (%d)\n", id, ret);
}
const u32 put_core_ids[] = {
AM64X_DEV_R5FSS0_CORE1,
AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
};
/* Iterate through list of cores to put (shutdown) */
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
u32 id = put_core_ids[i];
/*
* Queue up the core shutdown request. Note that this call
* needs to be followed up by an actual invocation of an WFE
* or WFI CPU instruction.
*/
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
if (ret)
panic("Failed sending core %u shutdown message (%d)\n",
id, ret);
}
}
#endif

41
arch/arm/mach-k3/arm64-mmu.c
View File

@ -180,3 +180,44 @@ struct mm_region *mem_map = j7200_mem_map;
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#endif /* CONFIG_SOC_K3_J721E */
#ifdef CONFIG_SOC_K3_AM642
/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
/* ToDo: Add 64bit IO */
struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x880000000UL,
.phys = 0x880000000UL,
.size = 0x80000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0x500000000UL,
.phys = 0x500000000UL,
.size = 0x400000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = am64_mem_map;
#endif /* CONFIG_SOC_K3_AM642 */

55
arch/arm/mach-k3/include/mach/am64_hardware.h Normal file
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@ -0,0 +1,55 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* K3: AM64 SoC definitions, structures etc.
*
* (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __ASM_ARCH_AM64_HARDWARE_H
#define __ASM_ARCH_AM64_HARDWARE_H
#include <config.h>
#define CTRL_MMR0_BASE 0x43000000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
#define PADCFG_MMR1_BASE 0xf0000
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
/* After the cfg mask and shifts have been applied */
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
/*
* The CTRL_MMR and PADCFG_MMR memory space is divided into several
* equally-spaced partitions, so defining the partition size allows us to
* determine register addresses common to those partitions.
*/
#define CTRL_MMR0_PARTITION_SIZE 0x4000
/*
* CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
*/
#define CTRLMMR_LOCK_KICK0 0x01008
#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
/* Use Last 1K as Scratch pad */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00
#endif /* __ASM_ARCH_DRA8_HARDWARE_H */

44
arch/arm/mach-k3/include/mach/am64_spl.h Normal file
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@ -0,0 +1,44 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
*/
#ifndef _ASM_ARCH_AM64_SPL_H_
#define _ASM_ARCH_AM64_SPL_H_
/* Primary BootMode devices */
#define BOOT_DEVICE_RAM 0x00
#define BOOT_DEVICE_OSPI 0x01
#define BOOT_DEVICE_QSPI 0x02
#define BOOT_DEVICE_SPI 0x03
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_ETHERNET_RGMII 0x04
#define BOOT_DEVICE_ETHERNET_RMII 0x05
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
#define BOOT_DEVICE_MMC 0x08
#define BOOT_DEVICE_EMMC 0x09
#define BOOT_DEVICE_USB 0x0A
#define BOOT_DEVICE_GPMC_NOR 0x0C
#define BOOT_DEVICE_PCIE 0x0D
#define BOOT_DEVICE_XSPI 0x0E
#define BOOT_DEVICE_NOBOOT 0x0F
#define BOOT_DEVICE_MMC2 0x08
#define BOOT_DEVICE_MMC1 0x09
/* INVALID */
#define BOOT_DEVICE_MMC2_2 0x1F
/* Backup BootMode devices */
#define BACKUP_BOOT_DEVICE_USB 0x01
#define BACKUP_BOOT_DEVICE_UART 0x03
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
#define BACKUP_BOOT_DEVICE_MMC 0x05
#define BACKUP_BOOT_DEVICE_SPI 0x06
#define BACKUP_BOOT_DEVICE_I2C 0x07
#define K3_PRIMARY_BOOTMODE 0x0
#endif

4
arch/arm/mach-k3/include/mach/hardware.h
View File

@ -14,6 +14,10 @@
#include "j721e_hardware.h"
#endif
#ifdef CONFIG_SOC_K3_AM642
#include "am64_hardware.h"
#endif
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
#define JTAG_ID_VARIANT_SHIFT 28

4
arch/arm/mach-k3/include/mach/spl.h
View File

@ -13,4 +13,8 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_spl.h"
#endif
#ifdef CONFIG_SOC_K3_AM642
#include "am64_spl.h"
#endif
#endif /* _ASM_ARCH_SPL_H_ */

21
arch/sandbox/dts/test.dts
View File

@ -45,7 +45,6 @@
fdt-dummy1 = "/translation-test@8000/dev@1,100";
fdt-dummy2 = "/translation-test@8000/dev@2,200";
fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
usb0 = &usb_0;
usb1 = &usb_1;
usb2 = &usb_2;
@ -1270,7 +1269,6 @@
1 0x100 0x9000 0x1000
2 0x200 0xA000 0x1000
3 0x300 0xB000 0x1000
4 0x400 0xC000 0x1000
>;
dma-ranges = <0 0x000 0x10000000 0x1000
@ -1307,25 +1305,6 @@
reg = <0x42>;
};
};
xlatebus@4,400 {
compatible = "sandbox,zero-size-cells-bus";
reg = <4 0x400 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 4 0x400 0x1000>;
devs {
#address-cells = <1>;
#size-cells = <0>;
dev@19 {
compatible = "denx,u-boot-fdt-dummy";
reg = <0x19>;
};
};
};
};
osd {

62
board/ti/am64x/Kconfig Normal file
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@ -0,0 +1,62 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
choice
prompt "K3 AM64 based boards"
optional
config TARGET_AM642_A53_EVM
bool "TI K3 based AM642 EVM running on A53"
select ARM64
select SOC_K3_AM642
imply BOARD
imply SPL_BOARD
imply TI_I2C_BOARD_DETECT
config TARGET_AM642_R5_EVM
bool "TI K3 based AM642 EVM running on R5"
select CPU_V7R
select SYS_THUMB_BUILD
select K3_LOAD_SYSFW
select SOC_K3_AM642
select RAM
select SPL_RAM
select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
endchoice
if TARGET_AM642_A53_EVM
config SYS_BOARD
default "am64x"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "am64x_evm"
source "board/ti/common/Kconfig"
endif
if TARGET_AM642_R5_EVM
config SYS_BOARD
default "am64x"
config SYS_VENDOR
default "ti"
config SYS_CONFIG_NAME
default "am64x_evm"
config SPL_LDSCRIPT
default "arch/arm/mach-omap2/u-boot-spl.lds"
source "board/ti/common/Kconfig"
endif

8
board/ti/am64x/MAINTAINERS Normal file
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@ -0,0 +1,8 @@
AM64x BOARD
M: Dave Gerlach <d-gerlach@ti.com>
M: Lokesh Vutla <lokeshvutla@ti.com>
S: Maintained
F: board/ti/am64x/
F: include/configs/am64x_evm.h
F: configs/am64x_evm_r5_defconfig
F: configs/am64x_evm_a53_defconfig

8
board/ti/am64x/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
# Keerthy <j-keerthy@ti.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += evm.o

154
board/ti/am64x/evm.c Normal file
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@ -0,0 +1,154 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board specific initialization for AM642 EVM
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
* Keerthy <j-keerthy@ti.com>
*
*/
#include <common.h>
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <env.h>
#include "../common/board_detect.h"
#define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM")
#define board_is_am64x_skevm() board_ti_k3_is("AM64-SKEVM")
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int dram_init(void)
{
gd->ram_size = 0x80000000;
return 0;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
return 0;
}
#if defined(CONFIG_SPL_LOAD_FIT)
int board_fit_config_name_match(const char *name)
{
bool eeprom_read = board_ti_was_eeprom_read();
if (!eeprom_read || board_is_am64x_gpevm()) {
if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm"))
return 0;
} else if (board_is_am64x_skevm()) {
if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk"))
return 0;
}
return -1;
}
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
int do_board_detect(void)
{
int ret;
ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (ret) {
printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS + 1);
if (ret)
pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
}
return ret;
}
int checkboard(void)
{
struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
if (!do_board_detect())
printf("Board: %s rev %s\n", ep->name, ep->version);
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
static void setup_board_eeprom_env(void)
{
char *name = "am64x_gpevm";
if (do_board_detect())
goto invalid_eeprom;
if (board_is_am64x_gpevm())
name = "am64x_gpevm";
else if (board_is_am64x_skevm())
name = "am64x_skevm";
else
printf("Unidentified board claims %s in eeprom header\n",
board_ti_get_name());
invalid_eeprom:
set_board_info_env_am6(name);
}
static void setup_serial(void)
{
struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
unsigned long board_serial;
char *endp;
char serial_string[17] = { 0 };
if (env_get("serial#"))
return;
board_serial = simple_strtoul(ep->serial, &endp, 16);
if (*endp != '\0') {
pr_err("Error: Can't set serial# to %s\n", ep->serial);
return;
}
snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
env_set("serial#", serial_string);
}
#endif
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
setup_board_eeprom_env();
setup_serial();
/*
* The first MAC address for ethernet a.k.a. ethernet0 comes from
* efuse populated via the am654 gigabit eth switch subsystem driver.
* All the other ones are populated via EEPROM, hence continue with
* an index of 1.
*/
board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
}
return 0;
}
#endif

4
board/ti/j721e/Kconfig
View File

@ -23,7 +23,7 @@ config TARGET_J721E_R5_EVM
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_J721E_DDRSS
select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
@ -43,7 +43,7 @@ config TARGET_J7200_R5_EVM
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
select K3_J721E_DDRSS
select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT

6
common/fdt_support.c
View File

@ -20,8 +20,6 @@
#include <exports.h>
#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
@ -1001,8 +999,8 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR FDT_ADDR_T_NONE
#define OF_CHECK_COUNTS(na, ns) (((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) && \
((ns) > 0 || gd_size_cells_0()))
#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
(ns) > 0)
/* Debug utility */
#ifdef DEBUG

104
configs/am64x_evm_a53_defconfig Normal file
View File

@ -0,0 +1,104 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_A53_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DMA=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_TIME=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_TI=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

107
configs/am64x_evm_r5_defconfig Normal file
View File

@ -0,0 +1,107 @@
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_ENV_SIZE=0x20000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_TEXT_BASE=0x70020000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_SIZE_LIMIT=0x190000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_SPL_LOAD_FIT=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_REMOTEPROC=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
CONFIG_RESET_TI_SCI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384

3
doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
View File

@ -9,7 +9,8 @@ DDRSS device node:
==================
Required properties:
--------------------
- compatible: Shall be: "ti,j721e-ddrss"
- compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200
"ti,am64-ddrss" for am642
- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
- reg: Contains the register map per reg-names.

86
drivers/clk/ti/clk-am3-dpll.c
View File

@ -17,15 +17,16 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include "clk.h"
struct clk_ti_am3_dpll_drv_data {
ulong max_rate;
};
struct clk_ti_am3_dpll_priv {
fdt_addr_t clkmode_reg;
fdt_addr_t idlest_reg;
fdt_addr_t clksel_reg;
struct clk_ti_reg clkmode_reg;
struct clk_ti_reg idlest_reg;
struct clk_ti_reg clksel_reg;
struct clk clk_bypass;
struct clk clk_ref;
u16 last_rounded_mult;
@ -75,6 +76,37 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
return ret;
}
static void clk_ti_am3_dpll_clken(struct clk_ti_am3_dpll_priv *priv,
u8 clken_bits)
{
u32 v;
v = clk_ti_readl(&priv->clkmode_reg);
v &= ~CM_CLKMODE_DPLL_DPLL_EN_MASK;
v |= clken_bits << CM_CLKMODE_DPLL_EN_SHIFT;
clk_ti_writel(v, &priv->clkmode_reg);
}
static int clk_ti_am3_dpll_state(struct clk *clk, u8 state)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
u32 i = 0, v;
do {
v = clk_ti_readl(&priv->idlest_reg) & ST_DPLL_CLK_MASK;
if (v == state) {
dev_dbg(clk->dev, "transition to '%s' in %d loops\n",
state ? "locked" : "bypassed", i);
return 1;
}
} while (++i < LDELAY);
dev_err(clk->dev, "failed transition to '%s'\n",
state ? "locked" : "bypassed");
return 0;
}
static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
@ -85,16 +117,13 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
if (IS_ERR_VALUE(round_rate))
return round_rate;
v = readl(priv->clksel_reg);
v = clk_ti_readl(&priv->clksel_reg);
/* enter bypass mode */
clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
clk_ti_am3_dpll_clken(priv, DPLL_EN_MN_BYPASS);
/* wait for bypass mode */
if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
(void *)priv->idlest_reg, LDELAY))
dev_err(clk->dev, "failed bypassing dpll\n");
clk_ti_am3_dpll_state(clk, 0);
/* set M & N */
v &= ~CM_CLKSEL_DPLL_M_MASK;
@ -105,18 +134,14 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
CM_CLKSEL_DPLL_N_MASK;
writel(v, priv->clksel_reg);
clk_ti_writel(v, &priv->clksel_reg);
/* lock dpll */
clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
/* wait till the dpll locks */
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
(void *)priv->idlest_reg, LDELAY)) {
dev_err(clk->dev, "failed locking dpll\n");
if (!clk_ti_am3_dpll_state(clk, ST_DPLL_CLK_MASK))
hang();
}
return round_rate;
}
@ -128,7 +153,7 @@ static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
u32 m, n, v;
/* Return bypass rate if DPLL is bypassed */
v = readl(priv->clkmode_reg);
v = clk_ti_readl(&priv->clkmode_reg);
v &= CM_CLKMODE_DPLL_EN_MASK;
v >>= CM_CLKMODE_DPLL_EN_SHIFT;
@ -141,7 +166,7 @@ static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
return rate;
}
v = readl(priv->clksel_reg);
v = clk_ti_readl(&priv->clksel_reg);
m = v & CM_CLKSEL_DPLL_M_MASK;
m >>= CM_CLKSEL_DPLL_M_SHIFT;
n = v & CM_CLKSEL_DPLL_N_MASK;
@ -204,33 +229,28 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
struct clk_ti_am3_dpll_drv_data *data =
(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
int err;
priv->max_rate = data->max_rate;
priv->clkmode_reg = dev_read_addr_index(dev, 0);
if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
dev_err(dev, "failed to get clkmode register\n");
return -EINVAL;
err = clk_ti_get_reg_addr(dev, 0, &priv->clkmode_reg);
if (err) {
dev_err(dev, "failed to get clkmode register address\n");
return err;
}
dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
priv->idlest_reg = dev_read_addr_index(dev, 1);
if (priv->idlest_reg == FDT_ADDR_T_NONE) {
err = clk_ti_get_reg_addr(dev, 1, &priv->idlest_reg);
if (err) {
dev_err(dev, "failed to get idlest register\n");
return -EINVAL;
}
dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
priv->clksel_reg = dev_read_addr_index(dev, 2);
if (priv->clksel_reg == FDT_ADDR_T_NONE) {
err = clk_ti_get_reg_addr(dev, 2, &priv->clksel_reg);
if (err) {
dev_err(dev, "failed to get clksel register\n");
return -EINVAL;
return err;
}
dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
return 0;
}

20
drivers/clk/ti/clk-divider.c
View File

@ -27,7 +27,7 @@
struct clk_ti_divider_priv {
struct clk parent;
fdt_addr_t reg;
struct clk_ti_reg reg;
const struct clk_div_table *table;
u8 shift;
u8 flags;
@ -200,11 +200,11 @@ static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
val = _get_val(priv->table, priv->div_flags, div);
v = readl(priv->reg);
v = clk_ti_readl(&priv->reg);
v &= ~(priv->mask << priv->shift);
v |= val << priv->shift;
writel(v, priv->reg);
clk_ti_latch(priv->reg, priv->latch);
clk_ti_writel(v, &priv->reg);
clk_ti_latch(&priv->reg, priv->latch);
return clk_get_rate(clk);
}
@ -220,7 +220,7 @@ static ulong clk_ti_divider_get_rate(struct clk *clk)
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
v = readl(priv->reg) >> priv->shift;
v = clk_ti_readl(&priv->reg) >> priv->shift;
v &= priv->mask;
div = _get_div(priv->table, priv->div_flags, v);
@ -287,10 +287,14 @@ static int clk_ti_divider_of_to_plat(struct udevice *dev)
u32 min_div = 0;
u32 max_val, max_div = 0;
u16 mask;
int i, div_num;
int i, div_num, err;
err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
if (err) {
dev_err(dev, "failed to get register address\n");
return err;
}
priv->reg = dev_read_addr(dev);
dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
if (dev_read_bool(dev, "ti,index-starts-at-one"))

23
drivers/clk/ti/clk-gate.c
View File

@ -13,9 +13,10 @@
#include <clk-uclass.h>
#include <asm/io.h>
#include <linux/clk-provider.h>
#include "clk.h"
struct clk_ti_gate_priv {
fdt_addr_t reg;
struct clk_ti_reg reg;
u8 enable_bit;
u32 flags;
bool invert_enable;
@ -26,13 +27,13 @@ static int clk_ti_gate_disable(struct clk *clk)
struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
u32 v;
v = readl(priv->reg);
v = clk_ti_readl(&priv->reg);
if (priv->invert_enable)
v |= (1 << priv->enable_bit);
else
v &= ~(1 << priv->enable_bit);
writel(v, priv->reg);
clk_ti_writel(v, &priv->reg);
/* No OCP barrier needed here since it is a disable operation */
return 0;
}
@ -42,29 +43,29 @@ static int clk_ti_gate_enable(struct clk *clk)
struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
u32 v;
v = readl(priv->reg);
v = clk_ti_readl(&priv->reg);
if (priv->invert_enable)
v &= ~(1 << priv->enable_bit);
else
v |= (1 << priv->enable_bit);
writel(v, priv->reg);
clk_ti_writel(v, &priv->reg);
/* OCP barrier */
v = readl(priv->reg);
v = clk_ti_readl(&priv->reg);
return 0;
}
static int clk_ti_gate_of_to_plat(struct udevice *dev)
{
struct clk_ti_gate_priv *priv = dev_get_priv(dev);
int err;
priv->reg = dev_read_addr(dev);
if (priv->reg == FDT_ADDR_T_NONE) {
dev_err(dev, "failed to get control register\n");
return -EINVAL;
err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
if (err) {
dev_err(dev, "failed to get control register address\n");
return err;
}
dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
if (dev_read_bool(dev, "ti,set-rate-parent"))
priv->flags |= CLK_SET_RATE_PARENT;

20
drivers/clk/ti/clk-mux.c
View File

@ -17,7 +17,7 @@
struct clk_ti_mux_priv {
struct clk_bulk parents;
fdt_addr_t reg;
struct clk_ti_reg reg;
u32 flags;
u32 mux_flags;
u32 mask;
@ -58,7 +58,7 @@ static int clk_ti_mux_get_index(struct clk *clk)
struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
u32 val;
val = readl(priv->reg);
val = clk_ti_readl(&priv->reg);
val >>= priv->shift;
val &= priv->mask;
@ -91,13 +91,13 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
if (priv->flags & CLK_MUX_HIWORD_MASK) {
val = priv->mask << (priv->shift + 16);
} else {
val = readl(priv->reg);
val = clk_ti_readl(&priv->reg);
val &= ~(priv->mask << priv->shift);
}
val |= index << priv->shift;
writel(val, priv->reg);
clk_ti_latch(priv->reg, priv->latch);
clk_ti_writel(val, &priv->reg);
clk_ti_latch(&priv->reg, priv->latch);
return 0;
}
@ -215,14 +215,14 @@ static int clk_ti_mux_probe(struct udevice *dev)
static int clk_ti_mux_of_to_plat(struct udevice *dev)
{
struct clk_ti_mux_priv *priv = dev_get_priv(dev);
int err;
priv->reg = dev_read_addr(dev);
if (priv->reg == FDT_ADDR_T_NONE) {
dev_err(dev, "failed to get register\n");
return -EINVAL;
err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
if (err) {
dev_err(dev, "failed to get register address\n");
return err;
}
dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);

95
drivers/clk/ti/clk.c
View File

@ -6,21 +6,34 @@
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <regmap.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include "clk.h"
static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
#define CLK_MAX_MEMMAPS 10
struct clk_iomap {
struct regmap *regmap;
ofnode node;
};
static unsigned int clk_memmaps_num;
static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
static void clk_ti_rmw(u32 val, u32 mask, struct clk_ti_reg *reg)
{
u32 v;
v = readl(reg);
v = clk_ti_readl(reg);
v &= ~mask;
v |= val;
writel(v, reg);
clk_ti_writel(v, reg);
}
void clk_ti_latch(fdt_addr_t reg, s8 shift)
void clk_ti_latch(struct clk_ti_reg *reg, s8 shift)
{
u32 latch;
@ -31,5 +44,77 @@ void clk_ti_latch(fdt_addr_t reg, s8 shift)
clk_ti_rmw(latch, latch, reg);
clk_ti_rmw(0, latch, reg);
readl(reg); /* OCP barrier */
clk_ti_readl(reg); /* OCP barrier */
}
void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
{
struct clk_iomap *io = &clk_memmaps[reg->index];
regmap_write(io->regmap, reg->offset, val);
}
u32 clk_ti_readl(struct clk_ti_reg *reg)
{
struct clk_iomap *io = &clk_memmaps[reg->index];
u32 val;
regmap_read(io->regmap, reg->offset, &val);
return val;
}
static ofnode clk_ti_get_regmap_node(struct udevice *dev)
{
ofnode node = dev_ofnode(dev), parent;
if (!ofnode_valid(node))
return ofnode_null();
parent = ofnode_get_parent(node);
if (strcmp(ofnode_get_name(parent), "clocks"))
return ofnode_null();
return ofnode_get_parent(parent);
}
int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
{
ofnode node;
int i, ret;
u32 val;
ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
if (ret) {
dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
index);
return ret;
}
/* parent = ofnode_get_parent(parent); */
node = clk_ti_get_regmap_node(dev);
if (!ofnode_valid(node)) {
dev_err(dev, "failed to get regmap node\n");
return -EFAULT;
}
for (i = 0; i < clk_memmaps_num; i++) {
if (ofnode_equal(clk_memmaps[i].node, node))
break;
}
if (i == clk_memmaps_num) {
if (i == CLK_MAX_MEMMAPS)
return -ENOMEM;
ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
if (ret)
return ret;
clk_memmaps[i].node = node;
clk_memmaps_num++;
}
reg->index = i;
reg->offset = val;
return 0;
}

15
drivers/clk/ti/clk.h
View File

@ -8,6 +8,19 @@
#ifndef _CLK_TI_H
#define _CLK_TI_H
void clk_ti_latch(fdt_addr_t reg, s8 shift);
/**
* struct clk_ti_reg - TI register declaration
* @offset: offset from the master IP module base address
* @index: index of the master IP module
*/
struct clk_ti_reg {
u16 offset;
u8 index;
};
void clk_ti_latch(struct clk_ti_reg *reg, s8 shift);
void clk_ti_writel(u32 val, struct clk_ti_reg *reg);
u32 clk_ti_readl(struct clk_ti_reg *reg);
int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg);
#endif /* #ifndef _CLK_TI_H */

12
drivers/core/Kconfig
View File

@ -271,18 +271,6 @@ config OF_TRANSLATE
used for the address translation. This function is faster and
smaller in size than fdt_translate_address().
config OF_TRANSLATE_ZERO_SIZE_CELLS
bool "Enable translation for zero size cells"
depends on OF_TRANSLATE
default n
help
The routine used to translate an FDT address into a physical CPU
address was developed by IBM. It considers that crossing any level
with #size-cells = <0> makes translation impossible, even if it is
not the way it was specified.
Enabling this option makes translation possible even in the case
of crossing levels with #size-cells = <0>.
config SPL_OF_TRANSLATE
bool "Translate addresses using fdt_translate_address in SPL"
depends on SPL_DM && SPL_OF_CONTROL

2
drivers/core/fdtaddr.c
View File

@ -50,7 +50,7 @@ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index)
reg += index * (na + ns);
if (ns || gd_size_cells_0()) {
if (ns) {
/*
* Use the full-fledged translate function for complex
* bus setups.

13
drivers/core/of_addr.c
View File

@ -18,8 +18,7 @@
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
#define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && \
((ns) > 0 || gd_size_cells_0()))
#define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0)
static struct of_bus *of_match_bus(struct device_node *np);
@ -163,6 +162,11 @@ const __be32 *of_get_address(const struct device_node *dev, int index,
}
EXPORT_SYMBOL(of_get_address);
static int of_empty_ranges_quirk(const struct device_node *np)
{
return false;
}
static int of_translate_one(const struct device_node *parent,
struct of_bus *bus, struct of_bus *pbus,
__be32 *addr, int na, int ns, int pna,
@ -189,8 +193,11 @@ static int of_translate_one(const struct device_node *parent,
* As far as we know, this damage only exists on Apple machines, so
* This code is only enabled on powerpc. --gcl
*/
ranges = of_get_property(parent, rprop, &rlen);
if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
debug("no ranges; cannot translate\n");
return 1;
}
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);

7
drivers/core/ofnode.c
View File

@ -319,8 +319,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
ns = of_n_size_cells(ofnode_to_np(node));
if (IS_ENABLED(CONFIG_OF_TRANSLATE) &&
(ns > 0 || gd_size_cells_0())) {
if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
return of_translate_address(ofnode_to_np(node), prop_val);
} else {
na = of_n_addr_cells(ofnode_to_np(node));
@ -703,10 +702,8 @@ fdt_addr_t ofnode_get_addr_size(ofnode node, const char *property,
ns = of_n_size_cells(np);
*sizep = of_read_number(prop + na, ns);
if (CONFIG_IS_ENABLED(OF_TRANSLATE) &&
(ns > 0 || gd_size_cells_0())) {
if (CONFIG_IS_ENABLED(OF_TRANSLATE) && ns > 0)
return of_translate_address(np, prop);
}
else
return of_read_number(prop, na);
} else {

3
drivers/core/root.c
View File

@ -164,9 +164,6 @@ int dm_init(bool of_live)
{
int ret;
if (IS_ENABLED(CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS))
gd->dm_flags |= GD_DM_FLG_SIZE_CELLS_0;
if (gd->dm_root) {
dm_warn("Virtual root driver already exists!\n");
return -EINVAL;

1
drivers/dma/ti/Makefile
View File

@ -5,3 +5,4 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o

156
drivers/dma/ti/k3-psil-am64.c Normal file
View File

@ -0,0 +1,156 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*/
#include <linux/kernel.h>
#include "k3-psil-priv.h"
#define PSIL_PDMA_XY_TR(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_PDMA_XY, \
.mapped_channel_id = -1, \
}, \
}
#define PSIL_PDMA_XY_PKT(x) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_PDMA_XY, \
.mapped_channel_id = -1, \
.pkt_mode = 1, \
}, \
}
#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_NATIVE, \
.pkt_mode = 1, \
.needs_epib = 1, \
.psd_size = 16, \
.mapped_channel_id = ch, \
.flow_start = flow_base, \
.flow_num = flow_cnt, \
.default_flow_id = flow_base, \
}, \
}
#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
{ \
.thread_id = x, \
.ep_config = { \
.ep_type = PSIL_EP_NATIVE, \
.pkt_mode = 1, \
.needs_epib = 1, \
.psd_size = 64, \
.mapped_channel_id = ch, \
.flow_start = flow_base, \
.flow_num = flow_cnt, \
.default_flow_id = default_flow, \
.notdpkt = tx, \
}, \
}
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
static struct psil_ep am64_src_ep_map[] = {
/* SAUL */
PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
/* ICSS_G0 */
PSIL_ETHERNET(0x4100, 21, 48, 16),
PSIL_ETHERNET(0x4101, 22, 64, 16),
PSIL_ETHERNET(0x4102, 23, 80, 16),
PSIL_ETHERNET(0x4103, 24, 96, 16),
/* ICSS_G1 */
PSIL_ETHERNET(0x4200, 25, 112, 16),
PSIL_ETHERNET(0x4201, 26, 128, 16),
PSIL_ETHERNET(0x4202, 27, 144, 16),
PSIL_ETHERNET(0x4203, 28, 160, 16),
/* PDMA_MAIN0 - SPI0-3 */
PSIL_PDMA_XY_PKT(0x4300),
PSIL_PDMA_XY_PKT(0x4301),
PSIL_PDMA_XY_PKT(0x4302),
PSIL_PDMA_XY_PKT(0x4303),
PSIL_PDMA_XY_PKT(0x4304),
PSIL_PDMA_XY_PKT(0x4305),
PSIL_PDMA_XY_PKT(0x4306),
PSIL_PDMA_XY_PKT(0x4307),
PSIL_PDMA_XY_PKT(0x4308),
PSIL_PDMA_XY_PKT(0x4309),
PSIL_PDMA_XY_PKT(0x430a),
PSIL_PDMA_XY_PKT(0x430b),
PSIL_PDMA_XY_PKT(0x430c),
PSIL_PDMA_XY_PKT(0x430d),
PSIL_PDMA_XY_PKT(0x430e),
PSIL_PDMA_XY_PKT(0x430f),
/* PDMA_MAIN0 - USART0-1 */
PSIL_PDMA_XY_PKT(0x4310),
PSIL_PDMA_XY_PKT(0x4311),
/* PDMA_MAIN1 - SPI4 */
PSIL_PDMA_XY_PKT(0x4400),
PSIL_PDMA_XY_PKT(0x4401),
PSIL_PDMA_XY_PKT(0x4402),
PSIL_PDMA_XY_PKT(0x4403),
/* PDMA_MAIN1 - USART2-6 */
PSIL_PDMA_XY_PKT(0x4404),
PSIL_PDMA_XY_PKT(0x4405),
PSIL_PDMA_XY_PKT(0x4406),
PSIL_PDMA_XY_PKT(0x4407),
PSIL_PDMA_XY_PKT(0x4408),
/* PDMA_MAIN1 - ADCs */
PSIL_PDMA_XY_TR(0x440f),
PSIL_PDMA_XY_TR(0x4410),
/* CPSW2 */
PSIL_ETHERNET(0x4500, 16, 16, 16),
};
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
static struct psil_ep am64_dst_ep_map[] = {
/* SAUL */
PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
/* ICSS_G0 */
PSIL_ETHERNET(0xc100, 26, 96, 1),
PSIL_ETHERNET(0xc101, 27, 97, 1),
PSIL_ETHERNET(0xc102, 28, 98, 1),
PSIL_ETHERNET(0xc103, 29, 99, 1),
PSIL_ETHERNET(0xc104, 30, 100, 1),
PSIL_ETHERNET(0xc105, 31, 101, 1),
PSIL_ETHERNET(0xc106, 32, 102, 1),
PSIL_ETHERNET(0xc107, 33, 103, 1),
/* ICSS_G1 */
PSIL_ETHERNET(0xc200, 34, 104, 1),
PSIL_ETHERNET(0xc201, 35, 105, 1),
PSIL_ETHERNET(0xc202, 36, 106, 1),
PSIL_ETHERNET(0xc203, 37, 107, 1),
PSIL_ETHERNET(0xc204, 38, 108, 1),
PSIL_ETHERNET(0xc205, 39, 109, 1),
PSIL_ETHERNET(0xc206, 40, 110, 1),
PSIL_ETHERNET(0xc207, 41, 111, 1),
/* CPSW2 */
PSIL_ETHERNET(0xc500, 16, 16, 8),
PSIL_ETHERNET(0xc501, 17, 24, 8),
PSIL_ETHERNET(0xc502, 18, 32, 8),
PSIL_ETHERNET(0xc503, 19, 40, 8),
PSIL_ETHERNET(0xc504, 20, 48, 8),
PSIL_ETHERNET(0xc505, 21, 56, 8),
PSIL_ETHERNET(0xc506, 22, 64, 8),
PSIL_ETHERNET(0xc507, 23, 72, 8),
};
struct psil_ep_map am64_ep_map = {
.name = "am64",
.src = am64_src_ep_map,
.src_count = ARRAY_SIZE(am64_src_ep_map),
.dst = am64_dst_ep_map,
.dst_count = ARRAY_SIZE(am64_dst_ep_map),
};

32
drivers/dma/ti/k3-psil-am654.c
View File

@ -44,40 +44,22 @@ static struct psil_ep am654_src_ep_map[] = {
static struct psil_ep am654_dst_ep_map[] = {
/* PRU_ICSSG0 */
PSIL_ETHERNET(0xc100),
PSIL_ETHERNET(0xc101),
PSIL_ETHERNET(0xc102),
PSIL_ETHERNET(0xc103),
/* PSIL: 0xc101 - 0xc103 unused */
PSIL_ETHERNET(0xc104),
PSIL_ETHERNET(0xc105),
PSIL_ETHERNET(0xc106),
PSIL_ETHERNET(0xc107),
/* PSIL: 0xc105 - 0xc107 unused */
/* PRU_ICSSG1 */
PSIL_ETHERNET(0xc200),
PSIL_ETHERNET(0xc201),
PSIL_ETHERNET(0xc202),
PSIL_ETHERNET(0xc203),
/* PSIL: 0xc201 - 0xc203 unused */
PSIL_ETHERNET(0xc204),
PSIL_ETHERNET(0xc205),
PSIL_ETHERNET(0xc206),
PSIL_ETHERNET(0xc207),
/* PSIL: 0xc205 - 0xc207 unused */
/* PRU_ICSSG2 */
PSIL_ETHERNET(0xc300),
PSIL_ETHERNET(0xc301),
PSIL_ETHERNET(0xc302),
PSIL_ETHERNET(0xc303),
/* PSIL: 0xc301 - 0xc303 unused */
PSIL_ETHERNET(0xc304),
PSIL_ETHERNET(0xc305),
PSIL_ETHERNET(0xc306),
PSIL_ETHERNET(0xc307),
/* PSIL: 0xc305 - 0xc307 unused */
/* CPSW0 */
PSIL_ETHERNET(0xf000),
PSIL_ETHERNET(0xf001),
PSIL_ETHERNET(0xf002),
PSIL_ETHERNET(0xf003),
PSIL_ETHERNET(0xf004),
PSIL_ETHERNET(0xf005),
PSIL_ETHERNET(0xf006),
PSIL_ETHERNET(0xf007),
/* PSIL: 0xf001 - 0xf007 unused */
};
struct psil_ep_map am654_ep_map = {

1
drivers/dma/ti/k3-psil-priv.h
View File

@ -39,5 +39,6 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
/* SoC PSI-L endpoint maps */
extern struct psil_ep_map am654_ep_map;
extern struct psil_ep_map j721e_ep_map;
extern struct psil_ep_map am64_ep_map;
#endif /* K3_PSIL_PRIV_H_ */

2
drivers/dma/ti/k3-psil.c
View File

@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
soc_ep_map = &am64_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {

16
drivers/dma/ti/k3-psil.h
View File

@ -50,6 +50,15 @@ enum psil_endpoint_type {
* @channel_tpl: Desired throughput level for the channel
* @pdma_acc32: ACC32 must be enabled on the PDMA side
* @pdma_burst: BURST must be enabled on the PDMA side
* @mapped_channel_id: PKTDMA thread to channel mapping for mapped
* channels. The thread must be serviced by the specified
* channel if mapped_channel_id is >= 0 in case of PKTDMA
* @flow_start: PKTDMA flow range start of mapped channel. Unmapped
* channels use flow_id == chan_id
* @flow_num: PKTDMA flow count of mapped channel. Unmapped
* channels use flow_id == chan_id
* @default_flow_id: PKTDMA default (r)flow index of mapped channel.
* Must be within the flow range of the mapped channel.
*/
struct psil_endpoint_config {
enum psil_endpoint_type ep_type;
@ -63,5 +72,12 @@ struct psil_endpoint_config {
/* PDMA properties, valid for PSIL_EP_PDMA_* */
unsigned pdma_acc32:1;
unsigned pdma_burst:1;
/* PKTDMA mapped channel */
int mapped_channel_id;
/* PKTDMA tflow and rflow ranges for mapped channel */
u16 flow_start;
u16 flow_num;
u16 default_flow_id;
};
#endif /* K3_PSIL_H_ */

1003
drivers/dma/ti/k3-udma.c
View File

File diff suppressed because it is too large Load Diff

3
drivers/firmware/ti_sci.c
View File

@ -2466,6 +2466,9 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(
req.tx_orderid = params->tx_orderid;
req.fdepth = params->fdepth;
req.tx_sched_priority = params->tx_sched_priority;
req.tx_burst_size = params->tx_burst_size;
req.tx_tdtype = params->tx_tdtype;
req.extended_ch_type = params->extended_ch_type;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {

18
drivers/firmware/ti_sci.h
View File

@ -998,6 +998,9 @@ struct ti_sci_msg_psil_unpair {
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
* 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
* 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
* 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
*
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
*
@ -1058,6 +1061,18 @@ struct ti_sci_msg_psil_unpair {
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
* configuration to be programmed into the priority field of the channel's
* TCHAN_TST_SCHED register.
*
* @tx_burst_size: UDMAP transmit channel burst size configuration to be
* programmed into the tx_burst_size field of the TCHAN_TCFG register.
*
* @tx_tdtype: UDMAP transmit channel teardown type configuration to be
* programmed into the tdtype field of the TCHAN_TCFG register:
* 0 - Return immediately
* 1 - Wait for completion message from remote peer
*
* @extended_ch_type: Valid for BCDMA.
* 0 - the channel is split tx channel (tchan)
* 1 - the channel is block copy channel (bchan)
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
@ -1078,6 +1093,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
u8 tx_burst_size;
u8 tx_tdtype;
u8 extended_ch_type;
} __packed;
/**

10
drivers/mailbox/k3-sec-proxy.c
View File

@ -409,15 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
return 0;
}
/*
* Thread ID #4: ROM request
* Thread ID #5: ROM response, SYSFW notify
* Thread ID #6: SYSFW request response
* Thread ID #7: SYSFW request high priority
* Thread ID #8: SYSFW request low priority
* Thread ID #9: SYSFW notify response
*/
static const u32 am6x_valid_threads[] = { 4, 5, 6, 7, 8, 9, 11, 13 };
static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
static const struct k3_sec_proxy_desc am654_desc = {
.thread_count = 90,

18
drivers/mmc/am654_sdhci.c
View File

@ -470,6 +470,16 @@ const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
};
static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
.ops = &am654_sdhci_ops,
.flags = DLL_PRESENT | DLL_CALIB,
};
static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
.ops = &j721e_4bit_sdhci_ops,
.flags = IOMUX_PRESENT,
};
const struct soc_attr am654_sdhci_soc_attr[] = {
{ .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
{/* sentinel */}
@ -651,6 +661,14 @@ static const struct udevice_id am654_sdhci_ids[] = {
.compatible = "ti,j721e-sdhci-4bit",
.data = (ulong)&j721e_4bit_drv_data,
},
{
.compatible = "ti,am64-sdhci-8bit",
.data = (ulong)&sdhci_am64_8bit_drvdata,
},
{
.compatible = "ti,am64-sdhci-4bit",
.data = (ulong)&sdhci_am64_4bit_drvdata,
},
{ }
};

5
drivers/net/ti/am65-cpsw-nuss.c
View File

@ -26,7 +26,7 @@
#include "cpsw_mdio.h"
#define AM65_CPSW_CPSWNU_MAX_PORTS 2
#define AM65_CPSW_CPSWNU_MAX_PORTS 9
#define AM65_CPSW_SS_BASE 0x0
#define AM65_CPSW_SGMII_BASE 0x100
@ -719,11 +719,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
if (!port_id)
continue;
priv->port_id = port_id;
cpsw_common->ports[port_id].disabled = disabled;
if (disabled)
continue;
priv->port_id = port_id;
ret = am65_cpsw_ofdata_parse_phy(dev, node);
if (ret)
goto out;
@ -782,6 +782,7 @@ out:
static const struct udevice_id am65_cpsw_nuss_ids[] = {
{ .compatible = "ti,am654-cpsw-nuss" },
{ .compatible = "ti,j721e-cpsw-nuss" },
{ .compatible = "ti,am642-cpsw-nuss" },
{ }
};

24
drivers/ram/Kconfig
View File

@ -54,9 +54,19 @@ config K3_AM654_DDRSS
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
config K3_DDRSS
bool "Enable K3 DDRSS support"
depends on RAM
choice
depends on K3_DDRSS
prompt "K3 DDRSS Arch Support"
default K3_J721E_DDRSS if SOC_K3_J721E
default K3_AM64_DDRSS if SOC_K3_AM642
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
depends on RAM
help
The J721E DDR subsystem comprises DDR controller, DDR PHY and
wrapper logic to integrate these blocks in the device. The DDR
@ -65,6 +75,18 @@ config K3_J721E_DDRSS
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
config K3_AM64_DDRSS
bool "Enable AM64 DDRSS support"
help
The AM64 DDR subsystem comprises DDR controller, DDR PHY and
wrapper logic to integrate these blocks in the device. The DDR
subsystem is used to provide an interface to external SDRAM
devices which can be utilized for storing program or data.
Enabling this config adds support for the DDR memory controller
on AM642 family of SoCs.
endchoice
config IMXRT_SDRAM
bool "Enable i.MXRT SDRAM support"
depends on RAM

2
drivers/ram/Makefile
View File

@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o

108
drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h Normal file
View File

@ -0,0 +1,108 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_16BIT_IF_H
#define LPDDR4_16BIT_IF_H
#include <linux/types.h>
#define LPDDR4_INTR_MAX_CS (2U)
#define LPDDR4_INTR_CTL_REG_COUNT (423U)
#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
typedef enum {
LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U,
LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U,
LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U,
LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U,
LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U,
LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U,
LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U,
LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U,
LPDDR4_INTR_ECC_ERROR = 8U,
LPDDR4_INTR_LP_DONE = 9U,
LPDDR4_INTR_LP_TIMEOUT = 10U,
LPDDR4_INTR_PORT_TIMEOUT = 11U,
LPDDR4_INTR_RFIFO_TIMEOUT = 12U,
LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U,
LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U,
LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U,
LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U,
LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U,
LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U,
LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U,
LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U,
LPDDR4_INTR_USERIF_WRAP = 21U,
LPDDR4_INTR_USERIF_INVAL_SETTING = 22U,
LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U,
LPDDR4_INTR_MISC_SW_REQ_MODE = 24U,
LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U,
LPDDR4_INTR_MISC_TEMP_ALERT = 26U,
LPDDR4_INTR_MISC_REFRESH_STATUS = 27U,
LPDDR4_INTR_BIST_DONE = 28U,
LPDDR4_INTR_CRC = 29U,
LPDDR4_INTR_DFI_UPDATE_ERROR = 30U,
LPDDR4_INTR_DFI_PHY_ERROR = 31U,
LPDDR4_INTR_DFI_BUS_ERROR = 32U,
LPDDR4_INTR_DFI_STATE_CHANGE = 33U,
LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U,
LPDDR4_INTR_DFI_TIMEOUT = 35U,
LPDDR4_INTR_DIMM = 36U,
LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U,
LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U,
LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U,
LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U,
LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U,
LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U,
LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U,
LPDDR4_INTR_MC_INIT_DONE = 44U,
LPDDR4_INTR_INIT_POWER_ON_STATE = 45U,
LPDDR4_INTR_MRR_ERROR = 46U,
LPDDR4_INTR_MR_READ_DONE = 47U,
LPDDR4_INTR_MR_WRITE_DONE = 48U,
LPDDR4_INTR_PARITY_ERROR = 49U,
LPDDR4_INTR_LOR_BITS = 50U
} lpddr4_intr_ctlinterrupt;
typedef enum {
LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U,
LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U,
LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U,
LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U,
LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U,
LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U,
LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U,
LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U,
LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U,
LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U,
LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U,
LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U,
LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U,
LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U,
LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U,
LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U,
LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U,
LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U,
LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U,
LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U,
LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U,
LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U,
LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U,
LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U,
LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U,
LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U,
LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
} lpddr4_intr_phyindepinterrupt;
#endif /* LPDDR4_16BIT_IF_H */

14
drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h Normal file
View File

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_16BIT_OBJ_IF_H
#define LPDDR4_16BIT_OBJ_IF_H
#include "lpddr4_16bit_if.h"
#endif /* LPDDR4_16BIT_OBJ_IF_H */

15
drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_16BIT_STRUCTS_IF_H
#define LPDDR4_16BIT_STRUCTS_IF_H
#include <linux/types.h>
#include "lpddr4_16bit_if.h"
#endif /* LPDDR4_16BIT_STRUCTS_IF_H */

624
drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h Normal file
View File

@ -0,0 +1,624 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0
#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0
#define LPDDR4__DENALI_PHY_513_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0
#define LPDDR4__DENALI_PHY_514_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_515_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0
#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_516_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0
#define LPDDR4__DENALI_PHY_517_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0
#define LPDDR4__DENALI_PHY_518_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0
#define LPDDR4__DENALI_PHY_519_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0
#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0
#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0
#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
#define LPDDR4__DENALI_PHY_523_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0
#define LPDDR4__DENALI_PHY_524_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0
#define LPDDR4__DENALI_PHY_525_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0
#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0
#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
#define LPDDR4__DENALI_PHY_528_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_529_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529
#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0
#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0
#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0
#define LPDDR4__DENALI_PHY_532_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0
#define LPDDR4__DENALI_PHY_533_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0
#define LPDDR4__DENALI_PHY_534_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0
#define LPDDR4__DENALI_PHY_535_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0
#define LPDDR4__DENALI_PHY_536_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0
#define LPDDR4__DENALI_PHY_537_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0
#define LPDDR4__DENALI_PHY_538_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0
#define LPDDR4__DENALI_PHY_539_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0
#define LPDDR4__DENALI_PHY_540_READ_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH 30U
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0
#define LPDDR4__DENALI_PHY_541_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0
#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0
#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0
#define LPDDR4__DENALI_PHY_544_READ_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
#define LPDDR4__DENALI_PHY_545_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_546_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_547_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_548_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_549_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_550_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0
#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0
#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
#define LPDDR4__DENALI_PHY_553_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0
#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */

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drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1
#define LPDDR4__DENALI_PHY_769_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1
#define LPDDR4__DENALI_PHY_770_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
#define LPDDR4__DENALI_PHY_771_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
#define LPDDR4__DENALI_PHY_772_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1
#define LPDDR4__DENALI_PHY_773_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1
#define LPDDR4__DENALI_PHY_774_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774
#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774
#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1
#define LPDDR4__DENALI_PHY_775_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775
#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1
#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776
#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1
#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1
#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
#define LPDDR4__DENALI_PHY_779_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779
#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1
#define LPDDR4__DENALI_PHY_780_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780
#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1
#define LPDDR4__DENALI_PHY_781_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1
#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1
#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
#define LPDDR4__DENALI_PHY_784_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1
#define LPDDR4__DENALI_PHY_785_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785
#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1
#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1
#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1
#define LPDDR4__DENALI_PHY_788_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1
#define LPDDR4__DENALI_PHY_789_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1
#define LPDDR4__DENALI_PHY_790_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1
#define LPDDR4__DENALI_PHY_791_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1
#define LPDDR4__DENALI_PHY_792_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1
#define LPDDR4__DENALI_PHY_793_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1
#define LPDDR4__DENALI_PHY_794_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1
#define LPDDR4__DENALI_PHY_795_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1
#define LPDDR4__DENALI_PHY_796_READ_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH 30U
#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796
#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1
#define LPDDR4__DENALI_PHY_797_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797
#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797
#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1
#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1
#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1
#define LPDDR4__DENALI_PHY_800_READ_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
#define LPDDR4__DENALI_PHY_801_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x1F000000U
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_802_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_803_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_804_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_805_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1
#define LPDDR4__DENALI_PHY_806_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1
#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1
#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
#define LPDDR4__DENALI_PHY_809_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1
#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */

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drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031
#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032
#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036
#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041
#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH 30U
#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052
#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0x0707FFFFU
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x1F000000U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2
#define LPDDR4__DENALI_PHY_1063_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x0000010FU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */

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drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h Normal file
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drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_RW_MASKS_H_
#define LPDDR4_RW_MASKS_H_
#include <stdint.h>
extern u32 g_lpddr4_ddr_controller_rw_mask[423];
extern u32 g_lpddr4_pi_rw_mask[345];
extern u32 g_lpddr4_data_slice_0_rw_mask[126];
extern u32 g_lpddr4_data_slice_1_rw_mask[126];
extern u32 g_lpddr4_address_slice_0_rw_mask[43];
extern u32 g_lpddr4_address_slice_1_rw_mask[43];
extern u32 g_lpddr4_address_slice_2_rw_mask[43];
extern u32 g_lpddr4_phy_core_rw_mask[126];
#endif /* LPDDR4_RW_MASKS_H_ */

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drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h Normal file
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drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h Normal file
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drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h Normal file
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drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h Normal file
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drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_32BIT_IF_H
#define LPDDR4_32BIT_IF_H
#include <linux/types.h>
#define LPDDR4_INTR_MAX_CS (2U)
#define LPDDR4_INTR_CTL_REG_COUNT (459U)
#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U)
#define LPDDR4_INTR_PHY_REG_COUNT (1423U)
typedef enum {
LPDDR4_INTR_RESET_DONE = 0U,
LPDDR4_INTR_BUS_ACCESS_ERROR = 1U,
LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U,
LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U,
LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U,
LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U,
LPDDR4_INTR_ECC_SCRUB_DONE = 6U,
LPDDR4_INTR_ECC_SCRUB_ERROR = 7U,
LPDDR4_INTR_PORT_COMMAND_ERROR = 8U,
LPDDR4_INTR_MC_INIT_DONE = 9U,
LPDDR4_INTR_LP_DONE = 10U,
LPDDR4_INTR_BIST_DONE = 11U,
LPDDR4_INTR_WRAP_ERROR = 12U,
LPDDR4_INTR_INVALID_BURST_ERROR = 13U,
LPDDR4_INTR_RDLVL_ERROR = 14U,
LPDDR4_INTR_RDLVL_GATE_ERROR = 15U,
LPDDR4_INTR_WRLVL_ERROR = 16U,
LPDDR4_INTR_CA_TRAINING_ERROR = 17U,
LPDDR4_INTR_DFI_UPDATE_ERROR = 18U,
LPDDR4_INTR_MRR_ERROR = 19U,
LPDDR4_INTR_PHY_MASTER_ERROR = 20U,
LPDDR4_INTR_WRLVL_REQ = 21U,
LPDDR4_INTR_RDLVL_REQ = 22U,
LPDDR4_INTR_RDLVL_GATE_REQ = 23U,
LPDDR4_INTR_CA_TRAINING_REQ = 24U,
LPDDR4_INTR_LEVELING_DONE = 25U,
LPDDR4_INTR_PHY_ERROR = 26U,
LPDDR4_INTR_MR_READ_DONE = 27U,
LPDDR4_INTR_TEMP_CHANGE = 28U,
LPDDR4_INTR_TEMP_ALERT = 29U,
LPDDR4_INTR_SW_DQS_COMPLETE = 30U,
LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U,
LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U,
LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U,
LPDDR4_INTR_MR_WRITE_DONE = 34U,
LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U,
LPDDR4_INTR_DFI_INIT_STATE = 36U,
LPDDR4_INTR_DLL_RESYNC_DONE = 37U,
LPDDR4_INTR_TDFI_TO = 38U,
LPDDR4_INTR_DFS_DONE = 39U,
LPDDR4_INTR_DFS_STATUS = 40U,
LPDDR4_INTR_REFRESH_STATUS = 41U,
LPDDR4_INTR_ZQ_STATUS = 42U,
LPDDR4_INTR_SW_REQ_MODE = 43U,
LPDDR4_INTR_LOR_BITS = 44U
} lpddr4_intr_ctlinterrupt;
typedef enum {
LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U,
LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U,
LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U,
LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U,
LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U,
LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U,
LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U,
LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
} lpddr4_intr_phyindepinterrupt;
#endif /* LPDDR4_32BIT_IF_H */

14
drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h Normal file
View File

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_32BIT_OBJ_IF_H
#define LPDDR4_32BIT_OBJ_IF_H
#include "lpddr4_32bit_if.h"
#endif /* LPDDR4_32BIT_OBJ_IF_H */

15
drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h Normal file
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@ -0,0 +1,15 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_32BIT_STRUCTS_IF_H
#define LPDDR4_32BIT_STRUCTS_IF_H
#include <linux/types.h>
#include "lpddr4_32bit_if.h"
#endif /* LPDDR4_32BIT_STRUCTS_IF_H */

343
drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
View File

@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/**********************************************************************
* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
/*
* Cadence DDR Driver
*
* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
*
**********************************************************************
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
@ -32,16 +31,16 @@
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
@ -60,8 +59,8 @@
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
@ -80,8 +79,8 @@
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
@ -103,18 +102,18 @@
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
@ -138,8 +137,8 @@
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
@ -148,9 +147,9 @@
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
@ -161,50 +160,50 @@
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
@ -214,24 +213,24 @@
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
@ -244,8 +243,8 @@
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
@ -264,8 +263,8 @@
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
@ -296,112 +295,112 @@
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
@ -409,19 +408,19 @@
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
@ -441,13 +440,13 @@
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
@ -472,8 +471,8 @@
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
@ -500,8 +499,8 @@
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
@ -515,8 +514,8 @@
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
@ -526,8 +525,8 @@
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
@ -556,19 +555,19 @@
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
@ -578,11 +577,11 @@
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
@ -592,8 +591,8 @@
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U
@ -624,11 +623,11 @@
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
@ -639,13 +638,13 @@
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
@ -664,8 +663,8 @@
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@ -678,8 +677,8 @@
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@ -692,8 +691,8 @@
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@ -706,8 +705,8 @@
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@ -720,8 +719,8 @@
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@ -734,8 +733,8 @@
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
@ -754,8 +753,8 @@
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
@ -776,16 +775,16 @@
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
@ -806,8 +805,8 @@
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U

1545
drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h Normal file
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23
drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h Normal file
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@ -0,0 +1,23 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_RW_MASKS_H_
#define LPDDR4_RW_MASKS_H_
#include <stdint.h>
extern u32 g_lpddr4_ddr_controller_rw_mask[459];
extern u32 g_lpddr4_pi_rw_mask[300];
extern u32 g_lpddr4_data_slice_0_rw_mask[140];
extern u32 g_lpddr4_data_slice_1_rw_mask[140];
extern u32 g_lpddr4_data_slice_2_rw_mask[140];
extern u32 g_lpddr4_data_slice_3_rw_mask[140];
extern u32 g_lpddr4_address_slice_0_rw_mask[52];
extern u32 g_lpddr4_phy_core_rw_mask[143];
#endif /* LPDDR4_RW_MASKS_H_ */

1443
drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
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1363
drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
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1363
drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
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1363
drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
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7792
drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h Normal file
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1397
drivers/ram/k3-j721e/lpddr4_phy_core_macros.h → drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
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5396
drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h Normal file
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17
drivers/ram/k3-ddrss/Makefile Normal file
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@ -0,0 +1,17 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
#
obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
obj-$(CONFIG_K3_DDRSS) += lpddr4.o
ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/

102
drivers/ram/k3-ddrss/cps_drv_lpddr4.h Normal file
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@ -0,0 +1,102 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef CPS_DRV_H_
#define CPS_DRV_H_
#ifdef DEMO_TB
#include <cdn_demo.h>
#else
#include <asm/io.h>
#endif
#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
#define CPS_FLD_MASK(fld) (fld ## _MASK)
#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
(u32)(CPS_FLD_SHIFT(fld)), \
(u32)(reg_value)))
#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
(u32)(CPS_FLD_SHIFT(fld)), \
(u32)(reg_value), (u32)(value)))
#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
(u32)(CPS_FLD_MASK(fld)), \
(u32)(CPS_FLD_WOCLR(fld)), \
(u32)(reg_value)))
#ifdef CLR_USED
#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
(u32)(CPS_FLD_MASK(fld)), \
(u32)(CPS_FLD_WOSET(fld)), \
(u32)(CPS_FLD_WOCLR(fld)), \
(u32)(reg_value)))
#endif
static inline u32 cps_regread(volatile u32 *reg);
static inline u32 cps_regread(volatile u32 *reg)
{
return readl(reg);
}
static inline void cps_regwrite(volatile u32 *reg, u32 value);
static inline void cps_regwrite(volatile u32 *reg, u32 value)
{
writel(value, reg);
}
static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
{
u32 result = (reg_value & mask) >> shift;
return result;
}
static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
{
u32 new_value = (value << shift) & mask;
new_value = (reg_value & ~mask) | new_value;
return new_value;
}
static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
{
u32 new_value = reg_value;
if ((width == 1U) && (is_woclr == 0U))
new_value |= mask;
return new_value;
}
#ifdef CLR_USED
static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
{
u32 new_value = reg_value;
if ((width == 1U) && (is_woset == 0U))
new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
return new_value;
}
#endif /* CLR_USED */
#endif /* CPS_DRV_H_ */

289
drivers/ram/k3-j721e/k3-j721e-ddrss.c → drivers/ram/k3-ddrss/k3-ddrss.c
View File

@ -1,20 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Texas Instruments' J721E DDRSS driver
* Texas Instruments' K3 DDRSS driver
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <dm/device_compat.h>
#include <ram.h>
#include <hang.h>
#include <log.h>
#include <ram.h>
#include <asm/io.h>
#include <power-domain.h>
#include <wait_bit.h>
#include <dm/device_compat.h>
#include <power/regulator.h>
#include "lpddr4_obj_if.h"
#include "lpddr4_if.h"
@ -26,7 +27,10 @@
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
struct j721e_ddrss_desc {
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
void __iomem *ddrss_ctrl_mmr;
@ -37,13 +41,23 @@ struct j721e_ddrss_desc {
u32 ddr_freq1;
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
};
static LPDDR4_OBJ *driverdt;
static lpddr4_obj *driverdt;
static lpddr4_config config;
static lpddr4_privatedata pd;
static struct j721e_ddrss_desc *ddrss;
static struct k3_ddrss_desc *ddrss;
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
};
#define TH_MACRO_EXP(fld, str) (fld##str)
@ -56,22 +70,42 @@ static struct j721e_ddrss_desc *ddrss;
#define str(s) #s
#define xstr(s) str(s)
#define CTL_SHIFT 11
#define PHY_SHIFT 11
#define PI_SHIFT 10
#define CTL_SHIFT 11
#define PHY_SHIFT 11
#define PI_SHIFT 10
#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA
#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB
#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
char *i, *pstr= xstr(REG); offset = 0;\
char *i, *pstr = xstr(REG); offset = 0;\
for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
offset = offset * 10 + (*i - '0'); }\
offset = offset * 10 + (*i - '0'); } \
} while (0)
static void j721e_lpddr4_ack_freq_upd_req(void)
static u32 k3_lpddr4_read_ddr_type(void)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
}
dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
return dram_class;
}
static void k3_lpddr4_freq_update(void)
{
unsigned int req_type, counter;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
@ -83,7 +117,7 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
req_type = readl(ddrss->ddrss_ctrl_mmr +
CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
debug("%s: received freq change req: req type = %d, req no. = %d \n",
debug("%s: received freq change req: req type = %d, req no. = %d\n",
__func__, req_type, counter);
if (req_type == 1)
@ -110,15 +144,62 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
}
}
static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
lpddr4_infotype infotype)
static void k3_lpddr4_ack_freq_upd_req(void)
{
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
j721e_lpddr4_ack_freq_upd_req();
u32 dram_class;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
dram_class = k3_lpddr4_read_ddr_type();
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
k3_lpddr4_freq_update();
break;
default:
printf("Unrecognized dram_class cannot update frequency!\n");
}
}
static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
{
u32 dram_class;
int ret;
dram_class = k3_lpddr4_read_ddr_type();
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
/* Set to ddr_freq1 from DT for DDR4 */
ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
/* Set to bypass frequency for LPDDR4*/
ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
break;
default:
ret = -EINVAL;
printf("Unrecognized dram_class cannot init frequency!\n");
}
if (ret < 0)
dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
else
ret = 0;
return ret;
}
static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
lpddr4_infotype infotype)
{
if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
k3_lpddr4_ack_freq_upd_req();
}
static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
{
int ret;
@ -136,12 +217,24 @@ static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
return ret;
}
ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
&ddrss->vtt_supply);
if (ret) {
dev_dbg(ddrss->dev, "vtt-supply not found.\n");
} else {
ret = regulator_set_value(ddrss->vtt_supply, 3300000);
if (ret)
return ret;
dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
regulator_get_value(ddrss->vtt_supply));
}
return 0;
}
static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
{
struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
phys_addr_t reg;
int ret;
@ -193,42 +286,37 @@ static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
if (ret)
dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
/* Put DDR pll in bypass mode */
ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
if (ret)
dev_err(dev, "ddr clk bypass failed\n");
return ret;
}
void j721e_lpddr4_probe(void)
void k3_lpddr4_probe(void)
{
uint32_t status = 0U;
uint16_t configsize = 0U;
u32 status = 0U;
u16 configsize = 0U;
status = driverdt->probe(&config, &configsize);
if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
|| (configsize > SRAM_MAX)) {
printf("LPDDR4_Probe: FAIL\n");
printf("%s: FAIL\n", __func__);
hang();
} else {
debug("LPDDR4_Probe: PASS\n");
debug("%s: PASS\n", __func__);
}
}
void j721e_lpddr4_init(void)
void k3_lpddr4_init(void)
{
uint32_t status = 0U;
u32 status = 0U;
if ((sizeof(pd) != sizeof(lpddr4_privatedata))
|| (sizeof(pd) > SRAM_MAX)) {
printf("LPDDR4_Init: FAIL\n");
printf("%s: FAIL\n", __func__);
hang();
}
config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
status = driverdt->init(&pd, &config);
@ -236,140 +324,155 @@ void j721e_lpddr4_init(void)
(pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
(pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
(pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
printf("LPDDR4_Init: FAIL\n");
printf("%s: FAIL\n", __func__);
hang();
} else {
debug("LPDDR4_Init: PASS\n");
debug("%s: PASS\n", __func__);
}
}
void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
void populate_data_array_from_dt(struct reginitdata *reginit_data)
{
int ret, i;
ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
(u32 *) reginit_data->denalictlreg,
LPDDR4_CTL_REG_COUNT);
(u32 *)reginit_data->ctl_regs,
LPDDR4_INTR_CTL_REG_COUNT);
if (ret)
printf("Error reading ctrl data\n");
printf("Error reading ctrl data %d\n", ret);
for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
reginit_data->updatectlreg[i] = true;
for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
reginit_data->ctl_regs_offs[i] = i;
ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
(u32 *) reginit_data->denaliphyindepreg,
LPDDR4_PHY_INDEP_REG_COUNT);
(u32 *)reginit_data->pi_regs,
LPDDR4_INTR_PHY_INDEP_REG_COUNT);
if (ret)
printf("Error reading PI data\n");
for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
reginit_data->updatephyindepreg[i] = true;
for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
reginit_data->pi_regs_offs[i] = i;
ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
(u32 *) reginit_data->denaliphyreg,
LPDDR4_PHY_REG_COUNT);
(u32 *)reginit_data->phy_regs,
LPDDR4_INTR_PHY_REG_COUNT);
if (ret)
printf("Error reading PHY data\n");
printf("Error reading PHY data %d\n", ret);
for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
reginit_data->updatephyreg[i] = true;
for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
reginit_data->phy_regs_offs[i] = i;
}
void j721e_lpddr4_hardware_reg_init(void)
void k3_lpddr4_hardware_reg_init(void)
{
uint32_t status = 0U;
lpddr4_reginitdata reginitdata;
u32 status = 0U;
struct reginitdata reginitdata;
populate_data_array_from_dt(&reginitdata);
status = driverdt->writectlconfig(&pd, &reginitdata);
if (!status) {
status = driverdt->writephyindepconfig(&pd, &reginitdata);
}
if (!status) {
status = driverdt->writephyconfig(&pd, &reginitdata);
}
status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
reginitdata.ctl_regs_offs,
LPDDR4_INTR_CTL_REG_COUNT);
if (!status)
status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
reginitdata.pi_regs_offs,
LPDDR4_INTR_PHY_INDEP_REG_COUNT);
if (!status)
status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
reginitdata.phy_regs_offs,
LPDDR4_INTR_PHY_REG_COUNT);
if (status) {
printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
printf("%s: FAIL\n", __func__);
hang();
}
return;
}
void j721e_lpddr4_start(void)
void k3_lpddr4_start(void)
{
uint32_t status = 0U;
uint32_t regval = 0U;
uint32_t offset = 0U;
u32 status = 0U;
u32 regval = 0U;
u32 offset = 0U;
TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
printf("LPDDR4_StartTest: FAIL\n");
printf("%s: Pre start FAIL\n", __func__);
hang();
}
status = driverdt->start(&pd);
if (status > 0U) {
printf("LPDDR4_StartTest: FAIL\n");
printf("%s: FAIL\n", __func__);
hang();
}
status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
printf("LPDDR4_Start: FAIL\n");
printf("%s: Post start FAIL\n", __func__);
hang();
} else {
debug("LPDDR4_Start: PASS\n");
debug("%s: Post start PASS\n", __func__);
}
}
static int j721e_ddrss_probe(struct udevice *dev)
static int k3_ddrss_probe(struct udevice *dev)
{
int ret;
ddrss = dev_get_priv(dev);
debug("%s(dev=%p)\n", __func__, dev);
ret = j721e_ddrss_ofdata_to_priv(dev);
ret = k3_ddrss_ofdata_to_priv(dev);
if (ret)
return ret;
ddrss->dev = dev;
ret = j721e_ddrss_power_on(ddrss);
ret = k3_ddrss_power_on(ddrss);
if (ret)
return ret;
#ifdef CONFIG_K3_AM64_DDRSS
writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
#endif
driverdt = lpddr4_getinstance();
j721e_lpddr4_probe();
j721e_lpddr4_init();
j721e_lpddr4_hardware_reg_init();
j721e_lpddr4_start();
k3_lpddr4_probe();
k3_lpddr4_init();
k3_lpddr4_hardware_reg_init();
ret = k3_ddrss_init_freq(ddrss);
if (ret)
return ret;
k3_lpddr4_start();
return ret;
}
static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
{
return 0;
}
static struct ram_ops j721e_ddrss_ops = {
.get_info = j721e_ddrss_get_info,
static struct ram_ops k3_ddrss_ops = {
.get_info = k3_ddrss_get_info,
};
static const struct udevice_id j721e_ddrss_ids[] = {
static const struct udevice_id k3_ddrss_ids[] = {
{.compatible = "ti,am64-ddrss"},
{.compatible = "ti,j721e-ddrss"},
{}
};
U_BOOT_DRIVER(j721e_ddrss) = {
.name = "j721e_ddrss",
.id = UCLASS_RAM,
.of_match = j721e_ddrss_ids,
.ops = &j721e_ddrss_ops,
.probe = j721e_ddrss_probe,
.priv_auto = sizeof(struct j721e_ddrss_desc),
U_BOOT_DRIVER(k3_ddrss) = {
.name = "k3_ddrss",
.id = UCLASS_RAM,
.of_match = k3_ddrss_ids,
.ops = &k3_ddrss_ops,
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};

1079
drivers/ram/k3-ddrss/lpddr4.c Normal file
View File

File diff suppressed because it is too large Load Diff

73
drivers/ram/k3-ddrss/lpddr4.h Normal file
View File

@ -0,0 +1,73 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_H
#define LPDDR4_H
#include "lpddr4_ctl_regs.h"
#include "lpddr4_sanity.h"
#ifdef CONFIG_K3_AM64_DDRSS
#include "lpddr4_16bit.h"
#include "lpddr4_16bit_sanity.h"
#else
#include "lpddr4_32bit.h"
#include "lpddr4_32bit_sanity.h"
#endif
#ifdef REG_WRITE_VERIF
#include "lpddr4_ctl_regs_rw_masks.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define PRODUCT_ID (0x1046U)
#define LPDDR4_BIT_MASK (0x1U)
#define BYTE_MASK (0xffU)
#define NIBBLE_MASK (0xfU)
#define WORD_SHIFT (32U)
#define WORD_MASK (0xffffffffU)
#define SLICE_WIDTH (0x100)
#define CTL_OFFSET 0
#define PI_OFFSET (((u32)1) << 11)
#define PHY_OFFSET (((u32)1) << 12)
#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
#define PLL_READY (0x3U)
#define IO_CALIB_DONE ((u32)0x1U << 23U)
#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
#define IO_CALIB_STATE ((u32)0xBU << 28U)
#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
#define CDN_TRUE 1U
#define CDN_FALSE 0U
void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
#ifdef __cplusplus
}
#endif
#endif /* LPDDR4_H */

396
drivers/ram/k3-ddrss/lpddr4_16bit.c Normal file
View File

@ -0,0 +1,396 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
#include "cps_drv_lpddr4.h"
#include "lpddr4_ctl_regs.h"
#include "lpddr4_if.h"
#include "lpddr4.h"
#include "lpddr4_structs_if.h"
static u32 ctlintmap[51][3] = {
{ 0, 0, 7 },
{ 1, 0, 8 },
{ 2, 0, 9 },
{ 3, 0, 14 },
{ 4, 0, 15 },
{ 5, 0, 16 },
{ 6, 0, 17 },
{ 7, 0, 19 },
{ 8, 1, 0 },
{ 9, 2, 0 },
{ 10, 2, 3 },
{ 11, 3, 0 },
{ 12, 4, 0 },
{ 13, 5, 11 },
{ 14, 5, 12 },
{ 15, 5, 13 },
{ 16, 5, 14 },
{ 17, 5, 15 },
{ 18, 6, 0 },
{ 19, 6, 1 },
{ 20, 6, 2 },
{ 21, 6, 6 },
{ 22, 6, 7 },
{ 23, 7, 3 },
{ 24, 7, 4 },
{ 25, 7, 5 },
{ 26, 7, 6 },
{ 27, 7, 7 },
{ 28, 8, 0 },
{ 29, 9, 0 },
{ 30, 10, 0 },
{ 31, 10, 1 },
{ 32, 10, 2 },
{ 33, 10, 3 },
{ 34, 10, 4 },
{ 35, 10, 5 },
{ 36, 11, 0 },
{ 37, 12, 0 },
{ 38, 12, 1 },
{ 39, 12, 2 },
{ 40, 12, 3 },
{ 41, 12, 4 },
{ 42, 12, 5 },
{ 43, 13, 0 },
{ 44, 13, 1 },
{ 45, 13, 3 },
{ 46, 14, 0 },
{ 47, 14, 2 },
{ 48, 14, 3 },
{ 49, 15, 2 },
{ 50, 16, 0 },
};
static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
{
u32 result = 0U;
u32 regval = 0U;
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
return result;
}
u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
{
u32 result = 0U;
result = lpddr4_getctlinterruptmasksf(pd, mask);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
}
return result;
}
u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
{
u32 result;
u32 regval = 0;
const u64 ui64one = 1ULL;
const u32 ui32irqcount = (u32)32U;
result = lpddr4_setctlinterruptmasksf(pd, mask);
if ((result == (u32)0) && (ui32irqcount < 64U)) {
if (*mask >= (ui64one << ui32irqcount))
result = (u32)EINVAL;
}
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
}
return result;
}
static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
{
if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
else if (intr == LPDDR4_INTR_BIST_DONE)
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
else if (intr == LPDDR4_INTR_PARITY_ERROR)
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
else
*ctlmasterintflag = (u32)1U;
}
static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
{
if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
else
lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
}
static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
{
if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
else
lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
}
u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
{
u32 result;
u32 ctlmasterirqstatus = 0U;
u32 ctlgrpirqstatus = 0U;
u32 ctlmasterintflag = 0U;
result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
(((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
(ctlmasterintflag == (u32)0))
*irqstatus = true;
else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
(ctlmasterintflag == (u32)1U))
*irqstatus = true;
else
*irqstatus = false;
}
}
return result;
}
static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
{
u32 regval = 0;
if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
} else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
} else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
} else {
}
}
static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
{
u32 regval = 0;
if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
} else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
} else {
lpddr4_ackctlinterrupt_4(ctlregbase, intr);
}
}
static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
{
u32 regval = 0;
if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
} else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
} else {
lpddr4_ackctlinterrupt_3(ctlregbase, intr);
}
}
u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
{
u32 result;
result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
else
lpddr4_ackctlinterrupt_2(ctlregbase, intr);
}
return result;
}
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
{
u32 regval;
u32 errbitmask = 0U;
u32 snum;
volatile u32 *regaddress;
regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
for (snum = 0U; snum < DSLICE_NUM; snum++) {
regval = CPS_REG_READ(regaddress);
if ((regval & errbitmask) != 0U) {
debuginfo->wrlvlerror = CDN_TRUE;
*errfoundptr = true;
}
regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
}
}
u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
{
u32 result = 0U;
bool errorfound = false;
result = lpddr4_getdebuginitinfosf(pd, debuginfo);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
lpddr4_setsettings(ctlregbase, errorfound);
errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
}
if (errorfound == (bool)true)
result = (u32)EPROTO;
return result;
}
u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
{
u32 result = 0U;
result = lpddr4_getreducmodesf(pd, mode);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
*mode = LPDDR4_REDUC_ON;
else
*mode = LPDDR4_REDUC_OFF;
}
return result;
}
u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
{
u32 result = 0U;
u32 regval = 0U;
result = lpddr4_setreducmodesf(pd, mode);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
}
return result;
}
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
{
u32 lowerdata;
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
u32 result = (u32)0;
if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
*mmrvalue = (u64)0;
result = (u32)EIO;
} else {
*mrrstatus = (u8)0;
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
}
return result;
}
#ifdef REG_WRITE_VERIF
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
{
u32 rwmask = 0U;
switch (dslicenum) {
case 0:
if (arrayoffset < DSLICE0_REG_COUNT)
rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
break;
default:
if (arrayoffset < DSLICE1_REG_COUNT)
rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
break;
}
return rwmask;
}
#endif
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
{
u32 result = 0U;
result = lpddr4_geteccenablesf(pd, eccparam);
if (result == (u32)0) {
*eccparam = LPDDR4_ECC_DISABLED;
result = (u32)EOPNOTSUPP;
}
return result;
}
u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
{
u32 result = 0U;
result = lpddr4_seteccenablesf(pd, eccparam);
if (result == (u32)0)
result = (u32)EOPNOTSUPP;
return result;
}

33
drivers/ram/k3-ddrss/lpddr4_16bit.h Normal file
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@ -0,0 +1,33 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_16BIT_H
#define LPDDR4_16BIT_H
#define DSLICE_NUM (2U)
#define ASLICE_NUM (3U)
#ifdef __cplusplus
extern "C" {
#endif
#define DSLICE0_REG_COUNT (126U)
#define DSLICE1_REG_COUNT (126U)
#define ASLICE0_REG_COUNT (42U)
#define ASLICE1_REG_COUNT (42U)
#define ASLICE2_REG_COUNT (42U)
#define PHY_CORE_REG_COUNT (126U)
#define GRP_SHIFT 1
#define INT_SHIFT 2
#ifdef __cplusplus
}
#endif
#endif /* LPDDR4_16BIT_H */

1309
drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c Normal file
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File diff suppressed because it is too large Load Diff

257
drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_16BIT_SANITY_H
#define LPDDR4_16BIT_SANITY_H
#include <errno.h>
#include <linux/types.h>
#include <lpddr4_if.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (irqstatus == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
(intr != LPDDR4_INTR_ECC_ERROR) &&
(intr != LPDDR4_INTR_LP_DONE) &&
(intr != LPDDR4_INTR_LP_TIMEOUT) &&
(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
(intr != LPDDR4_INTR_USERIF_WRAP) &&
(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
(intr != LPDDR4_INTR_BIST_DONE) &&
(intr != LPDDR4_INTR_CRC) &&
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
(intr != LPDDR4_INTR_DIMM) &&
(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
(intr != LPDDR4_INTR_MRR_ERROR) &&
(intr != LPDDR4_INTR_MR_READ_DONE) &&
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
(intr != LPDDR4_INTR_PARITY_ERROR) &&
(intr != LPDDR4_INTR_LOR_BITS)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
(intr != LPDDR4_INTR_ECC_ERROR) &&
(intr != LPDDR4_INTR_LP_DONE) &&
(intr != LPDDR4_INTR_LP_TIMEOUT) &&
(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
(intr != LPDDR4_INTR_USERIF_WRAP) &&
(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
(intr != LPDDR4_INTR_BIST_DONE) &&
(intr != LPDDR4_INTR_CRC) &&
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
(intr != LPDDR4_INTR_DIMM) &&
(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
(intr != LPDDR4_INTR_MRR_ERROR) &&
(intr != LPDDR4_INTR_MR_READ_DONE) &&
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
(intr != LPDDR4_INTR_PARITY_ERROR) &&
(intr != LPDDR4_INTR_LOR_BITS)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (irqstatus == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
) {
ret = EINVAL;
} else {
}
return ret;
}
#ifdef __cplusplus
}
#endif
#endif /* LPDDR4_16BIT_SANITY_H */

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drivers/ram/k3-ddrss/lpddr4_32bit.c Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <errno.h>
#include "cps_drv_lpddr4.h"
#include "lpddr4_ctl_regs.h"
#include "lpddr4_if.h"
#include "lpddr4.h"
#include "lpddr4_structs_if.h"
static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound);
u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
{
u32 result = 0U;
u32 regval = 0U;
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
return result;
}
u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
{
u32 result = 0U;
u32 lowermask = 0U;
result = lpddr4_getctlinterruptmasksf(pd, mask);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG))));
*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG))));
*mask = (u64)((*mask << WORD_SHIFT) | lowermask);
}
return result;
}
u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
{
u32 result;
u32 regval = 0;
const u64 ui64one = 1ULL;
const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U;
result = lpddr4_setctlinterruptmasksf(pd, mask);
if ((result == (u32)0) && (ui32irqcount < 64U)) {
if (*mask >= (ui64one << ui32irqcount))
result = (u32)EINVAL;
}
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = (u32)(*mask & WORD_MASK);
regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK);
regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
}
return result;
}
u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
{
u32 result;
u32 ctlirqstatus = 0;
u32 fieldshift = 0;
result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
if ((u32)intr >= (u32)WORD_SHIFT) {
ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG));
fieldshift = (u32)intr - ((u32)WORD_SHIFT);
} else {
ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG));
fieldshift = (u32)intr;
}
if (fieldshift < WORD_SHIFT) {
if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U)
*irqstatus = true;
else
*irqstatus = false;
}
}
return result;
}
u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
{
u32 result = 0;
u32 regval = 0;
u32 localinterrupt = (u32)intr;
result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
if (localinterrupt > WORD_SHIFT) {
localinterrupt = (localinterrupt - (u32)WORD_SHIFT);
regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval);
} else {
regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval);
}
}
return result;
}
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
{
u32 regval;
u32 errbitmask = 0U;
u32 snum;
volatile u32 *regaddress;
regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK);
for (snum = 0U; snum < DSLICE_NUM; snum++) {
regval = CPS_REG_READ(regaddress);
if ((regval & errbitmask) != 0U) {
debuginfo->wrlvlerror = CDN_TRUE;
*errfoundptr = true;
}
regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
}
}
static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound)
{
volatile u32 *regaddress;
u32 snum = 0U;
u32 errbitmask = 0U;
u32 regval = 0U;
if (*errorfound == (bool)false) {
regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress));
if ((regval & errbitmask) != RX_CAL_DONE) {
debuginfo->rxoffseterror = (u8)true;
*errorfound = true;
}
regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
}
}
}
u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
{
u32 result = 0U;
bool errorfound = false;
result = lpddr4_getdebuginitinfosf(pd, debuginfo);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
lpddr4_setsettings(ctlregbase, errorfound);
lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
}
if (errorfound == (bool)true)
result = (u32)EPROTO;
return result;
}
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
{
u32 result = 0U;
u32 fldval = 0U;
result = lpddr4_geteccenablesf(pd, eccparam);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)));
switch (fldval) {
case 3:
*eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
break;
case 2:
*eccparam = LPDDR4_ECC_ERR_DETECT;
break;
case 1:
*eccparam = LPDDR4_ECC_ENABLED;
break;
default:
*eccparam = LPDDR4_ECC_DISABLED;
break;
}
}
return result;
}
u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
{
u32 result = 0U;
u32 regval = 0U;
result = lpddr4_seteccenablesf(pd, eccparam);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
}
return result;
}
u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
{
u32 result = 0U;
result = lpddr4_getreducmodesf(pd, mode);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U)
*mode = LPDDR4_REDUC_ON;
else
*mode = LPDDR4_REDUC_OFF;
}
return result;
}
u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
{
u32 result = 0U;
u32 regval = 0U;
result = lpddr4_setreducmodesf(pd, mode);
if (result == (u32)0) {
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode);
CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
}
return result;
}
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
{
u32 lowerdata;
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
u32 result = (u32)0;
if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
*mmrvalue = (u64)0;
result = (u32)EIO;
} else {
*mrrstatus = (u8)0;
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
*mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
}
return result;
}
#ifdef REG_WRITE_VERIF
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
{
u32 rwmask = 0U;
switch (dslicenum) {
case 0:
if (arrayoffset < DSLICE0_REG_COUNT)
rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
break;
case 1:
if (arrayoffset < DSLICE1_REG_COUNT)
rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
break;
case 2:
if (arrayoffset < DSLICE2_REG_COUNT)
rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset];
break;
default:
if (arrayoffset < DSLICE3_REG_COUNT)
rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset];
break;
}
return rwmask;
}
#endif

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drivers/ram/k3-ddrss/lpddr4_32bit.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_32BIT_H
#define LPDDR4_32BIT_H
#define DSLICE_NUM (4U)
#define ASLICE_NUM (1U)
#ifdef __cplusplus
extern "C" {
#endif
#define DSLICE0_REG_COUNT (140U)
#define DSLICE1_REG_COUNT (140U)
#define DSLICE2_REG_COUNT (140U)
#define DSLICE3_REG_COUNT (140U)
#define ASLICE0_REG_COUNT (52U)
#define PHY_CORE_REG_COUNT (140U)
#ifdef __cplusplus
}
#endif
#endif /* LPDDR4_32BIT_H */

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drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c Normal file
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drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h Normal file
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/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_32BIT_SANITY_H
#define LPDDR4_32BIT_SANITY_H
#include <errno.h>
#include <linux/types.h>
#include <lpddr4_if.h>
#ifdef __cplusplus
extern "C" {
#endif
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (irqstatus == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_RESET_DONE) &&
(intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
(intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
(intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
(intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
(intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
(intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
(intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
(intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
(intr != LPDDR4_INTR_LP_DONE) &&
(intr != LPDDR4_INTR_BIST_DONE) &&
(intr != LPDDR4_INTR_WRAP_ERROR) &&
(intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
(intr != LPDDR4_INTR_RDLVL_ERROR) &&
(intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
(intr != LPDDR4_INTR_WRLVL_ERROR) &&
(intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
(intr != LPDDR4_INTR_MRR_ERROR) &&
(intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
(intr != LPDDR4_INTR_WRLVL_REQ) &&
(intr != LPDDR4_INTR_RDLVL_REQ) &&
(intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
(intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
(intr != LPDDR4_INTR_LEVELING_DONE) &&
(intr != LPDDR4_INTR_PHY_ERROR) &&
(intr != LPDDR4_INTR_MR_READ_DONE) &&
(intr != LPDDR4_INTR_TEMP_CHANGE) &&
(intr != LPDDR4_INTR_TEMP_ALERT) &&
(intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
(intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
(intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
(intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
(intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
(intr != LPDDR4_INTR_DFI_INIT_STATE) &&
(intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
(intr != LPDDR4_INTR_TDFI_TO) &&
(intr != LPDDR4_INTR_DFS_DONE) &&
(intr != LPDDR4_INTR_DFS_STATUS) &&
(intr != LPDDR4_INTR_REFRESH_STATUS) &&
(intr != LPDDR4_INTR_ZQ_STATUS) &&
(intr != LPDDR4_INTR_SW_REQ_MODE) &&
(intr != LPDDR4_INTR_LOR_BITS)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_RESET_DONE) &&
(intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
(intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
(intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
(intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
(intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
(intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
(intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
(intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
(intr != LPDDR4_INTR_LP_DONE) &&
(intr != LPDDR4_INTR_BIST_DONE) &&
(intr != LPDDR4_INTR_WRAP_ERROR) &&
(intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
(intr != LPDDR4_INTR_RDLVL_ERROR) &&
(intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
(intr != LPDDR4_INTR_WRLVL_ERROR) &&
(intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
(intr != LPDDR4_INTR_MRR_ERROR) &&
(intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
(intr != LPDDR4_INTR_WRLVL_REQ) &&
(intr != LPDDR4_INTR_RDLVL_REQ) &&
(intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
(intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
(intr != LPDDR4_INTR_LEVELING_DONE) &&
(intr != LPDDR4_INTR_PHY_ERROR) &&
(intr != LPDDR4_INTR_MR_READ_DONE) &&
(intr != LPDDR4_INTR_TEMP_CHANGE) &&
(intr != LPDDR4_INTR_TEMP_ALERT) &&
(intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
(intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
(intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
(intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
(intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
(intr != LPDDR4_INTR_DFI_INIT_STATE) &&
(intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
(intr != LPDDR4_INTR_TDFI_TO) &&
(intr != LPDDR4_INTR_DFS_DONE) &&
(intr != LPDDR4_INTR_DFS_STATUS) &&
(intr != LPDDR4_INTR_REFRESH_STATUS) &&
(intr != LPDDR4_INTR_ZQ_STATUS) &&
(intr != LPDDR4_INTR_SW_REQ_MODE) &&
(intr != LPDDR4_INTR_LOR_BITS)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (irqstatus == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
) {
ret = EINVAL;
} else {
}
return ret;
}
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
{
u32 ret = 0;
if (pd == NULL) {
ret = EINVAL;
} else if (
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
) {
ret = EINVAL;
} else {
}
return ret;
}
#ifdef __cplusplus
}
#endif
#endif /* LPDDR4_32BIT_SANITY_H */

144
drivers/ram/k3-ddrss/lpddr4_if.h Normal file
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@ -0,0 +1,144 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef LPDDR4_IF_H
#define LPDDR4_IF_H
#include <linux/types.h>
#ifdef CONFIG_K3_AM64_DDRSS
#include <lpddr4_16bit_if.h>
#else
#include <lpddr4_32bit_if.h>
#endif
typedef struct lpddr4_config_s lpddr4_config;
typedef struct lpddr4_privatedata_s lpddr4_privatedata;
typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
typedef enum {
LPDDR4_CTL_REGS = 0U,
LPDDR4_PHY_REGS = 1U,
LPDDR4_PHY_INDEP_REGS = 2U
} lpddr4_regblock;
typedef enum {
LPDDR4_DRV_NONE = 0U,
LPDDR4_DRV_SOC_PLL_UPDATE = 1U
} lpddr4_infotype;
typedef enum {
LPDDR4_LPI_PD_WAKEUP_FN = 0U,
LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
} lpddr4_lpiwakeupparam;
typedef enum {
LPDDR4_REDUC_ON = 0U,
LPDDR4_REDUC_OFF = 1U
} lpddr4_reducmode;
typedef enum {
LPDDR4_ECC_DISABLED = 0U,
LPDDR4_ECC_ENABLED = 1U,
LPDDR4_ECC_ERR_DETECT = 2U,
LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
} lpddr4_eccenable;
typedef enum {
LPDDR4_DBI_RD_ON = 0U,
LPDDR4_DBI_RD_OFF = 1U,
LPDDR4_DBI_WR_ON = 2U,
LPDDR4_DBI_WR_OFF = 3U
} lpddr4_dbimode;
typedef enum {
LPDDR4_FSP_0 = 0U,
LPDDR4_FSP_1 = 1U,
LPDDR4_FSP_2 = 2U
} lpddr4_ctlfspnum;
typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype);
typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect);
typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect);
u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize);
u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg);
u32 lpddr4_start(const lpddr4_privatedata *pd);
u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask);
u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask);
u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask);
u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask);
u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off);
u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off);
u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
#endif /* LPDDR4_IF_H */

51
drivers/ram/k3-ddrss/lpddr4_obj_if.c Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "lpddr4_obj_if.h"
lpddr4_obj *lpddr4_getinstance(void)
{
static lpddr4_obj driver = {
.probe = lpddr4_probe,
.init = lpddr4_init,
.start = lpddr4_start,
.readreg = lpddr4_readreg,
.writereg = lpddr4_writereg,
.getmmrregister = lpddr4_getmmrregister,
.setmmrregister = lpddr4_setmmrregister,
.writectlconfig = lpddr4_writectlconfig,
.writephyconfig = lpddr4_writephyconfig,
.writephyindepconfig = lpddr4_writephyindepconfig,
.readctlconfig = lpddr4_readctlconfig,
.readphyconfig = lpddr4_readphyconfig,
.readphyindepconfig = lpddr4_readphyindepconfig,
.getctlinterruptmask = lpddr4_getctlinterruptmask,
.setctlinterruptmask = lpddr4_setctlinterruptmask,
.checkctlinterrupt = lpddr4_checkctlinterrupt,
.ackctlinterrupt = lpddr4_ackctlinterrupt,
.getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
.setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
.checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
.ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
.getdebuginitinfo = lpddr4_getdebuginitinfo,
.getlpiwakeuptime = lpddr4_getlpiwakeuptime,
.setlpiwakeuptime = lpddr4_setlpiwakeuptime,
.geteccenable = lpddr4_geteccenable,
.seteccenable = lpddr4_seteccenable,
.getreducmode = lpddr4_getreducmode,
.setreducmode = lpddr4_setreducmode,
.getdbireadmode = lpddr4_getdbireadmode,
.getdbiwritemode = lpddr4_getdbiwritemode,
.setdbimode = lpddr4_setdbimode,
.getrefreshrate = lpddr4_getrefreshrate,
.setrefreshrate = lpddr4_setrefreshrate,
.refreshperchipselect = lpddr4_refreshperchipselect,
};
return &driver;
}

86
drivers/ram/k3-ddrss/lpddr4_obj_if.h Normal file
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@ -0,0 +1,86 @@
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Cadence DDR Driver
*
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef lpddr4_obj_if_h
#define lpddr4_obj_if_h
#include "lpddr4_if.h"
typedef struct lpddr4_obj_s {
u32 (*probe)(const lpddr4_config *config, u16 *configsize);
u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
u32 (*start)(const lpddr4_privatedata *pd);
u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
} lpddr4_obj;
extern lpddr4_obj *lpddr4_getinstance(void);
#endif /* lpddr4_obj_if_h */

0
drivers/ram/k3-j721e/lpddr4_private.h → drivers/ram/k3-ddrss/lpddr4_private.h
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