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https://github.com/brain-hackers/u-boot-brain
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9f9b5c1c16
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
24 lines
692 B
C
24 lines
692 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_RW_MASKS_H_
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#define LPDDR4_RW_MASKS_H_
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#include <stdint.h>
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extern u32 g_lpddr4_ddr_controller_rw_mask[423];
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extern u32 g_lpddr4_pi_rw_mask[345];
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extern u32 g_lpddr4_data_slice_0_rw_mask[126];
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extern u32 g_lpddr4_data_slice_1_rw_mask[126];
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extern u32 g_lpddr4_address_slice_0_rw_mask[43];
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extern u32 g_lpddr4_address_slice_1_rw_mask[43];
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extern u32 g_lpddr4_address_slice_2_rw_mask[43];
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extern u32 g_lpddr4_phy_core_rw_mask[126];
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#endif /* LPDDR4_RW_MASKS_H_ */
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