ram: k3-ddrss: Introduce support for AM642 SoCs
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach
Lokesh Vutla
parent
a8c13c777e
commit
9f9b5c1c16
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@ -62,6 +62,9 @@ choice
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depends on K3_DDRSS
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prompt "K3 DDRSS Arch Support"
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default K3_J721E_DDRSS if SOC_K3_J721E
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default K3_AM64_DDRSS if SOC_K3_AM642
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config K3_J721E_DDRSS
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bool "Enable J721E DDRSS support"
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help
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@ -72,6 +75,16 @@ config K3_J721E_DDRSS
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Enabling this config adds support for the DDR memory controller
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on J721E family of SoCs.
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config K3_AM64_DDRSS
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bool "Enable AM64 DDRSS support"
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help
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The AM64 DDR subsystem comprises DDR controller, DDR PHY and
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wrapper logic to integrate these blocks in the device. The DDR
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subsystem is used to provide an interface to external SDRAM
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devices which can be utilized for storing program or data.
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Enabling this config adds support for the DDR memory controller
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on AM642 family of SoCs.
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endchoice
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config IMXRT_SDRAM
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@ -0,0 +1,108 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_16BIT_IF_H
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#define LPDDR4_16BIT_IF_H
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#include <linux/types.h>
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#define LPDDR4_INTR_MAX_CS (2U)
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#define LPDDR4_INTR_CTL_REG_COUNT (423U)
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#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
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#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
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typedef enum {
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LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U,
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LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U,
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LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U,
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LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U,
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LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U,
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LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U,
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LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U,
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LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U,
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LPDDR4_INTR_ECC_ERROR = 8U,
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LPDDR4_INTR_LP_DONE = 9U,
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LPDDR4_INTR_LP_TIMEOUT = 10U,
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LPDDR4_INTR_PORT_TIMEOUT = 11U,
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LPDDR4_INTR_RFIFO_TIMEOUT = 12U,
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LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U,
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LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U,
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LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U,
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LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U,
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LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U,
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LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U,
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LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U,
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LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U,
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LPDDR4_INTR_USERIF_WRAP = 21U,
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LPDDR4_INTR_USERIF_INVAL_SETTING = 22U,
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LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U,
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LPDDR4_INTR_MISC_SW_REQ_MODE = 24U,
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LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U,
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LPDDR4_INTR_MISC_TEMP_ALERT = 26U,
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LPDDR4_INTR_MISC_REFRESH_STATUS = 27U,
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LPDDR4_INTR_BIST_DONE = 28U,
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LPDDR4_INTR_CRC = 29U,
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LPDDR4_INTR_DFI_UPDATE_ERROR = 30U,
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LPDDR4_INTR_DFI_PHY_ERROR = 31U,
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LPDDR4_INTR_DFI_BUS_ERROR = 32U,
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LPDDR4_INTR_DFI_STATE_CHANGE = 33U,
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LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U,
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LPDDR4_INTR_DFI_TIMEOUT = 35U,
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LPDDR4_INTR_DIMM = 36U,
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LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U,
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LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U,
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LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U,
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LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U,
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LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U,
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LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U,
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LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U,
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LPDDR4_INTR_MC_INIT_DONE = 44U,
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LPDDR4_INTR_INIT_POWER_ON_STATE = 45U,
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LPDDR4_INTR_MRR_ERROR = 46U,
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LPDDR4_INTR_MR_READ_DONE = 47U,
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LPDDR4_INTR_MR_WRITE_DONE = 48U,
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LPDDR4_INTR_PARITY_ERROR = 49U,
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LPDDR4_INTR_LOR_BITS = 50U
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} lpddr4_intr_ctlinterrupt;
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typedef enum {
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LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
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LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U,
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LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U,
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LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U,
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LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U,
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LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U,
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LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U,
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LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U,
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LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U,
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LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U,
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LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U,
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LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U,
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LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
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LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U,
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LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U,
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LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U,
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LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U,
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LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U,
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LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U,
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LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U,
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LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U,
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LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U,
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LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
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} lpddr4_intr_phyindepinterrupt;
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#endif /* LPDDR4_16BIT_IF_H */
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_16BIT_OBJ_IF_H
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#define LPDDR4_16BIT_OBJ_IF_H
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#include "lpddr4_16bit_if.h"
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#endif /* LPDDR4_16BIT_OBJ_IF_H */
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@ -0,0 +1,15 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_16BIT_STRUCTS_IF_H
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#define LPDDR4_16BIT_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_16bit_if.h"
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#endif /* LPDDR4_16BIT_STRUCTS_IF_H */
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@ -0,0 +1,624 @@
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/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
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#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
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#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000107FFU
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#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000107FFU
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
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#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512
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#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
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#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512
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#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0
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#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
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#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
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#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512
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#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0
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#define LPDDR4__DENALI_PHY_513_READ_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
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#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
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#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513
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#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0
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#define LPDDR4__DENALI_PHY_514_READ_MASK 0x0FFFFFFFU
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#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x0FFFFFFFU
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
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#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514
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#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
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#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514
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#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
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#define LPDDR4__DENALI_PHY_515_READ_MASK 0xFF7F07FFU
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#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0xFF7F07FFU
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515
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#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
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#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
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#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
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#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
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#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
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#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
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#define LPDDR4__DENALI_PHY_516_READ_MASK 0x01000707U
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#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x01000707U
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
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#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516
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#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
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#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516
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#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
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#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
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#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
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#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
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#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
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#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
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#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516
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#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0
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#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_517_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_518_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518
|
||||
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_519_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_523_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_524_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_525_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_528_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_529_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_532_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_533_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_534_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_535_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_536_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_537_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_538_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_539_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_540_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_541_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_544_READ_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_545_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_546_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_547_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_548_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_549_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_550_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_553_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0
|
||||
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
|
||||
|
|
@ -0,0 +1,624 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
|
||||
#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
|
||||
|
||||
#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_769_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_770_READ_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_771_READ_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_772_READ_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_773_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_774_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774
|
||||
#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_775_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_779_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_780_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_781_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_784_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_785_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_788_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_789_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_790_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_791_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_792_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_793_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_794_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_795_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_796_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_797_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_800_READ_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_801_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_802_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_803_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_804_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_805_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_806_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_809_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1
|
||||
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
|
||||
|
|
@ -0,0 +1,624 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
|
||||
#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024
|
||||
#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024
|
||||
#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024
|
||||
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025
|
||||
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
|
||||
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028
|
||||
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028
|
||||
#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029
|
||||
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK 0x00000300U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030
|
||||
#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH 27U
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031
|
||||
#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032
|
||||
#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034
|
||||
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035
|
||||
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036
|
||||
#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038
|
||||
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039
|
||||
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040
|
||||
#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH 32U
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043
|
||||
#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1044_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050
|
||||
#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH 20U
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051
|
||||
#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH 30U
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052
|
||||
#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3F3F03FFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053
|
||||
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053
|
||||
#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053
|
||||
#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F0F3F3FU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054
|
||||
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x0000003FU
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055
|
||||
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056_READ_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0x0707FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x07000000U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056
|
||||
#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x1F07FF1FU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x0000001FU
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x1F000000U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
|
||||
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058
|
||||
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059
|
||||
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060
|
||||
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x001F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061
|
||||
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x000F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062
|
||||
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063_READ_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0xFF3F07FFU
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x0103FFFFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064
|
||||
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065
|
||||
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x0000010FU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2
|
||||
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U
|
||||
#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066
|
||||
#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
|
||||
|
||||
#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_RW_MASKS_H_
|
||||
#define LPDDR4_RW_MASKS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern u32 g_lpddr4_ddr_controller_rw_mask[423];
|
||||
extern u32 g_lpddr4_pi_rw_mask[345];
|
||||
extern u32 g_lpddr4_data_slice_0_rw_mask[126];
|
||||
extern u32 g_lpddr4_data_slice_1_rw_mask[126];
|
||||
extern u32 g_lpddr4_address_slice_0_rw_mask[43];
|
||||
extern u32 g_lpddr4_address_slice_1_rw_mask[43];
|
||||
extern u32 g_lpddr4_address_slice_2_rw_mask[43];
|
||||
extern u32 g_lpddr4_phy_core_rw_mask[126];
|
||||
|
||||
#endif /* LPDDR4_RW_MASKS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -8,6 +8,10 @@ obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
|
|||
obj-$(CONFIG_K3_DDRSS) += lpddr4.o
|
||||
ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
|
||||
|
||||
obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
|
||||
obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
|
||||
ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
|
||||
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
|
||||
obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
|
||||
ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@
|
|||
#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
|
||||
#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
|
||||
|
||||
#define DDRSS_V2A_R1_MAT_REG 0x0020
|
||||
#define DDRSS_ECC_CTRL_REG 0x0120
|
||||
|
||||
struct k3_ddrss_desc {
|
||||
struct udevice *dev;
|
||||
void __iomem *ddrss_ss_cfg;
|
||||
|
|
@ -416,6 +419,12 @@ static int k3_ddrss_probe(struct udevice *dev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
#ifdef CONFIG_K3_AM64_DDRSS
|
||||
|
||||
writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
|
||||
writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
|
||||
#endif
|
||||
|
||||
driverdt = lpddr4_getinstance();
|
||||
k3_lpddr4_probe();
|
||||
k3_lpddr4_init();
|
||||
|
|
@ -440,6 +449,7 @@ static struct ram_ops k3_ddrss_ops = {
|
|||
};
|
||||
|
||||
static const struct udevice_id k3_ddrss_ids[] = {
|
||||
{.compatible = "ti,am64-ddrss"},
|
||||
{.compatible = "ti,j721e-ddrss"},
|
||||
{}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,396 @@
|
|||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
#include "cps_drv_lpddr4.h"
|
||||
#include "lpddr4_ctl_regs.h"
|
||||
#include "lpddr4_if.h"
|
||||
#include "lpddr4.h"
|
||||
#include "lpddr4_structs_if.h"
|
||||
|
||||
static u32 ctlintmap[51][3] = {
|
||||
{ 0, 0, 7 },
|
||||
{ 1, 0, 8 },
|
||||
{ 2, 0, 9 },
|
||||
{ 3, 0, 14 },
|
||||
{ 4, 0, 15 },
|
||||
{ 5, 0, 16 },
|
||||
{ 6, 0, 17 },
|
||||
{ 7, 0, 19 },
|
||||
{ 8, 1, 0 },
|
||||
{ 9, 2, 0 },
|
||||
{ 10, 2, 3 },
|
||||
{ 11, 3, 0 },
|
||||
{ 12, 4, 0 },
|
||||
{ 13, 5, 11 },
|
||||
{ 14, 5, 12 },
|
||||
{ 15, 5, 13 },
|
||||
{ 16, 5, 14 },
|
||||
{ 17, 5, 15 },
|
||||
{ 18, 6, 0 },
|
||||
{ 19, 6, 1 },
|
||||
{ 20, 6, 2 },
|
||||
{ 21, 6, 6 },
|
||||
{ 22, 6, 7 },
|
||||
{ 23, 7, 3 },
|
||||
{ 24, 7, 4 },
|
||||
{ 25, 7, 5 },
|
||||
{ 26, 7, 6 },
|
||||
{ 27, 7, 7 },
|
||||
{ 28, 8, 0 },
|
||||
{ 29, 9, 0 },
|
||||
{ 30, 10, 0 },
|
||||
{ 31, 10, 1 },
|
||||
{ 32, 10, 2 },
|
||||
{ 33, 10, 3 },
|
||||
{ 34, 10, 4 },
|
||||
{ 35, 10, 5 },
|
||||
{ 36, 11, 0 },
|
||||
{ 37, 12, 0 },
|
||||
{ 38, 12, 1 },
|
||||
{ 39, 12, 2 },
|
||||
{ 40, 12, 3 },
|
||||
{ 41, 12, 4 },
|
||||
{ 42, 12, 5 },
|
||||
{ 43, 13, 0 },
|
||||
{ 44, 13, 1 },
|
||||
{ 45, 13, 3 },
|
||||
{ 46, 14, 0 },
|
||||
{ 47, 14, 2 },
|
||||
{ 48, 14, 3 },
|
||||
{ 49, 15, 2 },
|
||||
{ 50, 16, 0 },
|
||||
};
|
||||
|
||||
static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
|
||||
static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
|
||||
static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
|
||||
static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
|
||||
static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
|
||||
static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
|
||||
|
||||
u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
|
||||
{
|
||||
u32 result = 0U;
|
||||
u32 regval = 0U;
|
||||
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
|
||||
regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
|
||||
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
|
||||
regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
|
||||
CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
|
||||
{
|
||||
u32 result = 0U;
|
||||
|
||||
result = lpddr4_getctlinterruptmasksf(pd, mask);
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
|
||||
{
|
||||
u32 result;
|
||||
u32 regval = 0;
|
||||
const u64 ui64one = 1ULL;
|
||||
const u32 ui32irqcount = (u32)32U;
|
||||
|
||||
result = lpddr4_setctlinterruptmasksf(pd, mask);
|
||||
if ((result == (u32)0) && (ui32irqcount < 64U)) {
|
||||
if (*mask >= (ui64one << ui32irqcount))
|
||||
result = (u32)EINVAL;
|
||||
}
|
||||
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
|
||||
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
|
||||
{
|
||||
if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
|
||||
else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
|
||||
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
|
||||
else if (intr == LPDDR4_INTR_BIST_DONE)
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
|
||||
else if (intr == LPDDR4_INTR_PARITY_ERROR)
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
|
||||
else
|
||||
*ctlmasterintflag = (u32)1U;
|
||||
}
|
||||
|
||||
static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
|
||||
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
|
||||
{
|
||||
if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
|
||||
else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
|
||||
else
|
||||
lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
|
||||
}
|
||||
|
||||
static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
|
||||
u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
|
||||
{
|
||||
if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
|
||||
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
|
||||
else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
|
||||
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
|
||||
else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
|
||||
*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
|
||||
else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
|
||||
else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
|
||||
*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
|
||||
else
|
||||
lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
|
||||
}
|
||||
|
||||
u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
|
||||
{
|
||||
u32 result;
|
||||
u32 ctlmasterirqstatus = 0U;
|
||||
u32 ctlgrpirqstatus = 0U;
|
||||
u32 ctlmasterintflag = 0U;
|
||||
|
||||
result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
|
||||
|
||||
lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
|
||||
|
||||
if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
|
||||
if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
|
||||
(((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
|
||||
(ctlmasterintflag == (u32)0))
|
||||
*irqstatus = true;
|
||||
else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
|
||||
(ctlmasterintflag == (u32)1U))
|
||||
*irqstatus = true;
|
||||
else
|
||||
*irqstatus = false;
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
|
||||
{
|
||||
u32 regval = 0;
|
||||
|
||||
if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
|
||||
} else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
|
||||
(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
|
||||
} else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
|
||||
(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
|
||||
{
|
||||
u32 regval = 0;
|
||||
|
||||
if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
|
||||
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
|
||||
} else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
|
||||
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
|
||||
} else {
|
||||
lpddr4_ackctlinterrupt_4(ctlregbase, intr);
|
||||
}
|
||||
}
|
||||
|
||||
static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
|
||||
{
|
||||
u32 regval = 0;
|
||||
|
||||
if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
} else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
|
||||
(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
|
||||
} else {
|
||||
lpddr4_ackctlinterrupt_3(ctlregbase, intr);
|
||||
}
|
||||
}
|
||||
|
||||
u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
|
||||
{
|
||||
u32 result;
|
||||
|
||||
result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
|
||||
if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
|
||||
else
|
||||
lpddr4_ackctlinterrupt_2(ctlregbase, intr);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
|
||||
{
|
||||
u32 regval;
|
||||
u32 errbitmask = 0U;
|
||||
u32 snum;
|
||||
volatile u32 *regaddress;
|
||||
|
||||
regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
|
||||
errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
|
||||
for (snum = 0U; snum < DSLICE_NUM; snum++) {
|
||||
regval = CPS_REG_READ(regaddress);
|
||||
if ((regval & errbitmask) != 0U) {
|
||||
debuginfo->wrlvlerror = CDN_TRUE;
|
||||
*errfoundptr = true;
|
||||
}
|
||||
regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
|
||||
}
|
||||
}
|
||||
|
||||
u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
|
||||
{
|
||||
u32 result = 0U;
|
||||
bool errorfound = false;
|
||||
|
||||
result = lpddr4_getdebuginitinfosf(pd, debuginfo);
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
|
||||
lpddr4_setsettings(ctlregbase, errorfound);
|
||||
errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
|
||||
}
|
||||
|
||||
if (errorfound == (bool)true)
|
||||
result = (u32)EPROTO;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
|
||||
{
|
||||
u32 result = 0U;
|
||||
|
||||
result = lpddr4_getreducmodesf(pd, mode);
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
|
||||
*mode = LPDDR4_REDUC_ON;
|
||||
else
|
||||
*mode = LPDDR4_REDUC_OFF;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
|
||||
{
|
||||
u32 result = 0U;
|
||||
u32 regval = 0U;
|
||||
|
||||
result = lpddr4_setreducmodesf(pd, mode);
|
||||
if (result == (u32)0) {
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
|
||||
CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
|
||||
{
|
||||
u32 lowerdata;
|
||||
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
||||
u32 result = (u32)0;
|
||||
|
||||
if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
|
||||
*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
|
||||
*mmrvalue = (u64)0;
|
||||
result = (u32)EIO;
|
||||
} else {
|
||||
*mrrstatus = (u8)0;
|
||||
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
|
||||
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
|
||||
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#ifdef REG_WRITE_VERIF
|
||||
|
||||
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
||||
{
|
||||
u32 rwmask = 0U;
|
||||
|
||||
switch (dslicenum) {
|
||||
case 0:
|
||||
if (arrayoffset < DSLICE0_REG_COUNT)
|
||||
rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
|
||||
break;
|
||||
default:
|
||||
if (arrayoffset < DSLICE1_REG_COUNT)
|
||||
rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
|
||||
break;
|
||||
}
|
||||
return rwmask;
|
||||
}
|
||||
#endif
|
||||
|
||||
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
|
||||
{
|
||||
u32 result = 0U;
|
||||
|
||||
result = lpddr4_geteccenablesf(pd, eccparam);
|
||||
if (result == (u32)0) {
|
||||
*eccparam = LPDDR4_ECC_DISABLED;
|
||||
result = (u32)EOPNOTSUPP;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
|
||||
{
|
||||
u32 result = 0U;
|
||||
|
||||
result = lpddr4_seteccenablesf(pd, eccparam);
|
||||
if (result == (u32)0)
|
||||
result = (u32)EOPNOTSUPP;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_16BIT_H
|
||||
#define LPDDR4_16BIT_H
|
||||
|
||||
#define DSLICE_NUM (2U)
|
||||
#define ASLICE_NUM (3U)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DSLICE0_REG_COUNT (126U)
|
||||
#define DSLICE1_REG_COUNT (126U)
|
||||
#define ASLICE0_REG_COUNT (42U)
|
||||
#define ASLICE1_REG_COUNT (42U)
|
||||
#define ASLICE2_REG_COUNT (42U)
|
||||
#define PHY_CORE_REG_COUNT (126U)
|
||||
|
||||
#define GRP_SHIFT 1
|
||||
#define INT_SHIFT 2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_16BIT_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,257 @@
|
|||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*
|
||||
* Cadence DDR Driver
|
||||
*
|
||||
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
||||
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef LPDDR4_16BIT_SANITY_H
|
||||
#define LPDDR4_16BIT_SANITY_H
|
||||
|
||||
#include <errno.h>
|
||||
#include <linux/types.h>
|
||||
#include <lpddr4_if.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
|
||||
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
|
||||
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
|
||||
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
|
||||
|
||||
#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
|
||||
#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
|
||||
#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
|
||||
#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
if (pd == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (irqstatus == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
|
||||
(intr != LPDDR4_INTR_ECC_ERROR) &&
|
||||
(intr != LPDDR4_INTR_LP_DONE) &&
|
||||
(intr != LPDDR4_INTR_LP_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
|
||||
(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
|
||||
(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
|
||||
(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
|
||||
(intr != LPDDR4_INTR_USERIF_WRAP) &&
|
||||
(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
|
||||
(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
|
||||
(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
|
||||
(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
|
||||
(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
|
||||
(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
|
||||
(intr != LPDDR4_INTR_BIST_DONE) &&
|
||||
(intr != LPDDR4_INTR_CRC) &&
|
||||
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
|
||||
(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
|
||||
(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_DIMM) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
|
||||
(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
|
||||
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
|
||||
(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
|
||||
(intr != LPDDR4_INTR_MRR_ERROR) &&
|
||||
(intr != LPDDR4_INTR_MR_READ_DONE) &&
|
||||
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
|
||||
(intr != LPDDR4_INTR_PARITY_ERROR) &&
|
||||
(intr != LPDDR4_INTR_LOR_BITS)
|
||||
) {
|
||||
ret = EINVAL;
|
||||
} else {
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
if (pd == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
|
||||
(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
|
||||
(intr != LPDDR4_INTR_ECC_ERROR) &&
|
||||
(intr != LPDDR4_INTR_LP_DONE) &&
|
||||
(intr != LPDDR4_INTR_LP_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
|
||||
(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
|
||||
(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
|
||||
(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
|
||||
(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
|
||||
(intr != LPDDR4_INTR_USERIF_WRAP) &&
|
||||
(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
|
||||
(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
|
||||
(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
|
||||
(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
|
||||
(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
|
||||
(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
|
||||
(intr != LPDDR4_INTR_BIST_DONE) &&
|
||||
(intr != LPDDR4_INTR_CRC) &&
|
||||
(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
|
||||
(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
|
||||
(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
|
||||
(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
|
||||
(intr != LPDDR4_INTR_DIMM) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
|
||||
(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
|
||||
(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
|
||||
(intr != LPDDR4_INTR_MC_INIT_DONE) &&
|
||||
(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
|
||||
(intr != LPDDR4_INTR_MRR_ERROR) &&
|
||||
(intr != LPDDR4_INTR_MR_READ_DONE) &&
|
||||
(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
|
||||
(intr != LPDDR4_INTR_PARITY_ERROR) &&
|
||||
(intr != LPDDR4_INTR_LOR_BITS)
|
||||
) {
|
||||
ret = EINVAL;
|
||||
} else {
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
if (pd == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (irqstatus == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
|
||||
) {
|
||||
ret = EINVAL;
|
||||
} else {
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
if (pd == NULL) {
|
||||
ret = EINVAL;
|
||||
} else if (
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
|
||||
(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
|
||||
) {
|
||||
ret = EINVAL;
|
||||
} else {
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LPDDR4_16BIT_SANITY_H */
|
||||
Loading…
Reference in New Issue