mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
9f9b5c1c16
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
34 lines
649 B
C
34 lines
649 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
|
|
/*
|
|
* Cadence DDR Driver
|
|
*
|
|
* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
|
|
* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#ifndef LPDDR4_16BIT_H
|
|
#define LPDDR4_16BIT_H
|
|
|
|
#define DSLICE_NUM (2U)
|
|
#define ASLICE_NUM (3U)
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define DSLICE0_REG_COUNT (126U)
|
|
#define DSLICE1_REG_COUNT (126U)
|
|
#define ASLICE0_REG_COUNT (42U)
|
|
#define ASLICE1_REG_COUNT (42U)
|
|
#define ASLICE2_REG_COUNT (42U)
|
|
#define PHY_CORE_REG_COUNT (126U)
|
|
|
|
#define GRP_SHIFT 1
|
|
#define INT_SHIFT 2
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* LPDDR4_16BIT_H */
|