mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
9f9b5c1c16
Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
397 lines
15 KiB
C
397 lines
15 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <errno.h>
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#include "cps_drv_lpddr4.h"
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#include "lpddr4_ctl_regs.h"
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#include "lpddr4_if.h"
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#include "lpddr4.h"
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#include "lpddr4_structs_if.h"
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static u32 ctlintmap[51][3] = {
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{ 0, 0, 7 },
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{ 1, 0, 8 },
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{ 2, 0, 9 },
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{ 3, 0, 14 },
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{ 4, 0, 15 },
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{ 5, 0, 16 },
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{ 6, 0, 17 },
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{ 7, 0, 19 },
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{ 8, 1, 0 },
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{ 9, 2, 0 },
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{ 10, 2, 3 },
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{ 11, 3, 0 },
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{ 12, 4, 0 },
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{ 13, 5, 11 },
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{ 14, 5, 12 },
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{ 15, 5, 13 },
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{ 16, 5, 14 },
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{ 17, 5, 15 },
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{ 18, 6, 0 },
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{ 19, 6, 1 },
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{ 20, 6, 2 },
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{ 21, 6, 6 },
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{ 22, 6, 7 },
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{ 23, 7, 3 },
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{ 24, 7, 4 },
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{ 25, 7, 5 },
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{ 26, 7, 6 },
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{ 27, 7, 7 },
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{ 28, 8, 0 },
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{ 29, 9, 0 },
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{ 30, 10, 0 },
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{ 31, 10, 1 },
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{ 32, 10, 2 },
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{ 33, 10, 3 },
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{ 34, 10, 4 },
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{ 35, 10, 5 },
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{ 36, 11, 0 },
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{ 37, 12, 0 },
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{ 38, 12, 1 },
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{ 39, 12, 2 },
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{ 40, 12, 3 },
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{ 41, 12, 4 },
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{ 42, 12, 5 },
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{ 43, 13, 0 },
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{ 44, 13, 1 },
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{ 45, 13, 3 },
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{ 46, 14, 0 },
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{ 47, 14, 2 },
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{ 48, 14, 3 },
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{ 49, 15, 2 },
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{ 50, 16, 0 },
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};
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static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
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static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
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static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
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static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
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static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
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static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
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u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
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{
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u32 result = 0U;
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u32 regval = 0U;
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
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CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
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regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
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CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
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return result;
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}
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u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
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{
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u32 result = 0U;
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result = lpddr4_getctlinterruptmasksf(pd, mask);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
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}
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return result;
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}
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u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
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{
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u32 result;
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u32 regval = 0;
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const u64 ui64one = 1ULL;
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const u32 ui32irqcount = (u32)32U;
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result = lpddr4_setctlinterruptmasksf(pd, mask);
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if ((result == (u32)0) && (ui32irqcount < 64U)) {
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if (*mask >= (ui64one << ui32irqcount))
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result = (u32)EINVAL;
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}
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
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}
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return result;
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}
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static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
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u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
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{
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if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
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else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
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*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
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else if (intr == LPDDR4_INTR_BIST_DONE)
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
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else if (intr == LPDDR4_INTR_PARITY_ERROR)
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
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else
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*ctlmasterintflag = (u32)1U;
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}
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static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
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u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
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{
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if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
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else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
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else
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lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
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}
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static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
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u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
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{
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if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
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*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
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else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
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*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
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else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
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*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
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else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
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else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
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*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
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else
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lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
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}
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u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
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{
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u32 result;
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u32 ctlmasterirqstatus = 0U;
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u32 ctlgrpirqstatus = 0U;
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u32 ctlmasterintflag = 0U;
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result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
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lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
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if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
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if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
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(((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
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(ctlmasterintflag == (u32)0))
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*irqstatus = true;
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else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
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(ctlmasterintflag == (u32)1U))
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*irqstatus = true;
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else
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*irqstatus = false;
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}
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}
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return result;
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}
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static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
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{
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u32 regval = 0;
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if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
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} else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
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(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
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} else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
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(u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
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} else {
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}
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}
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static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
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{
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u32 regval = 0;
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if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
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(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
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} else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
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(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
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} else {
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lpddr4_ackctlinterrupt_4(ctlregbase, intr);
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}
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}
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static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
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{
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u32 regval = 0;
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if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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} else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
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(u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
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} else {
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lpddr4_ackctlinterrupt_3(ctlregbase, intr);
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}
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}
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u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
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{
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u32 result;
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result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
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if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
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CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
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else
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lpddr4_ackctlinterrupt_2(ctlregbase, intr);
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}
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return result;
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}
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void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
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{
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u32 regval;
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u32 errbitmask = 0U;
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u32 snum;
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volatile u32 *regaddress;
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regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
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errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
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for (snum = 0U; snum < DSLICE_NUM; snum++) {
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regval = CPS_REG_READ(regaddress);
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if ((regval & errbitmask) != 0U) {
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debuginfo->wrlvlerror = CDN_TRUE;
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*errfoundptr = true;
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}
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regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
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}
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}
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u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
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{
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u32 result = 0U;
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bool errorfound = false;
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result = lpddr4_getdebuginitinfosf(pd, debuginfo);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
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lpddr4_setsettings(ctlregbase, errorfound);
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errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
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}
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if (errorfound == (bool)true)
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result = (u32)EPROTO;
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return result;
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}
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u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
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{
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u32 result = 0U;
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result = lpddr4_getreducmodesf(pd, mode);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
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*mode = LPDDR4_REDUC_ON;
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else
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*mode = LPDDR4_REDUC_OFF;
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}
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return result;
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}
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u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
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{
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u32 result = 0U;
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u32 regval = 0U;
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result = lpddr4_setreducmodesf(pd, mode);
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if (result == (u32)0) {
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lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
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regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
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|
CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
|
|
{
|
|
u32 lowerdata;
|
|
lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
|
|
u32 result = (u32)0;
|
|
|
|
if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
|
|
*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
|
|
*mmrvalue = (u64)0;
|
|
result = (u32)EIO;
|
|
} else {
|
|
*mrrstatus = (u8)0;
|
|
lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
|
|
*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
|
|
result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
|
|
}
|
|
return result;
|
|
}
|
|
|
|
#ifdef REG_WRITE_VERIF
|
|
|
|
u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
|
|
{
|
|
u32 rwmask = 0U;
|
|
|
|
switch (dslicenum) {
|
|
case 0:
|
|
if (arrayoffset < DSLICE0_REG_COUNT)
|
|
rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
|
|
break;
|
|
default:
|
|
if (arrayoffset < DSLICE1_REG_COUNT)
|
|
rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
|
|
break;
|
|
}
|
|
return rwmask;
|
|
}
|
|
#endif
|
|
|
|
u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
|
|
{
|
|
u32 result = 0U;
|
|
|
|
result = lpddr4_geteccenablesf(pd, eccparam);
|
|
if (result == (u32)0) {
|
|
*eccparam = LPDDR4_ECC_DISABLED;
|
|
result = (u32)EOPNOTSUPP;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
|
|
{
|
|
u32 result = 0U;
|
|
|
|
result = lpddr4_seteccenablesf(pd, eccparam);
|
|
if (result == (u32)0)
|
|
result = (u32)EOPNOTSUPP;
|
|
|
|
return result;
|
|
}
|