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https://github.com/brain-hackers/u-boot-brain
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a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
31 lines
611 B
C
31 lines
611 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_32BIT_H
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#define LPDDR4_32BIT_H
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#define DSLICE_NUM (4U)
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#define ASLICE_NUM (1U)
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DSLICE0_REG_COUNT (140U)
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#define DSLICE1_REG_COUNT (140U)
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#define DSLICE2_REG_COUNT (140U)
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#define DSLICE3_REG_COUNT (140U)
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#define ASLICE0_REG_COUNT (52U)
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#define PHY_CORE_REG_COUNT (140U)
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPDDR4_32BIT_H */
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