mirror of
https://github.com/brain-hackers/u-boot-brain
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a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_32BIT_IF_H
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#define LPDDR4_32BIT_IF_H
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#include <linux/types.h>
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#define LPDDR4_INTR_MAX_CS (2U)
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#define LPDDR4_INTR_CTL_REG_COUNT (459U)
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#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U)
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#define LPDDR4_INTR_PHY_REG_COUNT (1423U)
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typedef enum {
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LPDDR4_INTR_RESET_DONE = 0U,
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LPDDR4_INTR_BUS_ACCESS_ERROR = 1U,
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LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U,
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LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U,
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LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U,
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LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U,
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LPDDR4_INTR_ECC_SCRUB_DONE = 6U,
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LPDDR4_INTR_ECC_SCRUB_ERROR = 7U,
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LPDDR4_INTR_PORT_COMMAND_ERROR = 8U,
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LPDDR4_INTR_MC_INIT_DONE = 9U,
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LPDDR4_INTR_LP_DONE = 10U,
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LPDDR4_INTR_BIST_DONE = 11U,
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LPDDR4_INTR_WRAP_ERROR = 12U,
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LPDDR4_INTR_INVALID_BURST_ERROR = 13U,
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LPDDR4_INTR_RDLVL_ERROR = 14U,
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LPDDR4_INTR_RDLVL_GATE_ERROR = 15U,
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LPDDR4_INTR_WRLVL_ERROR = 16U,
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LPDDR4_INTR_CA_TRAINING_ERROR = 17U,
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LPDDR4_INTR_DFI_UPDATE_ERROR = 18U,
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LPDDR4_INTR_MRR_ERROR = 19U,
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LPDDR4_INTR_PHY_MASTER_ERROR = 20U,
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LPDDR4_INTR_WRLVL_REQ = 21U,
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LPDDR4_INTR_RDLVL_REQ = 22U,
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LPDDR4_INTR_RDLVL_GATE_REQ = 23U,
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LPDDR4_INTR_CA_TRAINING_REQ = 24U,
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LPDDR4_INTR_LEVELING_DONE = 25U,
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LPDDR4_INTR_PHY_ERROR = 26U,
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LPDDR4_INTR_MR_READ_DONE = 27U,
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LPDDR4_INTR_TEMP_CHANGE = 28U,
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LPDDR4_INTR_TEMP_ALERT = 29U,
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LPDDR4_INTR_SW_DQS_COMPLETE = 30U,
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LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U,
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LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U,
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LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U,
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LPDDR4_INTR_MR_WRITE_DONE = 34U,
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LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U,
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LPDDR4_INTR_DFI_INIT_STATE = 36U,
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LPDDR4_INTR_DLL_RESYNC_DONE = 37U,
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LPDDR4_INTR_TDFI_TO = 38U,
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LPDDR4_INTR_DFS_DONE = 39U,
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LPDDR4_INTR_DFS_STATUS = 40U,
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LPDDR4_INTR_REFRESH_STATUS = 41U,
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LPDDR4_INTR_ZQ_STATUS = 42U,
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LPDDR4_INTR_SW_REQ_MODE = 43U,
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LPDDR4_INTR_LOR_BITS = 44U
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} lpddr4_intr_ctlinterrupt;
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typedef enum {
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LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
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LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
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LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U,
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LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
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LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U,
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LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
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LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U,
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LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
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LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U,
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LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U,
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LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
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LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U,
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LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U,
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LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
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LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
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} lpddr4_intr_phyindepinterrupt;
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#endif /* LPDDR4_32BIT_IF_H */
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