mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef CPS_DRV_H_
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#define CPS_DRV_H_
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#ifdef DEMO_TB
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#include <cdn_demo.h>
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#else
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#include <asm/io.h>
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#endif
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#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
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#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
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#define CPS_FLD_MASK(fld) (fld ## _MASK)
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#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
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#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
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#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
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#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
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#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_SHIFT(fld)), \
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(u32)(reg_value)))
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#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_SHIFT(fld)), \
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(u32)(reg_value), (u32)(value)))
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#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
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(u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_WOCLR(fld)), \
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(u32)(reg_value)))
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#ifdef CLR_USED
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#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
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(u32)(CPS_FLD_MASK(fld)), \
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(u32)(CPS_FLD_WOSET(fld)), \
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(u32)(CPS_FLD_WOCLR(fld)), \
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(u32)(reg_value)))
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#endif
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static inline u32 cps_regread(volatile u32 *reg);
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static inline u32 cps_regread(volatile u32 *reg)
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{
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return readl(reg);
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}
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static inline void cps_regwrite(volatile u32 *reg, u32 value);
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static inline void cps_regwrite(volatile u32 *reg, u32 value)
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{
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writel(value, reg);
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}
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static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
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static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
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{
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u32 result = (reg_value & mask) >> shift;
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return result;
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}
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static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
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static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
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{
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u32 new_value = (value << shift) & mask;
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new_value = (reg_value & ~mask) | new_value;
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return new_value;
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}
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static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
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static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
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{
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u32 new_value = reg_value;
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if ((width == 1U) && (is_woclr == 0U))
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new_value |= mask;
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return new_value;
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}
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#ifdef CLR_USED
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static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
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static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
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{
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u32 new_value = reg_value;
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if ((width == 1U) && (is_woset == 0U))
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new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
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return new_value;
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}
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#endif /* CLR_USED */
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#endif /* CPS_DRV_H_ */
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