i.MX8/8X SECO MU is dedicated for communication between kernel
and SECO. To use SECO MU more effectivly, add "fsl,imx8-seco-mu"
compatible to support fast IPC.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
(cherry picked from commit 7dd4eb4742)
Add driver support for i.MX8DXL DB Perf, which supports AXI ID PORT
CHANNEL filter.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Add driver support for i.MX8DXL DDR Perf, which supports AXI ID PORT
CHANNEL filter.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Add documentation for a new clock 'phy_parent'. This clock is optional
and is used to re-parent the PHY related clocks (phy_ref, tx_esc and
rx_esc) to a valid parent. This clock is needed, in order to make the
re-parenting in driver, since the default re-parenting in dts node
(using assigned-clock-parents) may break the LVDS block, which has it's
PHY shared with MIPI-DSI.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
(cherry picked from commit 7ed3b8738e)
Some MAC PCS blocks are unable to provide interrupts when their status
changes. As we already have support in phylink for polling status, use
this to provide a hook for MACs to enable polling mode.
The patch idea was picked up from Russell King's suggestion on the macb
phylink patch thread here [0] but the implementation was changed.
Instead of introducing a new phylink_start_poll() function, which would
make the implementation cumbersome for common PHYLINK implementations
for multiple types of devices, like DSA, just add a boolean property to
the phylink_config structure, which is just as backwards-compatible.
https://lkml.org/lkml/2019/12/16/603
Suggested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Conflicts:
drivers/net/phy/phylink.c
with upstream commit 24cf0e693bb5 ("net: phylink: split link_an_mode
configured and current settings") submitted for net-next and merged
during v5.5-rc1.
(cherry picked from commit ac7420c5ed)
QORIQ LS1028A soc used fsl,vf610-edma, but it has a little bit different
from others, so add new compatible to distinguish them.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Link: https://lore.kernel.org/r/20191212033714.4090-3-peng.ma@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit f8dd1f395d)
Add "mem" clock that is required for imx8dxl platform.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add information for i.MX8MP DDRC which reports the single bit errors
that are corrected and the double bit errors that are detected.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Add two parameters which are used to tune USB signal for imx picophy,
picophy is used at imx7d and imx8mm.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Add devicetree bindings for i.MX8mp LDB controller.
The controller supports two four data lane LVDS channels and supports
single/dual channel mode. The controller connects with LCDIFv3 on
i.MX8mp SoC.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add devicetree bindings for Freescale i.MX8mp LVDS PHY.
The IP block contains two PHYs, each of which supports
a four data lane LVDS channel.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add one hsio phandle and compatible ID required by iMX8MP PCIe.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <Fugang.duan@nxp.com>
Add "clock" property (and corresponding "clock-names")
for the CAAM SNVS node.
This property is optional: there are cases when SNVS clock is kept
always on (chips such as i.MX6 SX, UL).
A good guide line is to check whether i.MX clk driver defines the clock.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Adds compatible string for "nxp,cbtl04gp", which is also super speed
mux switch for type-c orientation, controlled by one GPIO.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
imx8mp SoC has the similar USB3 PHY with different version than
imx8mq, add compatible string "fsl,imx8mp-usb-phy", which has
the same properties.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
iMX8MP USB3 integrate Synopsys DesignWare Cores SuperSpeed
USB 3.0 Controller 3.30b IP, the glue layer is added to support
wakeup from low power mode.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Some registers on pfuze3000 will lost after exit from LPSR, need restore them,
otherwise system may reboot with below command after system enter LPSR one time:
root@imx7d_all:~# echo enabled > /sys/class/tty/ttymxc0/power/wakeup
root@imx7d_all:~# echo mem > /sys/power/state
because LDOGCTL not recover as 1. Add 'fsl,lpsr-mode' property to this case,
please add this property if your board support LPSR mode as imx7d-12x12-lpddr3-arm2
board.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 4aa2a2a928)
Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.
Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
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Merge linux-5.4.y tag 'v5.4.3' into lf-5.4.y
This is the 5.4.3 stable release
Conflicts:
drivers/cpufreq/imx-cpufreq-dt.c
drivers/spi/spi-fsl-qspi.c
The conflict is very minor, fixed it when do the merge. The imx-cpufreq-dt.c
is just one line code-style change, using upstream one, no any function change.
The spi-fsl-qspi.c has minor conflicts when merge upstream fixes: c69b17da53
spi: spi-fsl-qspi: Clear TDH bits in FLSHCR register
After merge, basic boot sanity test and basic qspi test been done on i.mx
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646
on LS1021A
Reviewed-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
* wifi/next: (51 commits)
MLK-22949 brcmfmac: add chip id check for clm_blob firmware load
MLK-22948 brcmfmac: avoid to send mailbox interrupt twice for core version 0xb
MLK-22946 brcmfmac: freeing wiphy after brcmf attach failed
dt-bindings: add new property to enable board_type
brcmfmac: let board_type is optional
...
* thermal/next: (12 commits)
MLK-23010 thermal: imx_sc_thermal: Correct message format to avoid stack corruption
thermal: imx_sc_thermal: Add system-wide device cooling to all thermal zones
thermal: qoriq: add thermal monitor unit version 2 support
thermal: imx: Add device cooling support
thermal: imx8mm: Add device cooling support
...
* rpmsg/next: (8 commits)
LF-44 rpmsg: imx: add the rpmsg tty demo
rpmsg: imx: enable the tx_block mechanism in the flow
rpmsg: imx_rpmsg: add partition reset notify
rpmsg: imx: bug fix and clean up the codes
rpmsg: imx: extend the rpmsg support for imx8qm and so on
...
* reset/next: (12 commits)
reset: Kconfig: use 'ARCH_MXC' for reset dispmix
reset: imx8m: Correct clock name for dispmix driver
reset: gpio-reset: add pinctrl comsuer header file
reset: imx7: add the clkreq reset for imx8m
dt-bindings: reset: imx7: add clkreq reset used by the l1ss on imx8m
...
* pcie/next: (40 commits)
LF-128 PCI: imx: turn off the clocks and regulators when link is down
PCI: imx: add the imx pcie ep verification solution
misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support
PCI: mobiveil: Add workaround for unsupported request error
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
...
Use commonly used phy-handle property and mdio subnode to handle
phy properties.
Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Currently, of_get_mac_address supports NVMEM, some platforms
MAC address that read from NVMEM efuse requires to swap bytes
order, so add new property "nvmem_macaddr_swap" to specify the
behavior. If the MAC address is valid from NVMEM, add new property
"nvmem-mac-address" in ethernet node.
Update these two properties in the binding documentation.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
[ Aisheng: update to yaml format ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Introduce the rescan attribute as a bus attribute to
synchronize the fsl-mc bus objects and the MC firmware.
To rescan the fsl-mc bus, e.g.,
echo 1 > /sys/bus/fsl-mc/rescan
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Franck LENORMAND