usb: dwc3: Add chip-specific compatible string

Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.

Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>

Documentation/devicetree/bindings/usb/dwc3.txt

@@ -4,7 +4,15 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
       as described in 'usb/generic.txt'
 
 Required properties:
- - compatible: must be "snps,dwc3"
+ - compatible: must be "snps,dwc3" and (if applicable) may contain a
+	chip-specific compatible string in front of it to allow dwc3 driver be
+	able to update cache type configuration accordingly, otherwise
+	Layerscape SoC will encounter USB init failure when adding property
+	dma-coherent on device tree.
+	Example:
+	* "fsl,layerscape-dwc3", "snps,dwc3"
+	* "snps,dwc3"
+
  - reg : Address and length of the register set for the device
  - interrupts: Interrupts used by the dwc3 controller.
  - clock-names: should contain "ref", "bus_early", "suspend"