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Merge branch 'phy/next' into next 

* phy/next: (6 commits)
  phy: mixel-lvds-combo: Configure CO divider to meet fvco range requirement
  phy: Add Mixel LVDS combo PHY support
  dt-bindings: phy: Add DT binding for Mixel LVDS PHY(LVDS/MIPI DSI combo)
  phy: Add Mixel LVDS PHY support
  dt-bindings: phy: Add DT binding for Mixel LVDS PHY
  ...
This commit is contained in:
Dong Aisheng 2019-12-02 18:05:18 +08:00
parent b5f8879f2e 9ff00c698a
commit 4402983b63
9 changed files with 770 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt Normal file
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@ -0,0 +1,19 @@
Mixel LVDS combo PHY
Required properties:
- compatible: must be "mixel,lvds-combo-phy".
- reg: offset and length of the register block.
- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
- clocks: clock phandle and specifier pair.
- clock-names: string, clock input name, must be "phy".
- power-domains: phandle pointing to power domain.
Example:
ldb_phy@56221000 {
compatible = "mixel,lvds-combo-phy";
reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>;
#phy-cells = <0>;
clocks = <&clk IMX_LVDS0_PHY_CLK>;
clock-names = "phy";
power-domains = <&pd IMX_SC_R_LVDS_0>;
};

39
Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt Normal file
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@ -0,0 +1,39 @@
Mixel LVDS PHY
This LVDS PHY supports two LVDS channels.
Required properties:
- compatible: must be "mixel,lvds-phy".
- reg: offset and length of the register block.
- #address-cells: number of address cells for the LVDS channel subnodes, must
be <1>.
- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>.
- clocks: clock phandle and specifier pair.
- clock-names: string, clock input name, must be "phy".
- power-domains: phandle pointing to power domain.
The LVDS PHY device tree node should have the subnodes corresponding to the two
LVDS channels. These subnodes must contain the following properties:
- reg: the PHY ID.
- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
Example:
ldb_phy@56241000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mixel,lvds-phy";
reg = <0x0 0x56241000 0x0 0x100>;
clocks = <&clk IMX_LVDS0_PHY_CLK>;
clock-names = "phy";
power-domains = <&pd IMX_SC_R_LVDS_0>;
ldb1_phy1: port@0 {
reg = <0>;
#phy-cells = <0>;
};
ldb1_phy2: port@1 {
reg = <1>;
#phy-cells = <0>;
};
};

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
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@ -605,6 +605,8 @@ patternProperties:
description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*":
description: Mitsubishi Electric Corporation
"^mixel,.*":
description: Mixel, Inc
"^mosaixtech,.*":
description: Mosaix Technologies, Inc.
"^motorola,.*":

10
drivers/phy/Kconfig
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@ -49,6 +49,16 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
config PHY_MIXEL_LVDS
tristate "MIXEL LVDS PHY support"
depends on OF
select GENERIC_PHY
config PHY_MIXEL_LVDS_COMBO
tristate "MIXEL LVDS PHY(LVDS+MIPI DSI combo PHY) support"
depends on OF
select GENERIC_PHY
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"

2
drivers/phy/Makefile
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@ -8,6 +8,8 @@ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_MIXEL_LVDS) += phy-mixel-lvds.o
obj-$(CONFIG_PHY_MIXEL_LVDS_COMBO) += phy-mixel-lvds-combo.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/

317
drivers/phy/phy-mixel-lvds-combo.c Normal file
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@ -0,0 +1,317 @@
/*
* Copyright 2017-2019 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/phy/phy-mixel-lvds-combo.h>
#include <linux/platform_device.h>
/* Control and Status Registers(CSR) */
#define PHY_CTRL 0x00
#define CCM(n) (((n) & 0x7) << 5)
#define CCM_MASK 0xe0
#define CA(n) (((n) & 0x7) << 2)
#define CA_MASK 0x1c
#define RFB BIT(1)
#define LVDS_EN BIT(0)
#define SS 0x20
#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
#define ULPS 0x30
#define ULPS_MASK 0x1f
#define LANE(n) BIT(n)
#define DPI 0x40
#define COLOR_CODE_MASK 0x7
#define BIT16_CFG1 0x0
#define BIT16_CFG2 0x1
#define BIT16_CFG3 0x2
#define BIT18_CFG1 0x3
#define BIT18_CFG2 0x4
#define BIT24 0x5
/* controller registers */
#define PD_TX 0x300
#define PD_PLL 0x31c
#define CO 0x32c
#define CO_DIV(n) (ffs(n) - 1)
#define MIN_PLL_VCO_FREQ 640000000
#define MAX_PLL_VCO_FREQ 1500000000
struct mixel_lvds_phy {
struct device *dev;
void __iomem *csr_base;
void __iomem *ctrl_base;
struct mutex lock;
struct phy *phy;
struct clk *phy_clk;
};
static inline u32 phy_csr_read(struct phy *phy, unsigned int reg)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
return readl(lvds_phy->csr_base + reg);
}
static inline void phy_csr_write(struct phy *phy, unsigned int reg, u32 value)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
writel(value, lvds_phy->csr_base + reg);
}
static inline u32 phy_ctrl_read(struct phy *phy, unsigned int reg)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
return readl(lvds_phy->ctrl_base + reg);
}
static inline void phy_ctrl_write(struct phy *phy, unsigned int reg, u32 value)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
writel(value, lvds_phy->ctrl_base + reg);
}
void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy,
unsigned long phy_clk_rate)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
struct device *dev = lvds_phy->dev;
unsigned long serial_clk = 7 * phy_clk_rate;
unsigned long fvco = serial_clk;
int div = 1;
/*
* Choose an appropriate divider to meet the requirement of
* PLL VCO frequency range.
*
* --------- 640MHz ~ 1500MHz ------------ --------------
* | PLL VCO | ----------------> | CO divider | -> | serial clock |
* --------- ------------ --------------
* 1/2/4/8 div 7 * phy_clk_rate
*/
if (fvco < MIN_PLL_VCO_FREQ) {
do {
div *= 2;
fvco = serial_clk * div;
} while (fvco < MIN_PLL_VCO_FREQ);
if (div > 8)
div = 8;
}
/* final fvco */
fvco = serial_clk * div;
if (fvco < MIN_PLL_VCO_FREQ || fvco > MAX_PLL_VCO_FREQ)
dev_warn(dev, "PLL VCO frequency %lu is out of range\n", fvco);
clk_prepare_enable(lvds_phy->phy_clk);
mutex_lock(&lvds_phy->lock);
phy_ctrl_write(phy, CO, CO_DIV(div));
mutex_unlock(&lvds_phy->lock);
clk_disable_unprepare(lvds_phy->phy_clk);
clk_set_rate(lvds_phy->phy_clk, phy_clk_rate);
}
EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_phy_speed);
void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
u32 val;
clk_prepare_enable(lvds_phy->phy_clk);
mutex_lock(&lvds_phy->lock);
val = phy_csr_read(phy, SS);
val &= ~(CH_HSYNC_M(0) | CH_HSYNC_M(1));
if (active_high)
val |= (CH_PHSYNC(0) | CH_PHSYNC(1));
phy_csr_write(phy, SS, val);
mutex_unlock(&lvds_phy->lock);
clk_disable_unprepare(lvds_phy->phy_clk);
}
EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_hsync_pol);
void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
u32 val;
clk_prepare_enable(lvds_phy->phy_clk);
mutex_lock(&lvds_phy->lock);
val = phy_csr_read(phy, SS);
val &= ~(CH_VSYNC_M(0) | CH_VSYNC_M(1));
if (active_high)
val |= (CH_PVSYNC(0) | CH_PVSYNC(1));
phy_csr_write(phy, SS, val);
mutex_unlock(&lvds_phy->lock);
clk_disable_unprepare(lvds_phy->phy_clk);
}
EXPORT_SYMBOL_GPL(mixel_phy_combo_lvds_set_vsync_pol);
static int mixel_lvds_combo_phy_init(struct phy *phy)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
u32 val;
clk_prepare_enable(lvds_phy->phy_clk);
mutex_lock(&lvds_phy->lock);
val = phy_csr_read(phy, PHY_CTRL);
val &= ~(CCM_MASK | CA_MASK);
val |= (CCM(0x5) | CA(0x4) | RFB);
phy_csr_write(phy, PHY_CTRL, val);
val = phy_csr_read(phy, DPI);
val &= ~COLOR_CODE_MASK;
val |= BIT24;
phy_csr_write(phy, DPI, val);
mutex_unlock(&lvds_phy->lock);
clk_disable_unprepare(lvds_phy->phy_clk);
return 0;
}
static int mixel_lvds_combo_phy_power_on(struct phy *phy)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
u32 val;
clk_prepare_enable(lvds_phy->phy_clk);
mutex_lock(&lvds_phy->lock);
phy_ctrl_write(phy, PD_PLL, 0);
phy_ctrl_write(phy, PD_TX, 0);
val = phy_csr_read(phy, ULPS);
val &= ~ULPS_MASK;
phy_csr_write(phy, ULPS, val);
val = phy_csr_read(phy, PHY_CTRL);
val |= LVDS_EN;
phy_csr_write(phy, PHY_CTRL, val);
mutex_unlock(&lvds_phy->lock);
usleep_range(500, 1000);
return 0;
}
static int mixel_lvds_combo_phy_power_off(struct phy *phy)
{
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
u32 val;
mutex_lock(&lvds_phy->lock);
val = phy_csr_read(phy, PHY_CTRL);
val &= ~LVDS_EN;
phy_csr_write(phy, PHY_CTRL, val);
val = phy_csr_read(phy, ULPS);
val |= ULPS_MASK;
phy_csr_write(phy, ULPS, val);
phy_ctrl_write(phy, PD_TX, 1);
phy_ctrl_write(phy, PD_PLL, 1);
mutex_unlock(&lvds_phy->lock);
clk_disable_unprepare(lvds_phy->phy_clk);
return 0;
}
static const struct phy_ops mixel_lvds_combo_phy_ops = {
.init = mixel_lvds_combo_phy_init,
.power_on = mixel_lvds_combo_phy_power_on,
.power_off = mixel_lvds_combo_phy_power_off,
.owner = THIS_MODULE,
};
static int mixel_lvds_combo_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct phy_provider *phy_provider;
struct mixel_lvds_phy *lvds_phy;
lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
if (!lvds_phy)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
lvds_phy->csr_base = devm_ioremap(dev, res->start, SZ_256);
if (!lvds_phy->csr_base)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res)
return -ENODEV;
lvds_phy->ctrl_base = devm_ioremap(dev, res->start, SZ_4K);
if (!lvds_phy->ctrl_base)
return -ENOMEM;
lvds_phy->phy_clk = devm_clk_get(dev, "phy");
if (IS_ERR(lvds_phy->phy_clk)) {
dev_err(dev, "cannot get phy clock\n");
return PTR_ERR(lvds_phy->phy_clk);
}
lvds_phy->dev = dev;
mutex_init(&lvds_phy->lock);
lvds_phy->phy = devm_phy_create(dev, NULL, &mixel_lvds_combo_phy_ops);
if (IS_ERR(lvds_phy->phy)) {
dev_err(dev, "failed to create phy\n");
return PTR_ERR(lvds_phy->phy);
}
phy_set_drvdata(lvds_phy->phy, lvds_phy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
return PTR_ERR_OR_ZERO(phy_provider);
}
static const struct of_device_id mixel_lvds_combo_phy_of_match[] = {
{ .compatible = "mixel,lvds-combo-phy" },
{}
};
MODULE_DEVICE_TABLE(of, mixel_lvds_combo_phy_of_match);
static struct platform_driver mixel_lvds_combo_phy_driver = {
.probe = mixel_lvds_combo_phy_probe,
.driver = {
.name = "mixel-lvds-combo-phy",
.of_match_table = mixel_lvds_combo_phy_of_match,
}
};
module_platform_driver(mixel_lvds_combo_phy_driver);
MODULE_AUTHOR("NXP Semiconductor");
MODULE_DESCRIPTION("Mixel LVDS combo PHY driver");
MODULE_LICENSE("GPL v2");

302
drivers/phy/phy-mixel-lvds.c Normal file
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@ -0,0 +1,302 @@
/*
* Copyright 2017-2019 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/phy/phy-mixel-lvds.h>
#include <linux/platform_device.h>
#define SET 0x4
#define CLR 0x8
#define TOG 0xc
#define PHY_CTRL 0x0
#define M(n) (((n) & 0x3) << 17)
#define M_MASK 0x60000
#define CCM(n) (((n) & 0x7) << 14)
#define CCM_MASK 0x1c000
#define CA(n) (((n) & 0x7) << 11)
#define CA_MASK 0x3800
#define TST(n) (((n) & 0x3f) << 5)
#define TST_MASK 0x7e0
#define CH_EN(id) BIT(3 + (id))
#define NB BIT(2)
#define RFB BIT(1)
#define PD BIT(0)
#define PHY_STATUS 0x10
#define LOCK BIT(0)
#define PHY_SS_CTRL 0x20
#define CH_HSYNC_M(id) BIT(0 + ((id) * 2))
#define CH_VSYNC_M(id) BIT(1 + ((id) * 2))
#define CH_PHSYNC(id) BIT(0 + ((id) * 2))
#define CH_PVSYNC(id) BIT(1 + ((id) * 2))
struct mixel_lvds_phy {
struct phy *phy;
unsigned int id;
};
struct mixel_lvds_phy_priv {
struct device *dev;
void __iomem *base;
struct mutex lock;
struct clk *phy_clk;
struct mixel_lvds_phy *phys[2];
};
static inline u32 phy_read(struct phy *phy, unsigned int reg)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
return readl(priv->base + reg);
}
static inline void phy_write(struct phy *phy, unsigned int reg, u32 value)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
writel(value, priv->base + reg);
}
void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
u32 val;
/* assuming NB is zero - 7bits per channel */
clk_prepare_enable(priv->phy_clk);
mutex_lock(&priv->lock);
val = phy_read(phy, PHY_CTRL);
val &= ~M_MASK;
if (phy_clk_rate < 44000000)
val |= M(0x2);
else if (phy_clk_rate < 90000000)
val |= M(0x1);
else
val |= M(0x0);
phy_write(phy, PHY_CTRL, val);
mutex_unlock(&priv->lock);
clk_disable_unprepare(priv->phy_clk);
clk_set_rate(priv->phy_clk, phy_clk_rate);
}
EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_phy_speed);
void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
unsigned int id = lvds_phy->id;
u32 val;
clk_prepare_enable(priv->phy_clk);
mutex_lock(&priv->lock);
val = phy_read(phy, PHY_SS_CTRL);
val &= ~CH_HSYNC_M(id);
if (active_high)
val |= CH_PHSYNC(id);
phy_write(phy, PHY_SS_CTRL, val);
mutex_unlock(&priv->lock);
clk_disable_unprepare(priv->phy_clk);
}
EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_hsync_pol);
void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
unsigned int id = lvds_phy->id;
u32 val;
clk_prepare_enable(priv->phy_clk);
mutex_lock(&priv->lock);
val = phy_read(phy, PHY_SS_CTRL);
val &= ~CH_VSYNC_M(id);
if (active_high)
val |= CH_PVSYNC(id);
phy_write(phy, PHY_SS_CTRL, val);
mutex_unlock(&priv->lock);
clk_disable_unprepare(priv->phy_clk);
}
EXPORT_SYMBOL_GPL(mixel_phy_lvds_set_vsync_pol);
static int mixel_lvds_phy_init(struct phy *phy)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
u32 val;
clk_prepare_enable(priv->phy_clk);
mutex_lock(&priv->lock);
val = phy_read(phy, PHY_CTRL);
val &= ~(M_MASK | CCM_MASK | CA_MASK | TST_MASK | NB | PD);
val |= (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB);
phy_write(phy, PHY_CTRL, val);
mutex_unlock(&priv->lock);
clk_disable_unprepare(priv->phy_clk);
return 0;
}
static int mixel_lvds_phy_power_on(struct phy *phy)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
unsigned int id = lvds_phy->id;
clk_prepare_enable(priv->phy_clk);
mutex_lock(&priv->lock);
phy_write(phy, PHY_CTRL + SET, CH_EN(id));
mutex_unlock(&priv->lock);
usleep_range(500, 1000);
return 0;
}
static int mixel_lvds_phy_power_off(struct phy *phy)
{
struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent);
struct mixel_lvds_phy *lvds_phy = phy_get_drvdata(phy);
unsigned int id = lvds_phy->id;
mutex_lock(&priv->lock);
phy_write(phy, PHY_CTRL + CLR, CH_EN(id));
mutex_unlock(&priv->lock);
clk_disable_unprepare(priv->phy_clk);
return 0;
}
static const struct phy_ops mixel_lvds_phy_ops = {
.init = mixel_lvds_phy_init,
.power_on = mixel_lvds_phy_power_on,
.power_off = mixel_lvds_phy_power_off,
.owner = THIS_MODULE,
};
static int mixel_lvds_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *child;
struct resource *res;
struct phy_provider *phy_provider;
struct mixel_lvds_phy_priv *priv;
struct mixel_lvds_phy *lvds_phy;
struct phy *phy;
u32 phy_id;
int ret;
if (!np)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_ioremap(dev, res->start, SZ_256);
if (!priv->base)
return -ENOMEM;
priv->dev = dev;
priv->phy_clk = devm_clk_get(dev, "phy");
if (IS_ERR(priv->phy_clk)) {
dev_err(dev, "cannot get phy clock\n");
return PTR_ERR(priv->phy_clk);
}
mutex_init(&priv->lock);
dev_set_drvdata(dev, priv);
for_each_available_child_of_node(np, child) {
if (of_property_read_u32(child, "reg", &phy_id)) {
dev_err(dev, "missing reg property in node %s\n",
child->name);
ret = -EINVAL;
goto put_child;
}
if (phy_id >= ARRAY_SIZE(priv->phys)) {
dev_err(dev, "invalid reg in node %s\n", child->name);
ret = -EINVAL;
goto put_child;
}
if (priv->phys[phy_id]) {
dev_err(dev, "duplicated phy id: %u\n", phy_id);
ret = -EINVAL;
goto put_child;
}
lvds_phy = devm_kzalloc(dev, sizeof(*lvds_phy), GFP_KERNEL);
if (!lvds_phy) {
ret = -ENOMEM;
goto put_child;
}
phy = devm_phy_create(dev, child, &mixel_lvds_phy_ops);
if (IS_ERR(phy)) {
dev_err(dev, "failed to create phy\n");
ret = PTR_ERR(phy);
goto put_child;
}
lvds_phy->phy = phy;
lvds_phy->id = phy_id;
priv->phys[phy_id] = lvds_phy;
phy_set_drvdata(phy, lvds_phy);
}
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
return PTR_ERR_OR_ZERO(phy_provider);
put_child:
of_node_put(child);
return ret;
}
static const struct of_device_id mixel_lvds_phy_of_match[] = {
{ .compatible = "mixel,lvds-phy" },
{}
};
MODULE_DEVICE_TABLE(of, mixel_lvds_phy_of_match);
static struct platform_driver mixel_lvds_phy_driver = {
.probe = mixel_lvds_phy_probe,
.driver = {
.name = "mixel-lvds-phy",
.of_match_table = mixel_lvds_phy_of_match,
}
};
module_platform_driver(mixel_lvds_phy_driver);
MODULE_AUTHOR("NXP Semiconductor");
MODULE_DESCRIPTION("Mixel LVDS PHY driver");
MODULE_LICENSE("GPL v2");

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include/linux/phy/phy-mixel-lvds-combo.h Normal file
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/*
* Copyright 2017-2019 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef PHY_MIXEL_LVDS_COMBO_H_
#define PHY_MIXEL_LVDS_COMBO_H_
#include "phy.h"
#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS_COMBO)
void mixel_phy_combo_lvds_set_phy_speed(struct phy *phy,
unsigned long phy_clk_rate);
void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy, bool active_high);
void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy, bool active_high);
#else
static inline void
mixel_phy_combo_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate)
{
}
static inline void mixel_phy_combo_lvds_set_hsync_pol(struct phy *phy,
bool active_high)
{
}
static inline void mixel_phy_combo_lvds_set_vsync_pol(struct phy *phy,
bool active_high)
{
}
#endif
#endif /* PHY_MIXEL_LVDS_COMBO_H_ */

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/*
* Copyright 2017-2019 NXP
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*/
#ifndef PHY_MIXEL_LVDS_H_
#define PHY_MIXEL_LVDS_H_
#include "phy.h"
#if IS_ENABLED(CONFIG_PHY_MIXEL_LVDS)
void mixel_phy_lvds_set_phy_speed(struct phy *phy, unsigned long phy_clk_rate);
void mixel_phy_lvds_set_hsync_pol(struct phy *phy, bool active_high);
void mixel_phy_lvds_set_vsync_pol(struct phy *phy, bool active_high);
#else
static inline void mixel_phy_lvds_set_phy_speed(struct phy *phy,
unsigned long phy_clk_rate)
{
}
static inline void mixel_phy_lvds_set_hsync_pol(struct phy *phy,
bool active_high)
{
}
static inline void mixel_phy_lvds_set_vsync_pol(struct phy *phy,
bool active_high)
{
}
#endif
#endif /* PHY_MIXEL_LVDS_H_ */