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MLK-23216-7 usb: dwc3: imx8mp: Add device tree binding
iMX8MP USB3 integrate Synopsys DesignWare Cores SuperSpeed USB 3.0 Controller 3.30b IP, the glue layer is added to support wakeup from low power mode. Reviewed-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Li Jun <jun.li@nxp.com>
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Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt
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Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt
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NXP imx8M Plus DWC3 glue logic
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This file documents the parameters for the dwc3-imx8mp driver.
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This driver controls the glue logic used to configure the dwc3 core on
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imx8mp based platforms.
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Required properties:
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- compatible : must be "fsl,imx8mp-dwc3"
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- reg : glue logic base address and size
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- clocks : A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names : Should contain the following:
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"bus" System bus AXI clock
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"sleep" Sleep clock, used for wakeup.
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- interrupts : specifies interrupt from controller wrapper used
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to wakeup from low power/susepnd state.
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Sub-nodes:
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The dwc3 core should be added as subnode to imx8mp DWC3 glue as shown in the
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example below. The DT binding details of dwc3 can be found in:
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Documentation/devicetree/bindings/usb/dwc3.txt
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Example:
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usb3_0: usb@32f10100 {
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compatible = "fsl,imx8mp-dwc3";
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reg = <0 0x32f10100 0 0x8>;
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clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>,
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "bus", "sleep";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <500000000>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usb_dwc3_0: dwc3@38100000 {
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compatible = "snps,dwc3";
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reg = <0 0x38100000 0 0x10000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy0>, <&usb3_phy0>;
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phy-names = "usb2-phy", "usb3-phy";
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xhci-no-64bit-support;
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usb3-resume-missing-cas;
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snps,dis_u2_susphy_quirk;
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snps,dis_u3_susphy_quirk;
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status = "disabled";
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};
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};
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