This header file should not be included in other header files. Remove it
and use a forward declaration and un-inlining of dev_get_clk_ptr()
instead.
Fix up the kendryte header files to avoid build errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Also move the inline function out into a C file. We should not include C
code in headers.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Also drop asm/io.h
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Drop the common.h inclusion also.
Signed-off-by: Simon Glass <sjg@chromium.org>
This file should not include common.h and dm.h so remove them. Also move
the inclusion of this file to after the normal includes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
This header file should not be included in other header files. Remove it
and use a forward declaration instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
The -ENODEV error value in spi_nor_read_id() is incorrect since there
clearly is a device - it just cannot be supported. Use -ENOMEDIUM instead
which has the virtue of being less common.
Fix the return value in spi_nor_scan().
Also there are a few printf() statements which should be debug() since
they bloat the code with unused strings at present. Fix those while here.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some cases SPL needs to be able to erase but TPL just needs to read.
Allow these to have separate settings for SPI_FLASH_TINY.
Signed-off-by: Simon Glass <sjg@chromium.org>
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Indexes of reset signals available in PRCI driver are also
defined in include/dt-bindings/reset/sifive-fu540-prci.h.
So use those instead of defining new ones again within the
fu540-prci driver.
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Since commit 7812bbdc37 ("video: Correctly handle multiple
framebuffers") the vidconsole output is missing on the primary
display on boards with two IPU units (all i.MX6Q/D based boards).
The base address of the allocated framebuffer is not correctly
programmed in the display controller. Fix it.
Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Soeren Moch <smoch@web.de>
Adds support for SPI controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds a simple clock driver for the Marvell Octeon MIPS SoC
family. Its for IO clock rate passing via DT in some of the Octeon
driver, like I2C. So that we don't need to use the non-mainline API
octeon_get_io_clock().
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Lukasz Majewski <lukma@denx.de>
Add support for GPIO controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Continuing with the approach in commit <addf358bac1d2bd0> rename
additional drivers to allow the OF_PLATDATA support.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
After enabling OF_PLATDATA support to both MMC and GPIO drivers add the
support for card detection.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Continuing with the OF_PLATADATA support for iMX6 to reduce SPL
footprint, add it to mxc_gpio. Thanks to this, it will be possible to
enable card detection on MMC driver.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
In order to reduce the footprint of SPL by removing dtb and library
overhead, add OF_PLATDATA support to fsl_esdhc_imx. This initial
approach does not support card detection, which will be enabled after
adding OF_PLATDATA support to GPIO.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As discussed in commit <addf358bac1d2bd0> rename fsl_esdhc_imx
driver to allow the OF_PLATDATA support.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In our Python tests we expect to see the word "resetting". It may be
truncated if we reset before the serial console buffer is transferred.
Wait for 100 ms between the "resetting ..." message and the actual reset
like we do when powering off.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Refactor to allow any arch to create SPI-flash images
New button uclass
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Merge tag 'dm-pull-28jul20' of git://git.denx.de/u-boot-dm
Use binman instead of one of the Rockchip build scripts
Refactor to allow any arch to create SPI-flash images
New button uclass
- fix SPL boot issue due to early dbgmcu_init() call
- fix SPL boot issue due to dcache memory region configuration
- add support of CONFIG_ENV_IS_IN_MMC
- add specific SD/eMMC partition for U-Boot enviromnent
- enable env in SPL
- use "env info -q" to remove log during boot
- remove env location override for dh_stm32mp1
- update management of misc_read
- check result of find_mmc_device in stm32prog
- use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc
- enable CMD_ADTIMG flag to handle Android images
- device tree alignment with Linux Kernel v5.8-rc1
- remove hnp-srp-disable for usbotg on dk1
- add reset support to uart nodes on stm32mp15x
- use correct weak function name spl_board_prepare_for_linux
- use cd-gpios for ST and DHSOM boards
- add seeed studio odyssey-stm32mp157c board support
- move ethernet PHY into SoM DT
- add DHSOM based DRC02 board support
Add optee based bnxt fw load driver.
bnxt is Broadcom NetXtreme controller Ethernet card.
This driver is used to load bnxt firmware binary using OpTEE.
Signed-off-by: Vikas Gupta <vikas.gupta@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- nexell_display.c: Changed to DM, CONFIG_FB_ADDR can not be used
anymore because framebuffer is allocated by video_reserve() in
video-uclass.c. Therefore code changed appropriately.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Low level functions for DPC (Display Controller) and Makefile for all
nexell video low level functions.
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
- doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt added.
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- driver changed to DM.
- pinctrl-driver/dt is used now instead of configuring the mmc I/O-pins
in the mmc-driver.
- nexell_dwmmc_ofdata_to_platdata() reworked, i.e. valid default values
are used now (where possible) and the appropriate if-blocks have
been removed.
- new dt-property "mmcboost" is used now instead of "CONFIG_BOOST_MMC"
which was not defined anywhere.
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- i2c/nx_i2c.c: Some adaptions mainly because of changes in
"struct udevice".
- several Bugfixes in nx_i2c.c.
- the driver has been for s5p6818 only. Code extended appropriately
in order s5p4418 is also working.
- "probe_chip" added.
- pinctrl-driver/dt is used instead of configuring the i2c I/O-pins
in the i2c-driver.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- livetree API (dev_read_...) is used instead of fdt one (fdt...).
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
Snapdragon SoCs and IPQ40xx use common TLMM IP,
so existing driver supports IPQ40xx as well.
So lets simply add a compatible for IPQ40xx.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
IPQ40xx and currently supported Snapdragon boards don't use the same one
so enable reading it from DT, if no DT property is found default value
is the same as the previous define.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
The pins for the MMC controller weren't being set up correctly because the
pinctrl driver only sets the GPIO pullup/pulldown config and doesn't
handle the special cases with PUPD/R0/R1 control.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
The sgmii mode init flow is almost the same for all mediatek SoC, the
only difference is the register offset(SGMSYS_GEN2_SPEED) is 0x2028
in the old chip(mt7622) but changed to 0x128 for the newer chip(mt7629
and the following chips).
Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
Add a simple driver which allows use of buttons attached to GPIOs.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Add a new uclass for button that implements two functions:
- button_get_by_label
- button_get_status
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
After latest improvements on OF_PLATDATA struct names are generated
based on driver name instead of compatible strings. With this in mind,
using aliases in drivers are not longer needed.
This patch removes code that tried to handle these kind of aliases to
improve readability.
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while disabling vdd supply. This way the driver doesn't see an error
when disabling an always-on regulator.
This patch is needed since the commit f93fab3126 ("Revert 'power:
regulator: Return success on attempt to disable an always-on regulator'")
and use the API introduced by commit cc4a224af2 ("power: regulator:
Introduce regulator_set_enable_if_allowed api").
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
cleanups
- fsl-crypto: RNG support and bug fixes
This checks and handles RX errors on the Amlogic UART controller
after experiencing errors on the Khadas VIM3 & VIM3L when UART AO A
lines are not connected.
When the RX line is not connected, the first byte is erroneous and breaks
the U-Boot autoboot, breaking automatic boot.
This checks and drops any erroneous RX byte on pending and getc callbacks
to avoid returning true to pending when an error byte is in the FIFO.
Fixes: bfcef28ae4 ("arm: add initial support for Amlogic Meson and ODROID-C2")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Guillaume La Roque <glaroque@baylibre.com>
Currently checkpatch is not happy about this file:
total: 14 errors, 2 warnings, 7 checks, 359 lines checked
Improve the coding style so that it can now report:
total: 0 errors, 0 warnings, 6 checks, 360 lines checked
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
According to Server Base System Architecture (SBSA) specification,
the SBSA Generic Watchdog has two stage timeouts: the first signal
(WS0) is for alerting the system by interrupt, the second one (WS1) is a
real hardware reset.
More details about the hardware specification of this device:
ARM DEN0029B - Server Base System Architecture (SBSA)
This driver can operate ARM SBSA Generic Watchdog as a single stage
In the single stage mode, when the timeout is reached, your system
will be reset by WS1. The first signal (WS0) is ignored.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add Root Complex and Endpoint mode specific config entries, such that
it's feasible to enable the RC and/or EP mode driver indepently.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the PCIe EP mode support for lx2160a-v2 platform.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the INBOUND configuration for VFs of PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Due to the ls2085a and ls2080a use different way to set the BAR size,
so add the BAR size init code here.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The VF_BARn_REG register's Prefetchable and Type bit fields
are overwritten by a write to VF's BAR Mask register.
workaround: Before writing to the VF_BARn_MASK_REG register,
write 0b to the PCIE_MISC_CONTROL_1_OFF register.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Add the multiple function support for Layerscape platform, some PEXs
of Layerscaple platform have more than one PF.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Split the RC and EP driver, and reimplement the EP driver base on
the EP framework.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Move i2c_early_init_f to common function
to initialize baudrate of i2c
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Register the random number generator with the rng subsystem in u-boot.
This way it can be used by EFI as well as for the 'rng' command.
Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
If it is already instantiated tear it down first and then reinstanciate
it again with prediction resistance.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a
POR. Otherwise the RNG4 will throw an error.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Since Era 10, the version registers changed. Add the version registers
and use them on newer modules.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
We need the era in other modules, too. For example, to get the RNG
version.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Align the status line with all the other output in U-Boot.
Before the change:
DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
After the change:
DDR 3.9 GiB (DDR3, 32-bit, CL=11, ECC on)
SEC0: RNG instantiated
WDT: Started with servicing (60s timeout)
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The value 0 assigned to final is overwritten before ever being used.
Remove the assignment.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The sequence of arguments should match the format string.
For printing unsigned numbers we should use %u.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.
This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The correct setting for the RGMII ports on LS1012ARDB is to
enable delay on both Rx and Tx so the interface mode used should
be PHY_INTERFACE_MODE_RGMII_ID
Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
On aarch64 running with dcache off, will result in an unaligned access
exception:
=> dcache off
=> hash sha1 $kernel_addr_r 100
"Synchronous Abort" handler, esr 0x96000061
elr: 00000000960317d8 lr : 00000000960316a4 (reloc)
elr: 00000000fbd787d8 lr : 00000000fbd786a4
[..]
The compiler emits a "stur x1, [x0, #12]". x1 is might just be 32 bit
aligned pointer. Remove the unused u64 element from the union to drop
the minimal alignment to 32 bit. Also remove the union, because it is
no more needed.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.
These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.
To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/
The semantic patch that makes this change is as follows:
<smpl>
@@
expression dev;
@@
-devfdt_get_addr(dev)
+dev_read_addr(dev)
</smpl>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.
One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:
priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
if (!priv->regs)
return -EINVAL;
devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.
dev_read_addr_ptr() returns NULL on error, so this error check
will work.
I generated this commit by the following command:
$ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'
I manually fixed drivers/usb/host/ehci-mx6.c
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add a sandbox SOC driver, and some tests for the SOC uclass.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.
This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.
Signed-off-by: Simon Glass <sjg@chromium.org>
With all the changes in place, add support for DM into the
dc2114x driver.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Split the common code from the non-DM code, so it can be reused by
the DM code later. As always, the recv() function had to be split
into the actual receiving part and free_pkt part to fit with the
DM.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Split the RX data check from the rest of the RX function, so that
the check can be performed separately from the processing of the
packet and the release of the received packet once the processing
is finished.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
The RX/TX DMA descriptor rings are per-device-instance private data,
so move them into the private data.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
This is a trick in preparation for adding DM support. By passing in
the PCI BDF into the phys_to_bus() macros and calling that dev, we
can substitute dev with udevice when DM support lands and do minor
adjustment to the macros to support both DM and non-DM operation.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
This patch replaces the various uses of struct eth_device for accessing
device private data with struct dc2114x_priv, which is compatible both
with DM and non-DM operation.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Introduce dc2114x_priv, which is a super-structure around eth_device
and tracks per-device state and the device IO address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
The current dc21x4x driver accesses its memory mapped registers directly
instead of using the standard I/O accessors. This can cause problems on
some systems as the accesses can get out of order. So convert the direct
volatile dereferences to use the normal in/out macros.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
This code is never used, remove it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Add Kconfig entries for the dc2114x driver and convert various boards.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
For the usage in this driver, the chips are identical,
so support all of them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Use this macro to fully fill the PCI device ID table. This is mandatory
for the DM PCI support, which checks all the fields.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
