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pci: layerscape: Modify the ls_pcie_dump_atu function

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Modify the ls_pcie_dump_atu function, make it can print the INBOUND
windows registers.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Xiaowei Bao 2020-07-09 23:31:40 +08:00 committed by Priyanka Jain
parent 83bf32e680
commit 80b5a662b7
4 changed files with 18 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/pci/pcie_layerscape.c
View File

@ -121,24 +121,25 @@ void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
}
void ls_pcie_dump_atu(struct ls_pcie *pcie)
void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
{
int i;
int win_idx;
for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
PCIE_ATU_VIEWPORT);
debug("iATU%d:\n", i);
for (win_idx = 0; win_idx < win_num; win_idx++) {
dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
debug("iATU%d:\n", win_idx);
debug("\tLOWER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
debug("\tUPPER PHYS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
debug("\tLOWER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
debug("\tUPPER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LIMIT));
if (type == PCIE_ATU_REGION_OUTBOUND) {
debug("\tLOWER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
debug("\tUPPER BUS 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
debug("\tLIMIT 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_LIMIT));
}
debug("\tCR1 0x%08x\n",
dbi_readl(pcie, PCIE_ATU_CR1));
debug("\tCR2 0x%08x\n",

2
drivers/pci/pcie_layerscape.h
View File

@ -185,7 +185,7 @@ void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
u64 phys, u64 bus_addr, u64 size);
void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
int type, int idx, int bar, u64 phys);
void ls_pcie_dump_atu(struct ls_pcie *pcie);
void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type);
int ls_pcie_link_up(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie);
void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie);

3
drivers/pci/pcie_layerscape_ep.c
View File

@ -227,6 +227,9 @@ static void ls_pcie_setup_ep(struct ls_pcie_ep *pcie_ep)
ls_pcie_ep_setup_atu(pcie_ep, 0);
}
ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM_SRIOV,
PCIE_ATU_REGION_INBOUND);
ls_pcie_ep_enable_cfg(pcie_ep);
}

2
drivers/pci/pcie_layerscape_rc.c
View File

@ -115,7 +115,7 @@ static void ls_pcie_setup_atu(struct ls_pcie_rc *pcie_rc)
pref->bus_start,
pref->size);
ls_pcie_dump_atu(pcie);
ls_pcie_dump_atu(pcie, PCIE_ATU_REGION_NUM, PCIE_ATU_REGION_OUTBOUND);
}
/* Return 0 if the address is valid, -errno if not valid */