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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq 

- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes
This commit is contained in:
Tom Rini 2020-07-27 15:18:15 -04:00
parent fc3414212e 636999f21c
commit 8d1fc6fb89
181 changed files with 2317 additions and 1084 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -689,6 +689,7 @@ M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
I2C
M: Heiko Schocher <hs@denx.de>

9
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -23,6 +23,7 @@ config ARCH_LS1012A
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
@ -67,7 +68,6 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009929
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
@ -75,7 +75,7 @@ config ARCH_LS1043A
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC if !DM_I2C
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
@ -108,7 +108,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC if !DM_I2C
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
@ -591,9 +591,6 @@ config SYS_FSL_ERRATUM_A009635
config SYS_FSL_ERRATUM_A009660
bool
config SYS_FSL_ERRATUM_A009929
bool
config SYS_FSL_ERRATUM_A050382
bool

2
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View File

@ -6,7 +6,7 @@ obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_MP) += mp.o spintable.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
endif
obj-$(CONFIG_SPL) += spl.o

9
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -54,7 +54,6 @@ void ft_fixup_cpu(void *blob)
fdt32_t *reg;
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
u32 mask = cpu_pos_mask();
int off_prev = -1;
@ -145,11 +144,11 @@ remove_psci_node:
"cpu", 4);
}
fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
*boot_code_size);
fdt_add_mem_rsv(blob, (uintptr_t)secondary_boot_code_start,
secondary_boot_code_size);
#if CONFIG_IS_ENABLED(EFI_LOADER)
efi_add_memory_map((uintptr_t)&secondary_boot_code, *boot_code_size,
EFI_RESERVED_MEMORY_TYPE);
efi_add_memory_map((uintptr_t)secondary_boot_code_start,
secondary_boot_code_size, EFI_RESERVED_MEMORY_TYPE);
#endif
}
#endif

165
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -11,14 +11,16 @@
#include <asm/gic.h>
#include <asm/macro.h>
#include <asm/arch-fsl-layerscape/soc.h>
#ifdef CONFIG_MP
#include <asm/arch/mp.h>
#endif
#ifdef CONFIG_FSL_LSCH3
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#endif
#include <asm/u-boot.h>
.align 3
.weak secondary_boot_addr
secondary_boot_addr:
.quad 0
/* Get GIC offset
* For LS1043a rev1.0, GIC base address align with 4k.
* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
@ -208,8 +210,13 @@ ENTRY(lowlevel_init)
branch_if_master x0, x1, 2f
#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func
blr x0
/*
* Formerly, here was a jump to secondary_boot_func, but we just
* return early here and let the generic code in start.S handle
* the jump to secondary_boot_func.
*/
mov lr, x29 /* Restore LR */
ret
#endif
2:
@ -419,151 +426,3 @@ ENTRY(__asm_flush_l3_dcache)
ret
ENDPROC(__asm_flush_l3_dcache)
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
.ltorg
/* Using 64 bit alignment since the spin table is accessed as data */
.align 4
.global secondary_boot_code
/* Secondary Boot Code starts here */
secondary_boot_code:
.global __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2
ENTRY(secondary_boot_func)
/*
* MPIDR_EL1 Fields:
* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
* MPIDR[7:2] = AFF0_RES
* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
* MPIDR[23:16] = AFF2_CLUSTERID
* MPIDR[24] = MT
* MPIDR[29:25] = RES0
* MPIDR[30] = U
* MPIDR[31] = ME
* MPIDR[39:32] = AFF3
*
* Linear Processor ID (LPID) calculation from MPIDR_EL1:
* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
* until AFF2_CLUSTERID and AFF3 have non-zero values)
*
* LPID = MPIDR[15:8] | MPIDR[1:0]
*/
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
/*
* offset of the spin table element for this core from start of spin
* table (each elem is padded to 64 bytes)
*/
lsl x1, x10, #6
ldr x0, =__spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
ldr x0, =__real_cntfrq
ldr x0, [x0]
msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
dsb sy
#if defined(CONFIG_GICV3)
gic_wait_for_interrupt_m x0
#elif defined(CONFIG_GICV2)
bl get_gic_offset
mov x0, x1
gic_wait_for_interrupt_m x0, w1
#endif
slave_cpu:
wfe
ldr x0, [x11]
cbz x0, slave_cpu
#ifndef CONFIG_ARMV8_SWITCH_TO_EL1
mrs x1, sctlr_el2
#else
mrs x1, sctlr_el1
#endif
tbz x1, #25, cpu_is_le
rev x0, x0 /* BE to LE conversion */
cpu_is_le:
ldr x5, [x11, #24]
cbz x5, 1f
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, secondary_switch_to_el1
ldr x5, =ES_TO_AARCH64
#else
ldr x4, [x11]
ldr x5, =ES_TO_AARCH32
#endif
bl secondary_switch_to_el2
1:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x4, secondary_switch_to_el1
#else
ldr x4, [x11]
#endif
ldr x5, =ES_TO_AARCH64
bl secondary_switch_to_el2
ENDPROC(secondary_boot_func)
ENTRY(secondary_switch_to_el2)
switch_el x6, 1f, 0f, 0f
0: ret
1: armv8_switch_to_el2_m x4, x5, x6
ENDPROC(secondary_switch_to_el2)
ENTRY(secondary_switch_to_el1)
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
lsl x1, x10, #6
ldr x0, =__spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
ldr x4, [x11]
ldr x5, [x11, #24]
cbz x5, 2f
ldr x5, =ES_TO_AARCH32
bl switch_to_el1
2: ldr x5, =ES_TO_AARCH64
switch_to_el1:
switch_el x6, 0f, 1f, 0f
0: ret
1: armv8_switch_to_el1_m x4, x5, x6
ENDPROC(secondary_switch_to_el1)
/* Ensure that the literals used by the secondary boot code are
* assembled within it (this is required so that we can protect
* this area with a single memreserve region
*/
.ltorg
/* 64 bit alignment for elements accessed as data */
.align 4
.global __real_cntfrq
__real_cntfrq:
.quad COUNTER_FREQUENCY
.globl __secondary_boot_code_size
.type __secondary_boot_code_size, %object
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code
#endif

80
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -6,6 +6,7 @@
#include <common.h>
#include <cpu_func.h>
#include <image.h>
#include <log.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
@ -14,17 +15,14 @@
#include <linux/delay.h>
#include "cpu.h"
#include <asm/arch-fsl-layerscape/soc.h>
#include <efi_loader.h>
DECLARE_GLOBAL_DATA_PTR;
void *get_spin_tbl_addr(void)
{
return &__spin_table;
}
phys_addr_t determine_mp_bootpg(void)
{
return (phys_addr_t)&secondary_boot_code;
/* the spin table is at the beginning */
return secondary_boot_code_start;
}
void update_os_arch_secondary_cores(uint8_t os_arch)
@ -43,7 +41,7 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
}
#ifdef CONFIG_FSL_LSCH3
void wake_secondary_core_n(int cluster, int core, int cluster_cores)
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
@ -80,7 +78,11 @@ int fsl_layerscape_wake_seconday_cores(void)
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
u64 *table;
#ifdef CONFIG_EFI_LOADER
u64 reloc_addr = U32_MAX;
efi_status_t ret;
#endif
#ifdef COUNTER_FREQUENCY_REAL
/* update for secondary cores */
@ -89,16 +91,49 @@ int fsl_layerscape_wake_seconday_cores(void)
(unsigned long)&__real_cntfrq + 8);
#endif
#ifdef CONFIG_EFI_LOADER
/*
* EFI will reserve 64kb for its runtime services. This will probably
* overlap with our spin table code, which is why we have to relocate
* it.
* Keep this after the __real_cntfrq update, so we have it when we
* copy the complete section here.
*/
ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
EFI_RESERVED_MEMORY_TYPE,
efi_size_in_pages(secondary_boot_code_size),
&reloc_addr);
if (ret == EFI_SUCCESS) {
debug("Relocating spin table from %llx to %llx (size %lx)\n",
(u64)secondary_boot_code_start, reloc_addr,
secondary_boot_code_size);
memcpy((void *)reloc_addr, secondary_boot_code_start,
secondary_boot_code_size);
flush_dcache_range(reloc_addr,
reloc_addr + secondary_boot_code_size);
/* set new entry point for secondary cores */
secondary_boot_addr += (void *)reloc_addr -
secondary_boot_code_start;
flush_dcache_range((unsigned long)&secondary_boot_addr,
(unsigned long)&secondary_boot_addr + 8);
/* this will be used to reserve the memory */
secondary_boot_code_start = (void *)reloc_addr;
}
#endif
cores = cpu_mask();
/* Clear spin table so that secondary processors
* observe the correct value after waking up from wfe.
*/
table = get_spin_tbl_addr();
memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
flush_dcache_range((unsigned long)table,
(unsigned long)table +
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
#ifdef CONFIG_FSL_LSCH3
gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
@ -168,11 +203,11 @@ int fsl_layerscape_wake_seconday_cores(void)
udelay(10);
}
if (timeout <= 0) {
printf("Not all cores (0x%x) are up (0x%x)\n",
cores, cpu_up_mask);
printf("CPU: Failed to bring up some cores (mask 0x%x)\n",
cores ^ cpu_up_mask);
return 1;
}
printf("All (%d) cores are up.\n", hweight32(cores));
printf("CPU: %d cores online\n", hweight32(cores));
return 0;
}
@ -189,9 +224,9 @@ static int is_pos_valid(unsigned int pos)
int is_core_online(u64 cpu_id)
{
u64 *table;
u64 *table = get_spin_tbl_addr();
int pos = id_to_core(cpu_id);
table = (u64 *)get_spin_tbl_addr() + pos * WORDS_PER_SPIN_TABLE_ENTRY;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
}
@ -237,18 +272,16 @@ static int core_to_pos(int nr)
int cpu_status(u32 nr)
{
u64 *table;
u64 *table = get_spin_tbl_addr();
int pos;
if (nr == 0) {
table = (u64 *)get_spin_tbl_addr();
printf("table base @ 0x%p\n", table);
} else {
pos = core_to_pos(nr);
if (pos < 0)
return -1;
table = (u64 *)get_spin_tbl_addr() + pos *
WORDS_PER_SPIN_TABLE_ENTRY;
table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
printf("table @ 0x%p\n", table);
printf(" addr - 0x%016llx\n",
table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
@ -264,7 +297,7 @@ int cpu_status(u32 nr)
int cpu_release(u32 nr, int argc, char *const argv[])
{
u64 boot_addr;
u64 *table = (u64 *)get_spin_tbl_addr();
u64 *table = get_spin_tbl_addr();
int pos;
pos = core_to_pos(nr);
@ -277,11 +310,12 @@ int cpu_release(u32 nr, int argc, char *const argv[])
flush_dcache_range((unsigned long)table,
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
/*
* When the first release command runs, all cores are set to go. Those
* without a valid entry address will be trapped by "wfe". "sev" kicks
* them off to check the address again. When set, they continue to run.
* The secondary CPUs polling the spin-table above for a non-zero
* value. To save power "wfe" is called. Thus call "sev" here to
* wake the CPUs and let them check the spin-table again (see
* slave_cpu loop in lowlevel.S)
*/
asm volatile("sev");

15
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -445,20 +445,6 @@ int get_core_volt_from_fuse(void)
}
#elif defined(CONFIG_FSL_LSCH2)
static void erratum_a009929(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
rstrqmr1 |= 0x00000400;
gur_out32(&gur->rstrqmr1, rstrqmr1);
writel(0x01000000, dcsr_cop_ccp);
#endif
}
/*
* This erratum requires setting a value to eddrtqcr1 to optimal
* the DDR performance. The eddrtqcr1 register is in SCFG space
@ -724,7 +710,6 @@ void fsl_lsch2_early_init_f(void)
#endif
/* Erratum */
erratum_a008850_early(); /* part 1 of 2 */
erratum_a009929();
erratum_a009660();
erratum_a010539();
erratum_a009008();

118
arch/arm/cpu/armv8/fsl-layerscape/spintable.S Normal file
View File

@ -0,0 +1,118 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014-2015 Freescale Semiconductor
* Copyright 2019 NXP
*/
#include <config.h>
#include <linux/linkage.h>
#include <asm/macro.h>
#include <asm/system.h>
#include <asm/arch/mp.h>
.align 3
.global secondary_boot_addr
secondary_boot_addr:
.quad __secondary_boot_func
.global secondary_boot_code_start
secondary_boot_code_start:
.quad __secondary_boot_code_start
.global secondary_boot_code_size
secondary_boot_code_size:
.quad __secondary_boot_code_end - __secondary_boot_code_start
/* Using 64 bit alignment since the spin table is accessed as data */
.align 3
/* Secondary Boot Code starts here */
__secondary_boot_code_start:
__spin_table:
.space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
.align 2
__secondary_boot_func:
/*
* MPIDR_EL1 Fields:
* MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
* MPIDR[7:2] = AFF0_RES
* MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
* MPIDR[23:16] = AFF2_CLUSTERID
* MPIDR[24] = MT
* MPIDR[29:25] = RES0
* MPIDR[30] = U
* MPIDR[31] = ME
* MPIDR[39:32] = AFF3
*
* Linear Processor ID (LPID) calculation from MPIDR_EL1:
* (We only use AFF0_CPUID and AFF1_CLUSTERID for now
* until AFF2_CLUSTERID and AFF3 have non-zero values)
*
* LPID = MPIDR[15:8] | MPIDR[1:0]
*/
mrs x0, mpidr_el1
ubfm x1, x0, #8, #15
ubfm x2, x0, #0, #1
orr x10, x2, x1, lsl #2 /* x10 has LPID */
ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
/*
* offset of the spin table element for this core from start of spin
* table (each elem is padded to 64 bytes)
*/
lsl x1, x10, #6
adr x0, __spin_table
/* physical address of this cpus spin table element */
add x11, x1, x0
adr x0, __real_cntfrq
ldr x0, [x0]
msr cntfrq_el0, x0 /* set with real frequency */
str x9, [x11, #16] /* LPID */
mov x4, #1
str x4, [x11, #8] /* STATUS */
dsb sy
1:
wfe
ldr x4, [x11]
cbz x4, 1b
mrs x1, sctlr_el2
tbz x1, #25, 2f
rev x4, x4 /* BE to LE conversion */
2:
ldr x6, =ES_TO_AARCH64
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
adr x5, 3f
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x5, x6, x7
#endif
3:
ldr x7, [x11, #24] /* ARCH_COMP */
cbz x7, 4f
ldr x6, =ES_TO_AARCH32
4:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
switch_el x7, _dead_loop, 0f, _dead_loop
0: armv8_switch_to_el1_m x4, x6, x7
#else
switch_el x7, 0f, _dead_loop, _dead_loop
0: armv8_switch_to_el2_m x4, x6, x7
#endif
_dead_loop:
wfe
b _dead_loop
/* Ensure that the literals used by the secondary boot code are
* assembled within it (this is required so that we can protect
* this area with a single memreserve region
*/
.ltorg
/* 64 bit alignment for elements accessed as data */
.align 3
.global __real_cntfrq
__real_cntfrq:
.quad COUNTER_FREQUENCY
/* Secondary Boot Code ends here */
__secondary_boot_code_end:

74
arch/arm/dts/fsl-ls1028a-qds.dtsi
View File

@ -15,20 +15,94 @@
compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
aliases {
spi0 = &fspi;
spi1 = &dspi0;
spi2 = &dspi1;
spi3 = &dspi2;
};
};
&dspi0 {
bus-num = <0>;
status = "okay";
dflash0: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi1 {
bus-num = <0>;
status = "okay";
dflash3: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi2 {
bus-num = <0>;
status = "okay";
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
};
&esdhc0 {

33
arch/arm/dts/fsl-ls1046a.dtsi
View File

@ -257,6 +257,17 @@
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep@3400000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03400000 0x0 0x80000
0x00 0x034c0000 0x0 0x40000
0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
pcie@3500000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
@ -274,6 +285,17 @@
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep@3500000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03500000 0x0 0x80000
0x00 0x035c0000 0x0 0x40000
0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
pcie@3600000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
@ -290,6 +312,17 @@
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
pcie_ep@3600000 {
compatible = "fsl,ls-pcie-ep";
reg = <0x00 0x03600000 0x0 0x80000
0x00 0x036c0000 0x0 0x40000
0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "ctrl", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
big-endian;
};
sata: sata@3200000 {
compatible = "fsl,ls1046a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */

99
arch/arm/dts/fsl-lx2160a-qds.dtsi
View File

@ -20,6 +20,105 @@
phy-connection-type = "rgmii-id";
};
&dspi0 {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi1 {
bus-num = <0>;
status = "okay";
dflash3: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash4: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash5: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&dspi2 {
bus-num = <0>;
status = "okay";
dflash6: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash7: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash8: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&emdio1 {
status = "okay";
};

19
arch/arm/dts/fsl-lx2160a.dtsi
View File

@ -204,6 +204,13 @@
#interrupt-cells = <2>;
};
watchdog@23a0000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x23a0000 0 0x1000>,
<0x0 0x2390000 0 0x1000>;
timeout-sec = <30>;
};
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
@ -284,7 +291,7 @@
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
0x00 0x03480000 0x0 0x40000 /* LUT registers */
0x00 0x034c0000 0x0 0x40000 /* PF control registers */
0x80 0x00000000 0x0 0x1000>; /* configuration space */
0x80 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@ -298,7 +305,7 @@
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
0x00 0x03580000 0x0 0x40000 /* LUT registers */
0x00 0x035c0000 0x0 0x40000 /* PF control registers */
0x88 0x00000000 0x0 0x1000>; /* configuration space */
0x88 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@ -313,7 +320,7 @@
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
0x00 0x03680000 0x0 0x40000 /* LUT registers */
0x00 0x036c0000 0x0 0x40000 /* PF control registers */
0x90 0x00000000 0x0 0x1000>; /* configuration space */
0x90 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@ -327,7 +334,7 @@
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
0x00 0x03780000 0x0 0x40000 /* LUT registers */
0x00 0x037c0000 0x0 0x40000 /* PF control registers */
0x98 0x00000000 0x0 0x1000>; /* configuration space */
0x98 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@ -341,7 +348,7 @@
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
0x00 0x03880000 0x0 0x40000 /* LUT registers */
0x00 0x038c0000 0x0 0x40000 /* PF control registers */
0xa0 0x00000000 0x0 0x1000>; /* configuration space */
0xa0 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
@ -355,7 +362,7 @@
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
0x00 0x03980000 0x0 0x40000 /* LUT registers */
0x00 0x039c0000 0x0 0x40000 /* PF control registers */
0xa8 0x00000000 0x0 0x1000>; /* configuration space */
0xa8 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;

22
arch/arm/include/asm/arch-fsl-layerscape/gpio.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 NXP
*/
/*
* Dummy header file to enable CONFIG_OF_CONTROL.
* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
* OF_CONTROL must have arch/gpio.h.
*/
#ifndef __ASM_ARCH_MX85XX_GPIO_H
#define __ASM_ARCH_MX85XX_GPIO_H
struct mpc8xxx_gpio_plat {
ulong addr;
ulong size;
uint ngpios;
};
#endif

8
arch/arm/include/asm/arch-fsl-layerscape/mp.h
View File

@ -32,18 +32,16 @@
#define id_to_core(x) ((x & 3) | (x >> 6))
#ifndef __ASSEMBLY__
extern u64 __spin_table[];
extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
extern void *secondary_boot_addr;
extern void *secondary_boot_code_start;
extern size_t secondary_boot_code_size;
#ifdef CONFIG_MP
int fsl_layerscape_wake_seconday_cores(void);
#else
static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
#endif
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
u32 cpu_pos_mask(void);
#endif

8
arch/arm/include/asm/gpio.h
View File

@ -1,12 +1,8 @@
#if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
!defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM68360) && \
!defined(CONFIG_ARCH_BCM6858) && !defined(CONFIG_ARCH_BCM63158) && \
!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_LX2160A) && \
!defined(CONFIG_ARCH_LS1028A) && !defined(CONFIG_ARCH_LS2080A) && \
!defined(CONFIG_ARCH_LS1088A) && !defined(CONFIG_ARCH_ASPEED) && \
!defined(CONFIG_ARCH_LS1012A) && !defined(CONFIG_ARCH_LS1043A) && \
!defined(CONFIG_ARCH_LS1046A) && !defined(CONFIG_ARCH_U8500) && \
!defined(CONFIG_CORTINA_PLATFORM)
!defined(CONFIG_ARCH_ROCKCHIP) && !defined(CONFIG_ARCH_ASPEED) && \
!defined(CONFIG_ARCH_U8500) && !defined(CONFIG_CORTINA_PLATFORM)
#include <asm/arch/gpio.h>
#endif
#include <asm-generic/gpio.h>

4
arch/powerpc/include/asm/global_data.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2002-2010
* Copyright 2020 NXP
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
@ -15,9 +16,6 @@ struct arch_global_data {
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
u32 sdhc_per_clk;
#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
u8 sdhc_adapter;
#endif
#endif
#if defined(CONFIG_MPC8xx)
unsigned long brg_clk;

13
board/freescale/common/qixis.c
View File

@ -323,6 +323,19 @@ static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
} else if (strcmp(argv[1], "xspi") == 0) {
#ifdef QIXIS_LBMAP_XSPI
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
set_lbmap(QIXIS_LBMAP_XSPI);
set_rcw_src(QIXIS_RCW_SRC_XSPI);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_IDLE);
qixis_write_i2c(offsetof(struct qixis, rcfg_ctl),
QIXIS_RCFG_CTL_RECONFIG_START);
#else
printf("Not implemented\n");
#endif
} else if (strcmp(argv[1], "watchdog") == 0) {
static char *period[9] = {"2s", "4s", "8s", "16s", "32s",

14
board/freescale/common/qixis.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011 Freescale Semiconductor
* Copyright 2020 NXP
* Author: Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* This file provides support for the QIXIS of some Freescale reference boards.
@ -35,7 +36,12 @@ struct qixis {
u8 gdc;
u8 gdd; /* DCM Debug Data Register,0x17 */
u8 dmack;
u8 res1[6];
u8 res1;
u8 sdhc1;
u8 sdhc2;
u8 stat_pres3;
u8 los_stat;
u8 usb_ctl;
u8 watch; /* Watchdog Register,0x1F */
u8 pwr_ctl[2]; /* Power Control Register,0x20 */
u8 res2[2];
@ -115,8 +121,8 @@ void qixis_write_i2c(unsigned int reg, u8 value);
#endif
/* Use for SDHC adapter card type identification and operation */
#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
@ -125,12 +131,14 @@ void qixis_write_i2c(unsigned int reg, u8 value);
#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
#define QIXIS_SDHC1_S1V3 0x80 /* SDHC1: SDHC1 3.3V power control */
#define QIXIS_SDHC1_VS 0x30 /* BRDCFG11: route to SDHC1_VS */
#define QIXIS_SDCLKIN 0x08
#define QIXIS_SDCLKOUT 0x02
#define QIXIS_DAT5_6_7 0X02
#define QIXIS_DAT4 0X01
#define QIXIS_EVDD_BY_SDHC_VS 0x0c
#endif
#endif

2
board/freescale/ls1012ardb/eth.c
View File

@ -113,7 +113,7 @@ int pfe_eth_board_init(struct udevice *dev)
/* MAC2 */
pfe_set_phy_address_mode(priv->gemac_port,
CONFIG_PFE_EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_RGMII_TXID);
PHY_INTERFACE_MODE_RGMII_ID);
}
break;
case 0x2208:

14
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
#include <common.h>
@ -50,6 +50,10 @@ enum {
#define CFG_UART_MUX_SHIFT 1
#define CFG_LPUART_EN 0x1
#ifdef CONFIG_SYS_I2C_EARLY_INIT
void i2c_early_init_f(void);
#endif
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
@ -453,6 +457,7 @@ void board_retimer_init(void)
int board_early_init_f(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
@ -461,10 +466,13 @@ int board_early_init_f(void)
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C
/*
* Enable secure system counter for timer
*/
out_le32(cntcr, 0x1);
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#endif
fsl_lsch2_early_init_f();

5
board/freescale/ls1046afrwy/MAINTAINERS
View File

@ -5,3 +5,8 @@ F: board/freescale/ls1046afrwy/
F: board/freescale/ls1046afrwy/ls1046afrwy.c
F: include/configs/ls1046afrwy.h
F: configs/ls1046afrwy_tfa_defconfig
LS1046AFRWY_SECURE_BOOT BOARD
M: Manish Tomar <manish.tomar@nxp.com>
S: Maintained
F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig

14
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
#include <common.h>
@ -35,6 +35,10 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SYS_I2C_EARLY_INIT
void i2c_early_init_f(void);
#endif
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
{
@ -323,6 +327,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int board_early_init_f(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
@ -331,10 +336,13 @@ int board_early_init_f(void)
u8 uart;
#endif
#ifdef CONFIG_SYS_I2C
/*
* Enable secure system counter for timer
*/
out_le32(cntcr, 0x1);
#ifdef CONFIG_SYS_I2C_EARLY_INIT
i2c_early_init_f();
#endif
#endif
fsl_lsch2_early_init_f();

36
board/freescale/lx2160a/lx2160a.c
View File

@ -18,6 +18,7 @@
#include <fdt_support.h>
#include <linux/bitops.h>
#include <linux/libfdt.h>
#include <linux/delay.h>
#include <fsl-mc/fsl_mc.h>
#include <env_internal.h>
#include <efi_loader.h>
@ -379,7 +380,7 @@ int checkboard(void)
*/
u8 qixis_esdhc_detect_quirk(void)
{
/* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
/*
* SDHC1 Card ID:
* Specifies the type of card installed in the SDHC1 adapter slot.
* 000= (reserved)
@ -391,10 +392,35 @@ u8 qixis_esdhc_detect_quirk(void)
* 110= SDCard V2/V3 adapter installed.
* 111= no adapter is installed.
*/
return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
return ((QIXIS_READ(sdhc1) & QIXIS_SDID_MASK) !=
QIXIS_ESDHC_NO_ADAPTER);
}
static void esdhc_adapter_card_ident(void)
{
u8 card_id, val;
val = QIXIS_READ(sdhc1);
card_id = val & QIXIS_SDID_MASK;
switch (card_id) {
case QIXIS_ESDHC_ADAPTER_TYPE_SD:
/* Power cycle to card */
val &= ~QIXIS_SDHC1_S1V3;
QIXIS_WRITE(sdhc1, val);
mdelay(1);
val |= QIXIS_SDHC1_S1V3;
QIXIS_WRITE(sdhc1, val);
/* Route to SDHC1_VS */
val = QIXIS_READ(brdcfg[11]);
val |= QIXIS_SDHC1_VS;
QIXIS_WRITE(brdcfg[11], val);
break;
default:
break;
}
}
int config_board_mux(void)
{
u8 reg11, reg5, reg13;
@ -501,6 +527,12 @@ int config_board_mux(void)
return 0;
}
int board_early_init_r(void)
{
esdhc_adapter_card_ident();
return 0;
}
#elif defined(CONFIG_TARGET_LX2160ARDB)
int config_board_mux(void)
{

29
board/freescale/t208xqds/t208xqds.c
View File

@ -345,6 +345,33 @@ int brd_mux_lane_to_slot(void)
return 0;
}
static void esdhc_adapter_card_ident(void)
{
u8 card_id, value;
card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
switch (card_id) {
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
value = QIXIS_READ(brdcfg[5]);
value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
QIXIS_WRITE(brdcfg[5], value);
break;
case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
value = QIXIS_READ(pwr_ctl[1]);
value |= QIXIS_EVDD_BY_SDHC_VS;
QIXIS_WRITE(pwr_ctl[1], value);
break;
case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
value = QIXIS_READ(brdcfg[5]);
value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
QIXIS_WRITE(brdcfg[5], value);
break;
default:
break;
}
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@ -384,7 +411,7 @@ int board_early_init_r(void)
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
esdhc_adapter_card_ident();
return 0;
}

12
common/board_r.c
View File

@ -233,6 +233,15 @@ static int initr_unlock_ram_in_cache(void)
}
#endif
#ifdef CONFIG_PCI_ENDPOINT
static int initr_pci_ep(void)
{
pci_ep_init();
return 0;
}
#endif
#ifdef CONFIG_PCI
static int initr_pci(void)
{
@ -816,6 +825,9 @@ static init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_BITBANGMII
initr_bbmii,
#endif
#ifdef CONFIG_PCI_ENDPOINT
initr_pci_ep,
#endif
#ifdef CONFIG_CMD_NET
INIT_FUNC_WATCHDOG_RESET
initr_net,

2
configs/ls1012afrdm_qspi_defconfig
View File

@ -50,7 +50,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1012afrdm_tfa_defconfig
View File

@ -50,7 +50,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
View File

@ -48,7 +48,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012afrwy_qspi_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
View File

@ -48,7 +48,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012afrwy_tfa_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012aqds_qspi_defconfig
View File

@ -69,7 +69,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

2
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
View File

@ -58,7 +58,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

2
configs/ls1012aqds_tfa_defconfig
View File

@ -69,7 +69,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

2
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View File

@ -51,7 +51,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012ardb_qspi_defconfig
View File

@ -55,7 +55,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1012ardb_tfa_defconfig
View File

@ -54,7 +54,7 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1021aiot_qspi_defconfig
View File

@ -46,7 +46,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1021aiot_sdcard_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1021aqds_ddr4_nor_defconfig
View File

@ -59,7 +59,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y

2
configs/ls1021aqds_ddr4_nor_lpuart_defconfig
View File

@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y

2
configs/ls1021aqds_nand_defconfig
View File

@ -76,7 +76,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y

2
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -58,7 +58,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y

2
configs/ls1021aqds_nor_defconfig
View File

@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y

2
configs/ls1021aqds_nor_lpuart_defconfig
View File

@ -61,7 +61,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y

2
configs/ls1021aqds_qspi_defconfig
View File

@ -59,7 +59,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1021aqds_sdcard_ifc_defconfig
View File

@ -75,7 +75,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y

2
configs/ls1021aqds_sdcard_qspi_defconfig
View File

@ -71,7 +71,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1021atsn_qspi_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

2
configs/ls1021atsn_sdcard_defconfig
View File

@ -60,7 +60,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

2
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y

2
configs/ls1021atwr_nor_defconfig
View File

@ -54,7 +54,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y

2
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -56,7 +56,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y

2
configs/ls1021atwr_qspi_defconfig
View File

@ -57,7 +57,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -67,7 +67,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_DM_USB=y

2
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -69,7 +69,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_USB=y

2
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -68,7 +68,7 @@ CONFIG_TSEC_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -64,7 +64,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y

2
configs/ls1028aqds_tfa_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y

2
configs/ls1028aqds_tfa_lpuart_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y

2
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View File

@ -61,7 +61,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y

2
configs/ls1028ardb_tfa_defconfig
View File

@ -67,7 +67,7 @@ CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_RTC=y
CONFIG_RTC_PCF2127=y
CONFIG_SCSI=y

2
configs/ls1043aqds_defconfig
View File

@ -58,7 +58,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_lpuart_defconfig
View File

@ -59,7 +59,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y

2
configs/ls1043aqds_nand_defconfig
View File

@ -74,7 +74,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_nor_ddr3_defconfig
View File

@ -59,7 +59,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_qspi_defconfig
View File

@ -54,7 +54,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_sdcard_ifc_defconfig
View File

@ -75,7 +75,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_sdcard_qspi_defconfig
View File

@ -68,7 +68,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

2
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
View File

@ -58,7 +58,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043aqds_tfa_defconfig
View File

@ -68,7 +68,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_SECURE_BOOT_defconfig
View File

@ -49,7 +49,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_defconfig
View File

@ -52,7 +52,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
View File

@ -69,7 +69,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_nand_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -69,7 +69,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_sdcard_defconfig
View File

@ -70,7 +70,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
View File

@ -51,7 +51,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

2
configs/ls1043ardb_tfa_defconfig
View File

@ -57,7 +57,7 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y

68
configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,68 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_ENV_OFFSET=0x500000
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_MISC_INIT_R=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_MP=y
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
CONFIG_ENV_ADDR=0x40500000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_SECURE_BOOT=y
CONFIG_RSA=y
CONFIG_ENV_IS_NOWHERE=y
CONFIG_CMD_SETEXPR=y

3
configs/ls1046afrwy_tfa_defconfig
View File

@ -51,7 +51,8 @@ CONFIG_E1000=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

3
configs/ls1046aqds_SECURE_BOOT_defconfig
View File

@ -54,7 +54,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_defconfig
View File

@ -57,7 +57,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_lpuart_defconfig
View File

@ -58,7 +58,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_SCSI=y
CONFIG_DM_SERIAL=y

3
configs/ls1046aqds_nand_defconfig
View File

@ -65,7 +65,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_qspi_defconfig
View File

@ -54,7 +54,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_sdcard_ifc_defconfig
View File

@ -75,7 +75,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_sdcard_qspi_defconfig
View File

@ -69,7 +69,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
View File

@ -57,7 +57,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

3
configs/ls1046aqds_tfa_defconfig
View File

@ -67,7 +67,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

3
configs/ls1046ardb_emmc_defconfig
View File

@ -67,7 +67,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
View File

@ -49,7 +49,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046ardb_qspi_defconfig
View File

@ -53,7 +53,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046ardb_qspi_spl_defconfig
View File

@ -70,7 +70,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -63,7 +63,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

3
configs/ls1046ardb_sdcard_defconfig
View File

@ -66,7 +66,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y

3
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
View File

@ -49,7 +49,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

3
configs/ls1046ardb_tfa_defconfig
View File

@ -55,7 +55,8 @@ CONFIG_FMAN_ENET=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_PCIE_LAYERSCAPE_EP=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

2
configs/ls1088aqds_defconfig
View File

@ -59,7 +59,7 @@ CONFIG_MII=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PCIE_LAYERSCAPE_RC=y
CONFIG_DM_SCSI=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y

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