Commit Graph

17278 Commits

Author SHA1 Message Date
Kever Yang
c525bb42aa ram: rockchip: add common msch reg definition
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
691368c7f7 ram: rockchip: add phy driver code for PX30
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
09d7872336 ram: rockchip: add controller code for PX30
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
d6647b08b2 ram: rockchip: add common code for sdram driver
There are some function like os_reg setting, capacity detect functions,
can be used as common code for different Rockchip SoCs, add a
sdram_common.c for all these functions.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
c7becc3a2b rockchip: sdram: update the sys_reg to sys_reg2
We are using sys_reg2 and sys_reg3 as ddr cap info, sync the variable
name to what we real use to avoid confuse people.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
9a46f2a4cb rockchip: sdram: extend to use sys_reg3 for capacity info
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
d5d40f45de rockchip: sdram: move cap structure and debug function to sdram_common.h
The sdram.h suppose to be helper file for sdram.c which including dram
size decode and some u-boot related dram init interface, and all
structure and function for dram driver move to sdram_common.h

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
5d19ddf0db ram: rockchip: rename sdram_common.c/h to sdram.c
rename sdram_common.c in arch/arm/mach-rockchip to sdram.c;
so that we can use the file name sdram_common.c in dram driver for
better understand the code;
clean the related file who has use the header file at the same time.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Kever Yang
2a2f0b177c ram: rockchip: rename sdram.h to sdram_rk3288.h
The header file sdram.h is used for rk3288 and similar SoCs, rename it
to make it more understandable.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-17 16:23:56 +08:00
Tom Rini
5f7ff6d63e u-boot-imx-20191105
-------------------
 i.MX8MN SoC support
 ROM API image download support
 i.MX8MM enet enabling
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Merge tag 'u-boot-imx-20191105' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191105
-------------------
i.MX8MN SoC support
ROM API image download support
i.MX8MM enet enabling
2019-11-12 07:18:23 -05:00
Tom Rini
086e391bc4 Merge tag 'u-boot-rockchip-20191110' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip pmic rk805,rk809, rk816, rk817
- Add rk3399 board Leez support
- Fix bug in rk3328 ram driver
- Adapt SPL to support ATF bl31 with entry at 0x40000
- Fix the u8 type comparision with '-1'.
- Fix checkpatch warning for multi blank line and review signature.
2019-11-11 14:19:32 -05:00
Tom Rini
0b73ef0c02 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
2019-11-11 14:19:04 -05:00
Kever Yang
f74a089e47 rockchip: firefly-rk3288: Enable TPL support
This patch enable TPL support for firefly-rk3288 board, which works ths
same way with other RK3288 board like Tinker, evb.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Levin Du
2d86ab50ce rockchip: adding the missing "/" in entries of boot_devices
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:

   node = fdt_path_offset(blob, conf);

which will failed without the "/" indicating the path.

Currently only entries of boot_devices in rk3399 have the "/" prefix.
Therefore add the missing ones in other boards.

Signed-off-by: Levin Du <djw@t-chip.com.cn>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Kever Yang
006ab58d46 rockchip: rk3399: update SPL_STACK_R_ADDR
Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.

After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Heiko Stuebner
f848d2b2c8 rockchip: make_fit_atf.py: allow inclusion of a tee binary
A trusted execution environment should also get loaded as loadable from
a fit image, so add the possibility to present a tee.elf to make_fit_atf.py
that then gets included as additional loadable into the generated its.

For ease of integration the additional loadable is created as atf_(x+1)
after all others to re-use core generation loops.

Tested against the combinations of 1-part-atf and multi-part-atf each
time with and without a tee binary present.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Emmanuel Vadot
b5500b2057 rockchip: dts: rk3328: rock64: Add same-as-spl order
rk3328 can use same-as-spl option so next loaders are loaded from the same
medium.
Add the boot order in the rock64 dts otherwise booting from sdcard
will result in u-boot looking into the eMMC.

Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Simon South
2cbdb6e051 clk: rockchip: rk3328: Configure CPU clock
Add a call to rk3328_configure_cpu() during initialization to set the
CPU-clock frequency.

Signed-off-by: Simon South <simon@simonsouth.net>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Andy Yan
a4bbc662fc rockchip: rk3399: Add Leez P710 support
Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply

Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1: 	fc702ed49a8668a17343811ee28214d845bfc5e6)

Signed-off-by: Andy Yan <andyshrk@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-11-10 20:40:20 +08:00
Tom Rini
ee1c499851 Merge branch '2019-11-07-master-imports'
- Add Phytium Durian Board
- Assorted bugfixes
- Allow for  make ERR_PTR/PTR_ERR architecture specific
2019-11-08 07:27:45 -05:00
Udit Agarwal
bef1845404 freescale/powerpc: Rename the config CONFIG_SECURE_BOOT name
Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Udit Agarwal
5536c3c9d0 freescale/layerscape: Rename the config CONFIG_SECURE_BOOT name
Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 16:32:08 +05:30
Pankaj Bansal
812ff53c3e fsl-layerscape: fix warning if no hwconfig is defined
While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
	before environment is ready

Fix this by checking 'hwconfig' env variable.
If not found return without further processing.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
2019-11-08 15:50:12 +05:30
Michael Walle
762ee522e2 armv8: fsl-layerscape: introduce fsl_board_late_init()
The fsl-layerscape already occupies board_late_init(), therefore it is
not possible for a board to have its own board_late_init(). Introduce
fsl_board_late_init() which can be implemented in the board specific
code.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:39 +05:30
Michael Walle
065ee175e0 armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x
The clocks are not dependent on the target but only on the SoC.
Therefore, convert the CONFIG_TARGET_x macros to the corresponding
CONFIG_ARCH_x. This will allow other targets to automatically use the
common code. Otherwise every new target would have to add itself to the
"#if defined(CONFIG_TARGET_x) || .." macros.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:39 +05:30
Laurentiu Tudor
b4a59115e2 armv8: ls1028a: add erratum A-050382 workaround
Erratum A-050382 states that the eDMA ICID programmed in the eDMA_AMQR
register in DCFG is not correctly forwarded to the SMMU.
The workaround consists in programming the eDMA ICID in the eDMA_AMQR
register in DCFG to 40.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
30449aea50 armv8: lx2160a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
ab04dee542 fsl-layerscape: add missing SATA3 and SATA4 base addresses
LX2160A chips have 4 sata controllers. Add missing base addresses for
SATA3 and SATA4.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
e33938acc9 armv8: ls2088a: add icid setup for platform devices
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
5047781e99 fsl-layerscape: fix compile error with sec fw disabled
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n), below
compilation error appears
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)

Fix it by wrapping with CONFIG_IS_ENABLED().

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Laurentiu Tudor
db49c1b2de armv8: fsl-layerscape: guard caam specific defines
These macros should only be used when CONFIG_FSL_CAAM is present.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Mathew McBride
28f9393b1a fsl-layerscape: do not use layerscape EFI reset if PSCI used
If the secure world reset handlers are used (via CONFIG_PSCI_RESET),
then do not use the layerscape-specific implementation.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Mathew McBride
b50fe3fb7e armv8: dts: ls1088a: add PSCI binding for LS1088A
This allows the use of PSCI calls to trusted firmware to
initiate reset and poweroff events with CONFIG_PSCI_RESET and
CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target
board has implemented a custom reset or poweroff procedure in EL3.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-08 11:13:38 +05:30
Adam Ford
899836c315 ARM: dts: logicpd-som-lv-37xx-devkit-u-boot: Remove unused GPIO
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight.

This patch removes the all but GPIO4 from the spl device tree to
reduce the SPL footprint.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07 18:39:18 -05:00
Adam Ford
1e3d015a03 ARM: dts: logicpd-torpedo-37xx-devkit-u-boot: Remove unused GPIO
The only GPIO bank needed in SPL is GPIO4 and the SPL space is tight.

This patch removes the all but GPIO4 from the spl device tree to
reduce the SPL footprint.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-11-07 18:39:18 -05:00
Keerthy
2f71498d52 arm: dts: k3-j721e-r5-common-proc-board: Hook buck12_reg to vtm supply
Hook buck12_reg to vtm avs supply

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
0f63ceaf54 arm: dts: k3-j721e-r5-common: Add tps65941 node and dependent wkup_i2c0 node
Add tps65941 node and dependent wkup_i2c0 node needed for AVS class 0 support

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
69eceae870 arm: dts: k3-j721e-r5-common-proc-board: Add VTM node
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Tero Kristo
56adc6615f arm: dts: k3-am654-r5-base-board: enable wkup_vtm0 node and link in supplies
Link the vdd-supplies for the voltage domains under the VTM node. Also,
enable the node under SPL. This will enable the AVS class 0 support on
am65x-evm board.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Tero Kristo
c5f73d1c9f arm: dts: k3-am654-r5-base-board: add supply rail for MPU
MPU voltage on AM65x-evm is controlled via the TPS62363 chip attached
to i2c0 bus. Add device node for this so that it can be controlled via
a regulator driver.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Tero Kristo
4bbb3849aa arm: dts: k3-am654-r5-base-board: enable wkup_i2c0 driver for spl
Enable wkup_i2c0 as this is needed for voltage control.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
cfa6bd549c arm: dts: k3-am654-r5-base-board: Add VTM node
Add VTM node for voltage and thermal management. For u-boot, this is needed
for supporting AVS class 0, as the efuse values for the OPPs are stored
under the VTM.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
7b13493088 arm: mach-k3: j721e_init: Initialize avs class 0
Initialize avs class 0

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
27380cb7e9 arm: mach-k3: am6_init: Initialize AVS class 0
Initialize AVS class 0 so that mpu voltage rail is
programmed to the AVS class 0 compensated value.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
liu hao
e3aafef4cf arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07 18:01:13 -05:00
Lokesh Vutla
7a540eeecc arm: caches: Disable mmu only if mmu is available
As part of disabling caches MMU as well gets disabled. But MMU is not
available on all armv7 cores like R5F. So disable MMU only if it is
available.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07 18:01:13 -05:00
Simon Goldschmidt
a43b60cc78 arm: socfpga: gen5: fix ERR_PTR_OFFSET
The default implementation of ERR_PTR/PTR_ERR maps errno values at the
and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA).

For socfpga gen5 SPL, this doesn't really work, as the heap is nearly
at the end of the 32 bit address range.

This patch adjusts the ERR_PTR_OFFSET to map errno values into the range
of the Boot ROM, which should not be used for valid pointers.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-07 18:01:13 -05:00
Vignesh Raghavendra
37e66ba916 arm64: Add memcpy_{from, to}io() and memset_io() helpers
Provide optimized memcpy_{from,to}io() and memset_io(). This is required
when moving large amount of data to and from IO regions such as IP
registers or accessing memory mapped flashes.

Code is borrowed from Linux Kernel v5.4.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-11-07 18:01:12 -05:00
Heiko Schocher
81a7abe593 mpc85xx, dts, socrates: add u-boot specific dtsi
add u-boot specific dtsi file for socrates board.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30
Heiko Schocher
7d8c77e844 mpc85xx: add socrates dts from linux
add socrates device tree from linux:

commit 71ae5fc87c34 ("Merge tag 'linux-kselftest-5.2-rc1' of
git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest")

and added SPDX license identifier.
Did not fix checkpatch warnings:
arch/powerpc/dts/socrates.dts:235: check: Please don't use multiple blank lines
arch/powerpc/dts/socrates.dts:238: error: code indent should use tabs where possible

Also, add me as board maintainer.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30