arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board. The initial support comprises the UART and the PCIE. Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
This commit is contained in:
liu hao
Tom Rini
parent
672c57057f
commit
e3aafef4cf
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@ -481,6 +481,13 @@ S: Maintained
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T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git
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F: arch/arm/mach-zynqmp-r5/
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ARM PHYTIUM
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M: liuhao <liuhao@phytium.com.cn>
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M: shuyiqi <shuyiqi@phytium.com.cn>
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S: Maintained
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F: drivers/pci/pcie_phytium.c
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F: arch/arm/dts/phytium-durian.dts
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BINMAN
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M: Simon Glass <sjg@chromium.org>
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S: Maintained
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@ -1631,6 +1631,13 @@ config ARCH_ASPEED
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select OF_CONTROL
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imply CMD_DM
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config TARGET_DURIAN
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bool "Support Phytium Durian Platform"
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select ARM64
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help
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Support for durian platform.
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It has 2GB Sdram, uart and pcie.
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endchoice
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config ARCH_SUPPORT_TFABOOT
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@ -1830,6 +1837,7 @@ source "board/woodburn/Kconfig"
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source "board/xilinx/Kconfig"
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source "board/xilinx/zynq/Kconfig"
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source "board/xilinx/zynqmp/Kconfig"
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source "board/phytium/durian/Kconfig"
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source "arch/arm/Kconfig.debug"
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@ -834,6 +834,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb
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dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
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dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
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targets += $(dtb-y)
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# Add any required device tree compiler flags here
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@ -0,0 +1,33 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Phytium Ltd.
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* shuyiqi <shuyiqi@phytium.com.cn>
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*/
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/dts-v1/;
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/ {
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model = "Phytium Durian";
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compatible = "phytium,durian";
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-controller@40000000 {
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compatible = "phytium,pcie-host-1.0";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x40000000 0x0 0x10000000>;
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bus-range = <0x0 0xff>;
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ranges = <0x1000000 0x0 0x0 0x0 0x50000000 0x0 0xF00000>,
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<0x2000000 0x0 0x58000000 0x0 0x58000000 0x0 0x28000000>,
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<0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
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};
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uart@28001000 {
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compatible = "arm,pl011";
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reg = <0x0 0x28001000 0x0 0x1000>;
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clock = <48000000>;
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};
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};
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@ -0,0 +1,12 @@
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if TARGET_DURIAN
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config SYS_BOARD
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default "durian"
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config SYS_VENDOR
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default "phytium"
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config SYS_CONFIG_NAME
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default "durian"
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endif
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@ -0,0 +1,8 @@
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DURIAN BOARD
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M: liuhao <liuhao@phytium.com.cn>
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M: shuyiqi <shuyiqi@phytium.com.cn>
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S: Maintained
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F: board/phytium/durian/*
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F: include/configs/durian.h
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F: configs/durian_defconfig
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2019
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# shuyiqi <shuyiqi@phytium.com.cn>
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# liuhao <liuhao@phytium.com.cn>
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#
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obj-y += durian.o
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@ -0,0 +1,59 @@
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Here is the step-by-step to boot U-Boot on phytium durian board.
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Compile U-Boot
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==============
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> make durian_defconfig
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> make
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Get the prebuild binary about BPF
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=================================
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> cd ../
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> git clone https://github.com/phytium-durian/bpf.git
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Package the image
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=================
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> cd bpf
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> cp ../u-boot/u-boot.bin ./
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> ./dopack
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The fip-all.bin is the final image.
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Flash the image into the spi nor-flash
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======================================
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Any spi nor-flash and appropriate tool can be used to flash.
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For example, we choose the S25FL256 chip that produced from
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SPANSION company and EZP_XPro V1.2.
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Reset the board, you can get U-Boot log message from boot console:
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Power on...
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Start pcie setup!
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End pcie setup!
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Start ddr setup!
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End ddr setup!
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Jump to entrypoint: 0x500000
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U-Boot 2019.10-00594-g9ccc1b17ea-dirty (Oct 18 2019 - 00:17:09 +0800)
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DRAM: 1.9 GiB
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In: uart@28001000
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Out: uart@28001000
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Err: uart@28001000
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scanning bus for devices...
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Target spinup took 0 ms.
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SATA link 1 timeout.
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SATA link 2 timeout.
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SATA link 3 timeout.
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AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
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flags: 64bit ncq led only pmp fbss pio slum part sxs
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Device 0: (0:0) Vendor: ATA Prod.: ST1000DM010-2EP1 Rev: CC43
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Type: Hard Disk
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Capacity: 953869.7 MB = 931.5 GB (1953525168 x 512)
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SATA link 0 timeout.
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SATA link 1 timeout.
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SATA link 2 timeout.
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SATA link 3 timeout.
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AHCI 0001.0000 32 slots 4 ports 6 Gbps 0xf impl SATA mode
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flags: 64bit ncq led only pmp fbss pio slum part sxs
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Hit any key to stop autoboot: 0
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durian#
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@ -0,0 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019
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* Phytium Technology Ltd <www.phytium.com>
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* shuyiqi <shuyiqi@phytium.com.cn>
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*/
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#ifndef _FT_DURIAN_H
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#define _FT_DURIAN_H
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/* FLUSH L3 CASHE */
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#define HNF_COUNT 0x8
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#define HNF_PSTATE_REQ (HNF_BASE + 0x10)
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#define HNF_PSTATE_STAT (HNF_BASE + 0x18)
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#define HNF_PSTATE_OFF 0x0
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#define HNF_PSTATE_SFONLY 0x1
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#define HNF_PSTATE_HALF 0x2
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#define HNF_PSTATE_FULL 0x3
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#define HNF_STRIDE 0x10000
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#define HNF_BASE (unsigned long)(0x3A200000)
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#endif /* _FT_DURIAN_H */
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@ -0,0 +1,110 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019
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* shuyiqi <shuyiqi@phytium.com.cn>
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* liuhao <liuhao@phytium.com.cn>
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <linux/arm-smccc.h>
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#include <linux/kernel.h>
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#include <scsi.h>
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#include "cpu.h"
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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gd->mem_clk = 0;
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
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debug("reset cpu error, %lx\n", res.a0);
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}
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static struct mm_region durian_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN |
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PTE_BLOCK_UXN
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},
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{
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.virt = (u64)PHYS_SDRAM_1,
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.phys = (u64)PHYS_SDRAM_1,
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.size = (u64)PHYS_SDRAM_1_SIZE,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_NS |
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PTE_BLOCK_INNER_SHARE
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = durian_mem_map;
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int print_cpuinfo(void)
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{
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printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk);
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return 0;
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}
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int __asm_flush_l3_dcache(void)
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{
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int i, pstate;
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
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for (i = 0; i < HNF_COUNT; i++) {
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do {
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pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
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} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
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}
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for (i = 0; i < HNF_COUNT; i++)
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writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
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return 0;
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}
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int last_stage_init(void)
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{
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int ret;
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/* pci e */
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pci_init();
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/* scsi scan */
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ret = scsi_scan(true);
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if (ret) {
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printf("scsi scan failed\n");
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return CMD_RET_FAILURE;
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}
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return ret;
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}
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@ -0,0 +1,33 @@
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CONFIG_ARM=y
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CONFIG_ARM_SMCCC=y
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CONFIG_TARGET_DURIAN=y
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CONFIG_SYS_TEXT_BASE=0x500000
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CONFIG_NR_DRAM_BANKS=1
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# CONFIG_PSCI_RESET is not set
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CONFIG_AHCI=y
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw"
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# CONFIG_DISPLAY_CPUINFO is not set
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_SYS_PROMPT="durian#"
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# CONFIG_CMD_LZMADEC is not set
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# CONFIG_CMD_UNZIP is not set
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CONFIG_CMD_PCI=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="phytium-durian"
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# CONFIG_NET is not set
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CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_AHCI_PCI=y
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CONFIG_BLK=y
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# CONFIG_MMC is not set
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCI_PHYTIUM=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_DM_SERIAL=y
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CONFIG_PL01X_SERIAL=y
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@ -51,6 +51,13 @@ config PCIE_ECAM_GENERIC
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Say Y here if you want to enable support for generic ECAM-based
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PCIe host controllers, such as the one emulated by QEMU.
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config PCI_PHYTIUM
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bool "Phytium PCIe support"
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depends on DM_PCI
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help
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Say Y here if you want to enable PCIe controller support on
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Phytium SoCs.
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config PCIE_DW_MVEBU
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bool "Enable Armada-8K PCIe driver (DesignWare core)"
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depends on DM_PCI
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@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
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obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
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pcie_layerscape_gen4_fixup.o
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obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
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obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
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obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
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obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
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@ -0,0 +1,200 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Phytium PCIE host driver
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*
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* Heavily based on drivers/pci/pcie_xilinx.c
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*
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* Copyright (C) 2019
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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/**
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* struct phytium_pcie - phytium PCIe controller state
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* @cfg_base: The base address of memory mapped configuration space
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*/
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struct phytium_pcie {
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void *cfg_base;
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};
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/*
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* phytium_pci_skip_dev()
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* @parent: Identifies the PCIe device to access
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*
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* Checks whether the parent of the PCIe device is bridge
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*
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* Return: true if it is bridge, else false.
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*/
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static int phytium_pci_skip_dev(pci_dev_t parent)
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{
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unsigned char pos, id;
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unsigned long addr = 0x40000000;
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unsigned short capreg;
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unsigned char port_type;
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addr += PCI_BUS(parent) << 20;
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addr += PCI_DEV(parent) << 15;
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addr += PCI_FUNC(parent) << 12;
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pos = 0x34;
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while (1) {
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pos = readb(addr + pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = readb(addr + pos);
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if (id == 0xff)
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break;
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if (id == 0x10) {
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capreg = readw(addr + pos + 2);
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port_type = (capreg >> 4) & 0xf;
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if (port_type == 0x6 || port_type == 0x4)
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return 1;
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else
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return 0;
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}
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pos += 1;
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}
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return 0;
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}
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/**
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* pci_phytium_conf_address() - Calculate the address of a config access
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @paddress: Pointer to the pointer to write the calculates address to
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*
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* Calculates the address that should be accessed to perform a PCIe
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* configuration space access for a given device identified by the PCIe
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* controller device @pcie and the bus, device & function numbers in @bdf. If
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* access to the device is not valid then the function will return an error
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* code. Otherwise the address to access will be written to the pointer pointed
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* to by @paddress.
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*/
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static int pci_phytium_conf_address(struct udevice *bus, pci_dev_t bdf,
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uint offset,
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void **paddress)
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{
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struct phytium_pcie *pcie = dev_get_priv(bus);
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void *addr;
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pci_dev_t bdf_parent;
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unsigned int bus_no = PCI_BUS(bdf);
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unsigned int dev_no = PCI_DEV(bdf);
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bdf_parent = PCI_BDF((bus_no - 1), 0, 0);
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addr = pcie->cfg_base;
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addr += PCI_BUS(bdf) << 20;
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addr += PCI_DEV(bdf) << 15;
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addr += PCI_FUNC(bdf) << 12;
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|
||||
if (bus_no > 0 && dev_no > 0) {
|
||||
if ((readb(addr + PCI_HEADER_TYPE) & 0x7f) !=
|
||||
PCI_HEADER_TYPE_BRIDGE)
|
||||
return -ENODEV;
|
||||
if (phytium_pci_skip_dev(bdf_parent))
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
addr += offset;
|
||||
*paddress = addr;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_phytium_read_config() - Read from configuration space
|
||||
* @bus: Pointer to the PCI bus
|
||||
* @bdf: Identifies the PCIe device to access
|
||||
* @offset: The offset into the device's configuration space
|
||||
* @valuep: A pointer at which to store the read value
|
||||
* @size: Indicates the size of access to perform
|
||||
*
|
||||
* Read a value of size @size from offset @offset within the configuration
|
||||
* space of the device identified by the bus, device & function numbers in @bdf
|
||||
* on the PCI bus @bus.
|
||||
*/
|
||||
static int pci_phytium_read_config(struct udevice *bus, pci_dev_t bdf,
|
||||
uint offset, ulong *valuep,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
return pci_generic_mmap_read_config(bus, pci_phytium_conf_address,
|
||||
bdf, offset, valuep, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_phytium_write_config() - Write to configuration space
|
||||
* @bus: Pointer to the PCI bus
|
||||
* @bdf: Identifies the PCIe device to access
|
||||
* @offset: The offset into the device's configuration space
|
||||
* @value: The value to write
|
||||
* @size: Indicates the size of access to perform
|
||||
*
|
||||
* Write the value @value of size @size from offset @offset within the
|
||||
* configuration space of the device identified by the bus, device & function
|
||||
* numbers in @bdf on the PCI bus @bus.
|
||||
*/
|
||||
static int pci_phytium_write_config(struct udevice *bus, pci_dev_t bdf,
|
||||
uint offset, ulong value,
|
||||
enum pci_size_t size)
|
||||
{
|
||||
return pci_generic_mmap_write_config(bus, pci_phytium_conf_address,
|
||||
bdf, offset, value, size);
|
||||
}
|
||||
|
||||
/**
|
||||
* pci_phytium_ofdata_to_platdata() - Translate from DT to device state
|
||||
* @dev: A pointer to the device being operated on
|
||||
*
|
||||
* Translate relevant data from the device tree pertaining to device @dev into
|
||||
* state that the driver will later make use of. This state is stored in the
|
||||
* device's private data structure.
|
||||
*
|
||||
* Return: 0 on success, else -EINVAL
|
||||
*/
|
||||
static int pci_phytium_ofdata_to_platdata(struct udevice *dev)
|
||||
{
|
||||
struct phytium_pcie *pcie = dev_get_priv(dev);
|
||||
struct fdt_resource reg_res;
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int err;
|
||||
|
||||
err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
|
||||
0, ®_res);
|
||||
if (err < 0) {
|
||||
pr_err("\"reg\" resource not found\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
pcie->cfg_base = map_physmem(reg_res.start,
|
||||
fdt_resource_size(®_res),
|
||||
MAP_NOCACHE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_pci_ops pci_phytium_ops = {
|
||||
.read_config = pci_phytium_read_config,
|
||||
.write_config = pci_phytium_write_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id pci_phytium_ids[] = {
|
||||
{ .compatible = "phytium,pcie-host-1.0" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(pci_phytium) = {
|
||||
.name = "pci_phytium",
|
||||
.id = UCLASS_PCI,
|
||||
.of_match = pci_phytium_ids,
|
||||
.ops = &pci_phytium_ops,
|
||||
.ofdata_to_platdata = pci_phytium_ofdata_to_platdata,
|
||||
.priv_auto_alloc_size = sizeof(struct phytium_pcie),
|
||||
};
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2019
|
||||
* shuyiqi <shuyiqi@phytium.com.cn>
|
||||
* liuhao <liuhao@phytium.com.cn>
|
||||
*/
|
||||
|
||||
#ifndef __DURIAN_CONFIG_H__
|
||||
#define __DURIAN_CONFIG_H__
|
||||
|
||||
/* Sdram Bank #1 Address */
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x7B000000
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000)
|
||||
|
||||
/* Size of Malloc Pool */
|
||||
#define CONFIG_ENV_SIZE 4096
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (0x88000000 - 0x100000)
|
||||
|
||||
/* PCI CONFIG */
|
||||
#define CONFIG_SYS_PCI_64BIT 1
|
||||
#define CONFIG_PCI_SCAN_SHOW
|
||||
|
||||
/* SCSI */
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE 128
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 4
|
||||
|
||||
/* BOOT */
|
||||
#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"load_kernel=ext4load scsi 0:1 0x90100000 uImage-2004\0" \
|
||||
"load_fdt=ext4load scsi 0:1 0x95000000 ft2004-pci-64.dtb\0"\
|
||||
"boot_fdt=bootm 0x90100000 -:- 0x95000000\0" \
|
||||
"distro_bootcmd=run load_kernel; run load_fdt; run boot_fdt"
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue