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ram: rockchip: add controller code for PX30

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This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.

Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-11-15 11:04:40 +08:00
parent fba7bd4c34
commit 09d7872336
2 changed files with 344 additions and 0 deletions
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139
arch/arm/include/asm/arch-rockchip/sdram_pctl_px30.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Rockchip Electronics Co., Ltd
*/
#ifndef _ASM_ARCH_SDRAM_PCTL_PX30_H
#define _ASM_ARCH_SDRAM_PCTL_PX30_H
#include <asm/arch-rockchip/sdram_common.h>
struct ddr_pctl_regs {
u32 pctl[30][2];
};
/* ddr pctl registers define */
#define DDR_PCTL2_MSTR 0x0
#define DDR_PCTL2_STAT 0x4
#define DDR_PCTL2_MSTR1 0x8
#define DDR_PCTL2_MRCTRL0 0x10
#define DDR_PCTL2_MRCTRL1 0x14
#define DDR_PCTL2_MRSTAT 0x18
#define DDR_PCTL2_MRCTRL2 0x1c
#define DDR_PCTL2_DERATEEN 0x20
#define DDR_PCTL2_DERATEINT 0x24
#define DDR_PCTL2_PWRCTL 0x30
#define DDR_PCTL2_PWRTMG 0x34
#define DDR_PCTL2_HWLPCTL 0x38
#define DDR_PCTL2_RFSHCTL0 0x50
#define DDR_PCTL2_RFSHCTL1 0x54
#define DDR_PCTL2_RFSHCTL2 0x58
#define DDR_PCTL2_RFSHCTL4 0x5c
#define DDR_PCTL2_RFSHCTL3 0x60
#define DDR_PCTL2_RFSHTMG 0x64
#define DDR_PCTL2_RFSHTMG1 0x68
#define DDR_PCTL2_RFSHCTL5 0x6c
#define DDR_PCTL2_INIT0 0xd0
#define DDR_PCTL2_INIT1 0xd4
#define DDR_PCTL2_INIT2 0xd8
#define DDR_PCTL2_INIT3 0xdc
#define DDR_PCTL2_INIT4 0xe0
#define DDR_PCTL2_INIT5 0xe4
#define DDR_PCTL2_INIT6 0xe8
#define DDR_PCTL2_INIT7 0xec
#define DDR_PCTL2_DIMMCTL 0xf0
#define DDR_PCTL2_RANKCTL 0xf4
#define DDR_PCTL2_CHCTL 0xfc
#define DDR_PCTL2_DRAMTMG0 0x100
#define DDR_PCTL2_DRAMTMG1 0x104
#define DDR_PCTL2_DRAMTMG2 0x108
#define DDR_PCTL2_DRAMTMG3 0x10c
#define DDR_PCTL2_DRAMTMG4 0x110
#define DDR_PCTL2_DRAMTMG5 0x114
#define DDR_PCTL2_DRAMTMG6 0x118
#define DDR_PCTL2_DRAMTMG7 0x11c
#define DDR_PCTL2_DRAMTMG8 0x120
#define DDR_PCTL2_DRAMTMG9 0x124
#define DDR_PCTL2_DRAMTMG10 0x128
#define DDR_PCTL2_DRAMTMG11 0x12c
#define DDR_PCTL2_DRAMTMG12 0x130
#define DDR_PCTL2_DRAMTMG13 0x134
#define DDR_PCTL2_DRAMTMG14 0x138
#define DDR_PCTL2_DRAMTMG15 0x13c
#define DDR_PCTL2_DRAMTMG16 0x140
#define DDR_PCTL2_ZQCTL0 0x180
#define DDR_PCTL2_ZQCTL1 0x184
#define DDR_PCTL2_ZQCTL2 0x188
#define DDR_PCTL2_ZQSTAT 0x18c
#define DDR_PCTL2_DFITMG0 0x190
#define DDR_PCTL2_DFITMG1 0x194
#define DDR_PCTL2_DFILPCFG0 0x198
#define DDR_PCTL2_DFILPCFG1 0x19c
#define DDR_PCTL2_DFIUPD0 0x1a0
#define DDR_PCTL2_DFIUPD1 0x1a4
#define DDR_PCTL2_DFIUPD2 0x1a8
#define DDR_PCTL2_DFIMISC 0x1b0
#define DDR_PCTL2_DFITMG2 0x1b4
#define DDR_PCTL2_DFITMG3 0x1b8
#define DDR_PCTL2_DFISTAT 0x1bc
#define DDR_PCTL2_DBICTL 0x1c0
#define DDR_PCTL2_ADDRMAP0 0x200
#define DDR_PCTL2_ADDRMAP1 0x204
#define DDR_PCTL2_ADDRMAP2 0x208
#define DDR_PCTL2_ADDRMAP3 0x20c
#define DDR_PCTL2_ADDRMAP4 0x210
#define DDR_PCTL2_ADDRMAP5 0x214
#define DDR_PCTL2_ADDRMAP6 0x218
#define DDR_PCTL2_ADDRMAP7 0x21c
#define DDR_PCTL2_ADDRMAP8 0x220
#define DDR_PCTL2_ADDRMAP9 0x224
#define DDR_PCTL2_ADDRMAP10 0x228
#define DDR_PCTL2_ADDRMAP11 0x22c
#define DDR_PCTL2_ODTCFG 0x240
#define DDR_PCTL2_ODTMAP 0x244
#define DDR_PCTL2_SCHED 0x250
#define DDR_PCTL2_SCHED1 0x254
#define DDR_PCTL2_PERFHPR1 0x25c
#define DDR_PCTL2_PERFLPR1 0x264
#define DDR_PCTL2_PERFWR1 0x26c
#define DDR_PCTL2_DQMAP0 0x280
#define DDR_PCTL2_DQMAP1 0x284
#define DDR_PCTL2_DQMAP2 0x288
#define DDR_PCTL2_DQMAP3 0x28c
#define DDR_PCTL2_DQMAP4 0x290
#define DDR_PCTL2_DQMAP5 0x294
#define DDR_PCTL2_DBG0 0x300
#define DDR_PCTL2_DBG1 0x304
#define DDR_PCTL2_DBGCAM 0x308
#define DDR_PCTL2_DBGCMD 0x30c
#define DDR_PCTL2_DBGSTAT 0x310
#define DDR_PCTL2_SWCTL 0x320
#define DDR_PCTL2_SWSTAT 0x324
#define DDR_PCTL2_POISONCFG 0x36c
#define DDR_PCTL2_POISONSTAT 0x370
#define DDR_PCTL2_ADVECCINDEX 0x374
#define DDR_PCTL2_ADVECCSTAT 0x378
#define DDR_PCTL2_PSTAT 0x3fc
#define DDR_PCTL2_PCCFG 0x400
#define DDR_PCTL2_PCFGR_n 0x404
#define DDR_PCTL2_PCFGW_n 0x408
#define DDR_PCTL2_PCTRL_n 0x490
/* PCTL2_MRSTAT */
#define MR_WR_BUSY BIT(0)
void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
u32 dramtype);
int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
u32 dramtype);
u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
struct sdram_cap_info *cap_info,
u32 dram_type);
int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
u32 sr_idle, u32 pd_idle);
#endif

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drivers/ram/rockchip/sdram_pctl_px30.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
*/
#include <common.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch-rockchip/sdram.h>
#include <asm/arch-rockchip/sdram_pctl_px30.h>
/*
* rank = 1: cs0
* rank = 2: cs1
*/
void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
{
writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);
writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1);
setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
continue;
while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
continue;
}
/* rank = 1: cs0
* rank = 2: cs1
* rank = 3: cs0 & cs1
* note: be careful of keep mr original val
*/
int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
u32 dramtype)
{
while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
continue;
if (dramtype == DDR3 || dramtype == DDR4) {
writel((mr_num << 12) | (rank << 4) | (0 << 0),
pctl_base + DDR_PCTL2_MRCTRL0);
writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
} else {
writel((rank << 4) | (0 << 0),
pctl_base + DDR_PCTL2_MRCTRL0);
writel((mr_num << 8) | (arg & 0xff),
pctl_base + DDR_PCTL2_MRCTRL1);
}
setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
continue;
while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
continue;
return 0;
}
/*
* rank : 1:cs0, 2:cs1, 3:cs0&cs1
* vrefrate: 4500: 45%,
*/
int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
u32 dramtype)
{
u32 tccd_l, value;
u32 dis_auto_zq = 0;
if (dramtype != DDR4 || vrefrate < 4500 ||
vrefrate > 9200)
return (-1);
tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
tccd_l = (tccd_l - 4) << 10;
if (vrefrate > 7500) {
/* range 1 */
value = ((vrefrate - 6000) / 65) | tccd_l;
} else {
/* range 2 */
value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
}
dis_auto_zq = pctl_dis_zqcs_aref(pctl_base);
/* enable vrefdq calibratin */
pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
udelay(1);/* tvrefdqe */
/* write vrefdq value */
pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
udelay(1);/* tvref_time */
pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype);
udelay(1);/* tvrefdqx */
pctl_rest_zqcs_aref(pctl_base, dis_auto_zq);
return 0;
}
static int upctl2_update_ref_reg(void __iomem *pctl_base)
{
u32 ret;
ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
return 0;
}
u32 pctl_dis_zqcs_aref(void __iomem *pctl_base)
{
u32 dis_auto_zq = 0;
/* disable zqcs */
if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
(1ul << 31))) {
dis_auto_zq = 1;
setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
}
/* disable auto refresh */
setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
upctl2_update_ref_reg(pctl_base);
return dis_auto_zq;
}
void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq)
{
/* restore zqcs */
if (dis_auto_zq)
clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
/* restore auto refresh */
clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
upctl2_update_ref_reg(pctl_base);
}
u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
struct sdram_cap_info *cap_info,
u32 dram_type)
{
u32 tmp = 0, tmp_adr = 0, i;
for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
if (pctl_regs->pctl[i][0] == 0) {
tmp = pctl_regs->pctl[i][1];/* MSTR */
tmp_adr = i;
}
}
tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
switch (cap_info->dbw) {
case 2:
tmp |= (3ul << 30);
break;
case 1:
tmp |= (2ul << 30);
break;
case 0:
default:
tmp |= (1ul << 30);
break;
}
/*
* If DDR3 or DDR4 MSTR.active_ranks=1,
* it will gate memory clock when enter power down.
* Force set active_ranks to 3 to workaround it.
*/
if (cap_info->rank == 2 || dram_type == DDR3 ||
dram_type == DDR4)
tmp |= 3 << 24;
else
tmp |= 1 << 24;
tmp |= (2 - cap_info->bw) << 12;
pctl_regs->pctl[tmp_adr][1] = tmp;
return 0;
}
int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
u32 sr_idle, u32 pd_idle)
{
u32 i;
for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
writel(pctl_regs->pctl[i][1],
pctl_base + pctl_regs->pctl[i][0]);
}
clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
(0xff << 16) | 0x1f,
((sr_idle & 0xff) << 16) | (pd_idle & 0x1f));
clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
0xfff << 16,
5 << 16);
/* disable zqcs */
setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
return 0;
}