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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

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- Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC.
- Few bug fixes and updates related to SPI, hwconfig, ethernet,
  fsl-layerscape, pci, icid, PSCI
This commit is contained in:
Tom Rini 2019-11-11 14:19:04 -05:00
commit 0b73ef0c02
121 changed files with 286 additions and 144 deletions
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4
arch/arm/cpu/armv7/ls102xa/Kconfig
View File

@ -50,8 +50,8 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
config SECURE_BOOT
bool "Secure Boot"
config NXP_ESBC
bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.

7
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -45,6 +45,7 @@ config ARCH_LS1028A
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A050382
imply PANIC_HANG
config ARCH_LS1043A
@ -375,8 +376,8 @@ config EMC2305
Enable the EMC2305 fan controller for configuration of fan
speed.
config SECURE_BOOT
bool "Secure Boot"
config NXP_ESBC
bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature
@ -584,6 +585,8 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
config SYS_FSL_ERRATUM_A050382
bool
config SYS_FSL_HAS_RGMII
bool

2
arch/arm/cpu/armv8/fsl-layerscape/Makefile
View File

@ -24,10 +24,12 @@ endif
ifneq ($(CONFIG_ARCH_LX2160A),)
obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o
obj-y += icid.o lx2160_ids.o
endif
ifneq ($(CONFIG_ARCH_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
obj-y += icid.o ls2088_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1043A),)

6
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 NXP
* Copyright 2017-2019 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@ -1072,6 +1072,8 @@ static void config_core_prefetch(void)
if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
buf = buffer;
else
return;
prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
&arglen, buf);
@ -1221,7 +1223,7 @@ void __efi_runtime reset_cpu(ulong addr)
#endif
}
#ifdef CONFIG_EFI_LOADER
#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
void __efi_runtime EFIAPI efi_reset_system(
enum efi_reset_type reset_type,

10
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info)
};
uint i, cluster;
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
uint rcw_tmp;
#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info)
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
#define HWA_CGA_M2_CLK_SEL 0x00380000
#define HWA_CGA_M2_CLK_SHIFT 19
rcw_tmp = in_le32(&gur->rcwsr[5]);
@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info)
break;
}
#endif
#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
sys_info->freq_cga_m2 = sys_info->freq_systembus;
#endif
}
@ -176,10 +176,10 @@ int get_clocks(void)
#endif
#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB)
#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
#endif
#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB)
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
gd->arch.sdhc_clk = sys_info.freq_cga_m2;
#endif
#else

2
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c
View File

@ -18,6 +18,7 @@ struct icid_id_table icid_tbl[] = {
SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@ -28,6 +29,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

2
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c
View File

@ -13,6 +13,7 @@ struct icid_id_table icid_tbl[] = {
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
@ -25,6 +26,7 @@ struct icid_id_table icid_tbl[] = {
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

35
arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_SATA1_STREAM_ID),
SET_SATA_ICID(2, "fsl,ls2080a-ahci", FSL_SATA2_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

48
arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <asm/arch-fsl-layerscape/fsl_portals.h>
struct icid_id_table icid_tbl[] = {
SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),
SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
SET_SATA_ICID(1, "fsl,lx2160a-ahci", FSL_SATA1_STREAM_ID),
SET_SATA_ICID(2, "fsl,lx2160a-ahci", FSL_SATA2_STREAM_ID),
SET_SATA_ICID(3, "fsl,lx2160a-ahci", FSL_SATA3_STREAM_ID),
SET_SATA_ICID(4, "fsl,lx2160a-ahci", FSL_SATA4_STREAM_ID),
#ifdef CONFIG_FSL_CAAM
SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),
SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(4, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(5, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(6, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(7, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(8, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(9, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(10, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(11, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(12, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(13, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(14, FSL_SEC_STREAM_ID),
SET_SEC_DECO_ICID_ENTRY(15, FSL_SEC_STREAM_ID),
#endif
};
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);

10
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -341,7 +341,8 @@ void fsl_lsch3_early_init_f(void)
bypass_smmu();
#endif
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)
#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
set_icids();
#endif
}
@ -828,6 +829,11 @@ int fsl_setenv_mcinitcmd(void)
#endif
#ifdef CONFIG_BOARD_LATE_INIT
__weak int fsl_board_late_init(void)
{
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
@ -862,6 +868,6 @@ int board_late_init(void)
qspi_ahb_init();
#endif
return 0;
return fsl_board_late_init();
}
#endif

2
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -34,7 +34,7 @@ u32 spl_boot_device(void)
void spl_board_init(void)
{
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_LSCH2)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

5
arch/arm/dts/fsl-ls1088a.dtsi
View File

@ -192,4 +192,9 @@
status = "disabled";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
};

2
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@ -166,7 +166,7 @@ extern int fman_icid_tbl_sz;
#define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \
SET_ICID_ENTRY( \
(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
? NULL \

6
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -87,6 +87,8 @@
/* SATA */
#define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
#define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000)
#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000)
/* QDMA */
#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000)
@ -445,7 +447,9 @@ struct ccsr_gur {
u8 res_538[0x550 - 0x538]; /* add more registers when needed */
u32 sata1_amqr;
u32 sata2_amqr;
u8 res_558[0x570-0x558]; /* add more registers when needed */
u32 sata3_amqr;
u32 sata4_amqr;
u8 res_560[0x570 - 0x560]; /* add more registers when needed */
u32 misc1_amqr;
u8 res_574[0x590-0x574]; /* add more registers when needed */
u32 spare1_amqr;

17
arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h
View File

@ -105,8 +105,25 @@
#define FSL_SEC_JR4_STREAM_ID 68
#define FSL_SDMMC2_STREAM_ID 69
/*
* Erratum A-050382 workaround
*
* Description:
* The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
* correctly forwarded to the SMMU.
* Workaround:
* Program eDMA ICID in the eDMA_AMQR register in DCFG to 40.
*/
#ifdef CONFIG_SYS_FSL_ERRATUM_A050382
#define FSL_EDMA_STREAM_ID 40
#else
#define FSL_EDMA_STREAM_ID 70
#endif
#define FSL_GPU_STREAM_ID 71
#define FSL_DISPLAY_STREAM_ID 72
#define FSL_SATA3_STREAM_ID 73
#define FSL_SATA4_STREAM_ID 74
#endif

4
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1208,8 +1208,8 @@ config FSL_LAW
help
Use Freescale common code for Local Access Window
config SECURE_BOOT
bool "Secure Boot"
config NXP_ESBC
bool "NXP_ESBC"
help
Enable Freescale Secure Boot feature. Normally selected
by defconfig. If unsure, do not change.

8
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -38,7 +38,7 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
#include <asm/fsl_pamu.h>
#include <fsl_secboot_err.h>
#endif
@ -440,7 +440,7 @@ ulong cpu_init_f(void)
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
struct law_entry law;
#endif
#ifdef CONFIG_ARCH_MPC8548
@ -460,7 +460,7 @@ ulong cpu_init_f(void)
disable_tlb(14);
disable_tlb(15);
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
#if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT)
/* Disable the LAW created for NOR flash by the PBI commands */
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
@ -963,7 +963,7 @@ int cpu_init_r(void)
fman_enet_init();
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
#endif

10
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -33,7 +33,7 @@
#endif
#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && \
!defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
!defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define NOR_BOOT
#endif
@ -123,7 +123,7 @@ _start_e500:
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500MC) && \
!defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
@ -467,7 +467,7 @@ nexti: mflr r1 /* R1 = our PC */
blt 1b
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
!defined(CONFIG_SECURE_BOOT)
!defined(CONFIG_NXP_ESBC)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
@ -1065,7 +1065,7 @@ create_init_ram_area:
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
/* create a temp mapping in AS = 1 for Flash mapping
* created by PBL for ISBC code
*/
@ -1080,7 +1080,7 @@ create_init_ram_area:
* and for targets with CONFIG_SPL like T1, T2, T4, only for
* u-boot-spl i.e. CONFIG_SPL_BUILD
*/
#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \
#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
* to L3 Address configured by PBL for ISBC code

4
arch/powerpc/cpu/mpc8xxx/law.c
View File

@ -259,7 +259,7 @@ void init_laws(void)
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_E500) && \
!defined(CONFIG_E500MC)
/* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
* which is not disabled before transferring the control to uboot.
@ -268,7 +268,7 @@ void init_laws(void)
disable_law(0);
#endif
#if !defined(CONFIG_SECURE_BOOT)
#if !defined(CONFIG_NXP_ESBC)
/*
* if any non DDR LAWs has been created earlier, remove them before
* LAW table is parsed.

4
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -7,7 +7,7 @@
#define __FSL_SECURE_BOOT_H
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_NXP_ESBC
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
#elif defined(CONFIG_TARGET_BSC9132QDS)
@ -74,7 +74,7 @@
*/
#define CONFIG_FSL_ISBC_KEY_EXT
#endif
#endif /* #ifdef CONFIG_SECURE_BOOT */
#endif /* #ifdef CONFIG_NXP_ESBC */
#ifdef CONFIG_CHAIN_OF_TRUST
#ifdef CONFIG_SPL_BUILD

2
board/freescale/common/Kconfig
View File

@ -1,5 +1,5 @@
config CHAIN_OF_TRUST
depends on !FIT_SIGNATURE && SECURE_BOOT
depends on !FIT_SIGNATURE && NXP_ESBC
imply CMD_BLOB
imply CMD_HASH if ARM
select FSL_CAAM

2
board/freescale/common/Makefile
View File

@ -75,7 +75,7 @@ obj-$(CONFIG_TARGET_P5040DS) += p_corenet/
obj-$(CONFIG_LAYERSCAPE_NS_ACCESS) += ns_access.o
ifdef CONFIG_SECURE_BOOT
ifdef CONFIG_NXP_ESBC
obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
endif
obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o

2
board/freescale/common/p_corenet/tlb.c
View File

@ -43,7 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
#if !defined(CONFIG_SECURE_BOOT)
#if !defined(CONFIG_NXP_ESBC)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.

2
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -196,7 +196,7 @@ int board_init(void)
init_final_memctl_regs();
#endif
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_NXP_ESBC
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.

2
board/freescale/ls1046afrwy/ls1046afrwy.c
View File

@ -126,7 +126,7 @@ int checkboard(void)
int board_init(void)
{
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

2
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -407,7 +407,7 @@ int board_init(void)
ppa_init();
#endif
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

2
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -69,7 +69,7 @@ int board_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_NXP_ESBC
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.

3
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -20,6 +20,7 @@
#include <hwconfig.h>
#include <fsl_sec.h>
#include <asm/arch/ppa.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include "../common/qixis.h"
@ -358,6 +359,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_icid(blob);
return 0;
}
#endif

3
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -22,6 +22,7 @@
#include <asm/arch/soc.h>
#include <asm/arch/ppa.h>
#include <fsl_sec.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
@ -478,6 +479,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_icid(blob);
return 0;
}
#endif

2
board/freescale/lx2160a/lx2160a.c
View File

@ -27,6 +27,7 @@
#include "../common/qixis.h"
#include "../common/vid.h"
#include <fsl_immap.h>
#include <asm/arch-fsl-layerscape/fsl_icid.h>
#ifdef CONFIG_EMC2305
#include "../common/emc2305.h"
@ -684,6 +685,7 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fsl_mc_fixup_iommu_map_entry(blob);
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_icid(blob);
return 0;
}

4
board/freescale/t104xrdb/tlb.c
View File

@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
!defined(CONFIG_SECURE_BOOT)
!defined(CONFIG_NXP_ESBC)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
@ -37,7 +37,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
#elif defined(CONFIG_NXP_ESBC) && defined(CONFIG_SPL_BUILD)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
* the physical address of the SRAM is at 0xbffc0000,

2
configs/B4860QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_B4860QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x8FF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x8FF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_BSC9132QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/C29XPCIE_NOR_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_C29XPCIE=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_NAND_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_NOR_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_NAND_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_NOR_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P2041RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P3041DS_NAND_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P3041DS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P3041DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P4080DS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P4080DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P5020DS_NAND_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P5020DS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5020DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P5040DS_NAND_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/P5040DS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P5040DS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1023RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1023RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1024QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1024RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1040D4RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040D4RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1040QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1040RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1040RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1042D4RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042D4RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x30001000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y

2
configs/T1042RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1042RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T2080QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y

2
configs/T2080RDB_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080RDB=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T4160QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4160QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/T4240QDS_SECURE_BOOT_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T4240QDS=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_AHCI=y

2
configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AFRWY=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

2
configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2

2
configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1012ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

2
configs/ls1021aqds_nor_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_F is not set

2
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y

2
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1021ATWR=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

2
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1028AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

2
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1028ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_SYS_FSL_SDHC_CLK_DIV=1
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

2
configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1043ardb_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y

2
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y

2
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y

2
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1046aqds_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_SYS_TEXT_BASE=0x60100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_AHCI=y

2
configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1046AQDS=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y

2
configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2

2
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y

2
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
View File

@ -2,7 +2,7 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

2
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088AQDS=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2

2
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x20100000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2

2
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y
CONFIG_SYS_TEXT_BASE=0x80400000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y

2
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_TARGET_LS1088ARDB=y
CONFIG_TFABOOT=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SYS_MALLOC_F_LEN=0x6000
CONFIG_SECURE_BOOT=y
CONFIG_NXP_ESBC=y
CONFIG_QSPI_AHB_INIT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y

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