Like the other Logic PD OMAP35/DM37 boards, this board has device
tree enabled for U-Boot. This patch converts the board to enable
SPL_OF_CONTROL and further shrinks the device tree in SPL to limit
it to UART3 (console), MMC1, i2c1, and GPIO4 (for mmc1 CD and WP).
There appears to be a bug in minicom so users may need to
switch the minicom terminal emulation to ANSI from VT102 due
to the junk that gets pushed out of the UART on startup.
Signed-off-by: Adam Ford <aford173@gmail.com>
Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1].
Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.
[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
If UHS speed modes are enabled, a compatible SD card switches down to 1.8V
during enumeration. If after this a software reboot/crash takes place and
on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.
The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the card).
Because the beaglebone X15 (rev A,B and C), am57xx-evms and am57xx-idks don't
have this capability, disable voltage switching for these boards.
The major effect of this is that the maximum supported speed mode is now
high speed(50 MHz) down from SDR104(200 MHz).
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Sync with kernel dts by adding pinmuxes for mmc1 and mmc2. This fixes an
issue where mmc2 (eMMC) was coming up in HS52 mode instead of the
highest DDR52 mode.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.
According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.
In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.
Add a new pinctrl group for clock line without pullup to be used in boards
where mmc1_clk line is not connected to an external pullup.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Common Processor board is the baseboard that has most of the actual connectors,
power supply etc. A SOM (System on Module) is plugged on to the common
processor board and this contains the SoC, PMIC, DDR and basic highspeed
components necessary for functionality. Add initial dt support for this
common processor board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Update the power-domain-cells to 2 and add the permissions
to each node. Mark the following nodes accessed by r5 as shared:
- DDR node
- main uart 0
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The LS1021A-TSN is a development board built by VVDN/Argonboards in
partnership with NXP.
It features the LS1021A SoC and the first-generation SJA1105T Ethernet
switch for prototyping implementations of a subset of IEEE 802.1 TSN
standards.
Supported boot media: microSD card (via SPL), QSPI flash.
Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
is 64 MB in size and has an erase sector size of 256KB (therefore,
flashing the RCW would erase part of U-Boot).
Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
is only 32 MB in size but has an erase sector size of 64KB (therefore
the RCW image can be flashed without erasing U-Boot).
To avoid the problems above, the U-Boot base address has been selected
at 0x100000 (the start of the 5th 256KB erase sector), which works for
all board revisions. Actually 0x40000 would have been enough, but
0x100000 is common for all Layerscape devices.
eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
disabled.
Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Jianchao Wang <jianchao.wang@nxp.com>
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
[Vladimir] Code taken from https://github.com/openil/u-boot (which
itself is mostly copied from ls1021a-iot) and adapted with the following
changes:
- Add a008850 errata workaround
- Converted eTSEC, MMC to DM to avoid all build warnings
- Plugged in distro boot feature, including support for extlinux.conf
- Added defconfig for QSPI boot
- Added the board/freescale/ls1021atsn/README.rst for initial setup
- Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not
get overwritten during copying of the u-boot.bin payload from MMC to
DDR.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.
This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[Vladimir] Made the following changes:
- Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi
- Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 -
a mistake ported over from Linux. Each SGMII PCS lies on the private
MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS).
- Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs
- Completely removed non-DM_ETH support from ls1021atwr
- Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio"
and from "fsl,tsec" to "fsl,etsec2" to match Linux
For STM32 QSPI driver, "st,stm32-qspi" compatible string was first
introduced in U-boot. But later in kernel side, "st,stm32f469-qspi"
was used.
To simplify, align U-boot QSPI compatible string with kernel one.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
For STM32 QSPI driver, "st,stm32-qspi" compatible string was first
introduced in U-boot. But later in kernel side, "st,stm32f469-qspi"
was used.
To simplify, align U-boot QSPI compatible string with kernel one.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
We share the same default SPL boot order for all rk3288 boards,
use dts instead of hard code in board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The rk3288-firefly board have different setting for sdmmc
io, sync then from kernel mainline:
6fbc7275c7a9 Linux 5.2-rc7
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin
Associated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Let the board continue boot from the storage device where
it bootup.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
RK3399 use sdhci for eMMC and DW MMC for SD Card, and
spl will only try to boot from SDMMC if we don't specify
other boot device for spl-boot-order. So add sdhci and sdmmc
for spl-boot-order here.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync the dts files for the Rock960 boards from Linux to get the
latest changes and fixes for the devices.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Various FS/disk related fixes with security implications.
- Proper fix for the pci_ep test.
- Assorted bugfixes
- Some MediaTek updates.
- 'env erase' support.
The timer0 node has its two clocks written in reversed order. The timer0
is used as the tick timer which causes a problem that the time a delay
function used is 4 times longer.
This patch reverses these two clocks to solve this issue.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
The AM654 base board has a TCA9554/PCA9554-type GPIO expander on the
wkup_i2c0 bus at address 0x38 that is used to detect the presence of
daughter cards. Add a respective DTS description of this expander
to enable its use.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
To enable the use of an EEPROM-based board detection scheme we need to
be able to access the I2C bus associated with the EEPROMs across all
3 stages of U-Boot: R5 SPL, A53 SPL, and A53 U-Boot (proper). So go
ahead and add/update the wkup_i2c0 peripheral module DTS definitions
and its associated pinmux node accordingly.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Only U-Boot specifc DT properties or overrides, must be in -u-boot.dtsi.
Pinctrl nodes does not belong here. Now that pinctrl nodes are in kernel
DT, there is no reason to be keep these in -u-boot.dtsi. Move them to
proper places so that it would ease copying DT entries from kernel DT.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
With changes in the driver requiring phy related properties,
add the same for the SD card node to prevent breaking boot with
the driver update.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add mcu cpsw and its components along with scm_conf node
to have ethernet functional.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
dual colour LED and an optical S/PDIF connector.
Linux commit details about the sun8i-h3-beelink-x2.dts sync:
"ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2"
(sha1: cc4bddade114b696ab27c1a77cfc7040151306da)
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since we have limited resources in SPL, it is the best interest
to keep the SPL as small as possible and that includes the DTB.
There are a few items in the device tree that can be removed,
because these boards don't use them.
Signed-off-by: Adam Ford <aford173@gmail.com>
The MMC card-detect pin was incorrectly defined which was fixed.
This patch resync's the dts and removes the u-boot specific fix.
Signed-off-by: Adam Ford <aford173@gmail.com>
