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arm: dts: k3-am654: Update power-domains property for each node

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Update the power-domain-cells to 2 and add the permissions
to each node. Mark the following nodes accessed by r5 as shared:
- DDR node
- main uart 0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2019-06-07 19:24:47 +05:30 committed by Tom Rini
parent cd041c8041
commit 355be915ed
7 changed files with 18 additions and 13 deletions
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10
arch/arm/dts/k3-am65-main.dtsi
View File

@ -89,7 +89,7 @@
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47>;
power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@ -108,7 +108,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
@ -119,7 +119,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
@ -130,7 +130,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
@ -141,6 +141,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
};

2
arch/arm/dts/k3-am65-mcu.dtsi
View File

@ -24,6 +24,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
};

4
arch/arm/dts/k3-am65-wakeup.dtsi
View File

@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
#power-domain-cells = <1>;
#power-domain-cells = <2>;
};
k3_clks: clocks {
@ -60,6 +60,6 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
};

1
arch/arm/dts/k3-am65.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM654 SoC";

2
arch/arm/dts/k3-am654-base-board-u-boot.dtsi
View File

@ -26,7 +26,7 @@
reg = <0x0 0x4FA0000 0x0 0x1000>,
<0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
power-domains = <&k3_pds 48>;
power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
max-frequency = <25000000>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;

4
arch/arm/dts/k3-am654-ddr.dtsi
View File

@ -11,8 +11,8 @@
<0x0 0x02988000 0x0 0x2000>;
reg-names = "ss", "ctl", "phy";
clocks = <&k3_clks 20 0>;
power-domains = <&k3_pds 20>,
<&k3_pds 244>;
power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>,
<&k3_pds 244 TI_SCI_PD_SHARED>;
assigned-clocks = <&k3_clks 20 1>;
assigned-clock-rates = <DDR_PLL_FREQUENCY>;
u-boot,dm-spl;

8
arch/arm/dts/k3-am654-r5-base-board.dts
View File

@ -32,8 +32,8 @@
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x0 0x00a90000 0x0 0x10>;
power-domains = <&k3_pds 61>,
<&k3_pds 202>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 202 0>;
assigned-clocks = <&k3_clks 202 0>;
assigned-clock-rates = <800000000>;
@ -118,6 +118,10 @@
status = "okay";
};
&main_uart0 {
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_pmx0 {
u-boot,dm-spl;
wkup_uart0_pins_default: wkup_uart0_pins_default {