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arm: ls1021atwr: Convert to use driver model TSEC driver

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Now that we have added driver model support to the TSEC driver,
convert ls1021atwr board to use it.

This depends on previous DM series for ls1021atwr:
http://patchwork.ozlabs.org/patch/561855/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[Vladimir] Made the following changes:
- Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi
- Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 -
  a mistake ported over from Linux. Each SGMII PCS lies on the private
  MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS).
- Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs
- Completely removed non-DM_ETH support from ls1021atwr
- Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio"
  and from "fsl,tsec" to "fsl,etsec2" to match Linux
This commit is contained in:
Bin Meng 2019-07-19 00:29:59 +03:00 committed by Joe Hershberger
parent 1c8ad08674
commit f588b4d205
13 changed files with 85 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -296,7 +296,7 @@ int cpu_mmc_init(bd_t *bis)
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif

10
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -16,12 +16,17 @@
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev;
#else
struct eth_device *dev;
#endif
struct tsec_private *priv;
const char *enet_path, *phy_path;
char enet[16];
@ -29,7 +34,12 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
int phy_node;
int i = 0;
uint32_t ph;
#ifdef CONFIG_DM_ETH
char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
"ethernet@2d90000" };
#else
char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
#endif
for (; i < ARRAY_SIZE(name); i++) {
dev = eth_get_dev_by_name(name[i]);

32
arch/arm/dts/ls1021a-twr.dtsi
View File

@ -51,6 +51,26 @@
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet1 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet2 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
status = "okay";
};
&i2c0 {
status = "okay";
};
@ -84,12 +104,24 @@
sgmii_phy0: ethernet-phy@0 {
reg = <0x0>;
};
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
/* SGMII PCS for enet0 */
tbi0: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&mdio1 {
/* SGMII PCS for enet1 */
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";

30
arch/arm/dts/ls1021a.dtsi
View File

@ -350,12 +350,36 @@
<&platform_clk 1>;
};
enet0: ethernet@2d10000 {
compatible = "fsl,etsec2";
reg = <0x2d10000 0x1000>;
status = "disabled";
};
enet1: ethernet@2d50000 {
compatible = "fsl,etsec2";
reg = <0x2d50000 0x1000>;
status = "disabled";
};
enet2: ethernet@2d90000 {
compatible = "fsl,etsec2";
reg = <0x2d90000 0x1000>;
status = "disabled";
};
mdio0: mdio@2d24000 {
compatible = "gianfar";
device_type = "mdio";
compatible = "fsl,etsec2-mdio";
reg = <0x2d24000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
reg = <0x2d64000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2d24000 0x4000>;
};
usb@8600000 {

38
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -248,44 +248,6 @@ int board_mmc_init(bd_t *bis)
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
if (is_serdes_configured(SGMII_TSEC1)) {
puts("eTSEC1 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
puts("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}

2
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_nor_defconfig
View File

@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -42,7 +42,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_qspi_defconfig
View File

@ -42,7 +42,9 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -53,7 +53,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -54,7 +54,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -53,7 +53,9 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

28
include/configs/ls1021atwr.h
View File

@ -260,33 +260,7 @@
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC 1
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_ATHEROS
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_ETHPRIME "ethernet@2d10000"
#endif
/* PCIe */