Use toradex,colibri_t20 as the device-tree compatible node value rather
than toradex,t20 in accordance to our Apalis/Colibri T30 products.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add defines to allow reading recovery mode (RCM) boot type from the boot
information table (BIT) written by the boot ROM (BR) to the IRAM.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Since commit a26cd04920 ("arch: Make board selection choices
optional"), Kconfig could create such an insane .config file that
no SoC/board is selected.
This is now a real problem for Buildroot, for example.
(http://lists.busybox.net/pipermail/buildroot/2015-July/135125.html)
This commit drops the "optional" from the ARM target select menu
in favor of "Versatile family".
Rationale:
- Historically, Linux chose versatile_defconfig as the default
of ARM defconfig. (arch/arm/Makefile of Linux describes:
KBUILD_DEFCONFIG := versatile_defconfig)
- It was published by ARM Ltd.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
- Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel
v4.1
- Add config file for this board, enable DM and DM_GPIO
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not. Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
The "method" parameter was part of the original port of the driver from
the kernel. At some point this may have been added to allow for future
differentiation (as omap1 and omap2 have different GPIO IP blocks, so
this wasn't an unreasonable thing to do). At this point however it's
just extra overhead, so drop.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Re-sync DT files for am33xx with Linux Kernel v4.1
- Include DT file now for the "AM335x GP EVM" and build target for it,
via device tree and DM.
- We only need to provide platform data for UART when OF_CONTROL isn't
also enabled really. We can just push GPIO to coming from DT
Signed-off-by: Tom Rini <trini@konsulko.com>
Add initial support for CM-T43, an AM437x based SoM.
This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM
detection.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
AM43XX SoCs support up to 192 GPIO signals.
Make this amount available to the driver.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Add spi clock to the list of am43xx basic clocks to make the SPI
subsystem available on am43xx systems.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagan Teki <jteki@openedev.com>
HiKey is the first 96boards consumer edition compliant board. It features a hi6220
SoC which has eight ARM A53 cpu's.
This initial port adds support for: -
1) Serial
2) eMMC / SD card
3) USB
4) GPIO
It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable.
Notes:
eMMC has been tested with basic reading of eMMC partition into DDR. I have not
tested writing / erasing. Due to lack of clock control it won't be
running in the most performant high speed mode.
SD card slot has been tested for reading and booting kernels into DDR.
It is also currently configured to save the u-boot environment to the
SD card.
USB has been tested with ASIX networking adapter to tftpboot kernels
into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage
are correctly enumerated.
GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs.
Basic SoC datasheet can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf
Board schematic can be found here: -
https://github.com/96boards/documentation/blob/master/hikey/
96Boards-Hikey-Rev-A1.pdf
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
This patch adds the glue code for hi6220 SoC which has 2x synopsis
dw_mmc controllers. This will be used by the hikey board support
in subsequent patches.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
The semantics for non-static functions declared inline have changed in
gcc5, causing the empty functions not to be emitted as an external
symbol.
Since lowlevel_init() is only referenced from start.S, it should not be
declared inline at all.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>
[trini: Reword commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Remove unused external clocks and make a common definition
for all keystone platforms.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add print_cpuinfo() function and enable
CONFIG_DISPLAY_CPUINFO for keystone platforms,
so that cpu info can be displayed during boot.
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.
Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
This switches the Integrator boards over to using the device model
for its serial ports.
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.
In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.
So in this patch remove such code in flush_cache() and only call
flush_dcache_range().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Since some driver like ohci, lcd used dcache functions. But m68k don't
implement the invalidate_dcache_range()/flush_dcache_range() functions.
To avoid compiling errors this patch adds an weak empty stub function
for all m68k cpu.
Also each cpu can implement its own implementation. If not implemented
then by default is using an empty function.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Angelo Dureghello <angelo@sysam.it>
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini <trini@konsulko.com>
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.
For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.
This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.
It is up to each board to make use of this mechanism or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The change adds SPL build support to Timll DevKit3250 board, the
generated SPL image can be uploaded over UART5, JTAG or stored on
NAND. SPL is designed to load U-boot image from NAND.
All new NAND chip defines in board configuration are needed by
SPL NAND "simple" framework, the framework is used to reduce
potentially duplicated code from LPC32xx SLC NAND driver.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Enable BCM SF2 ethernet and PHY for BCM Cygnus SoC
Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
add support for the at91sam9260 based board smartweb from
siemens. SPL is used without serial support, as this
SoC has only 4k sram for running SPL. Here a U-Boot
bootlog:
RomBOOT
>
U-Boot 2015.07-rc2-00109-g4ae828c (Jun 15 2015 - 09:31:16 +0200)
CPU: AT91SAM9260
Crystal frequency: 18.432 MHz
CPU clock : 198.656 MHz
Master clock : 99.328 MHz
Watchdog enabled
DRAM: 64 MiB
WARNING: Caches not enabled
NAND: 256 MiB
In: serial
Out: serial
Err: serial
Net: macb0
Hit any key to stop autoboot: 0
U-Boot>
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.
Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: Tom Rini <trini@konsulko.com>
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Add a few extra sunxi display registers and constant defines.
Also rename some existing defines (e.g. dropping _GCTRL) and make
some more generic (e.g. dropping the 2x scaling from
SUNXI_LCDC_TCON1_TIMING_V_TOTAL).
This is a preparation patch for adding composite video out support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
To enable NAND flash in sunxi SPL,
pins 0-6, 8-22 and 24 on port C are configured.
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add code which uses the new functions for obtaining FPGA ID from
the scan manager. This new code prints the FPGA model attached to
the SoCFPGA during boot and sets environment variable "fpgatype",
which can be used to determine the FPGA model in U-Boot scripts.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Add code to get the FPGA type for Altera's SoCFPGA family of FPGA. The code
uses the scan manager to send jtag pulses that will return the FPGA ID.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Factor out the code which sends JTAG instruction followed by data
into separate function to tidy the code up a little.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Clean up the horrible macros present in the scan_manager.h . Firstly,
the function scan_mgr_io_scan_chain_prg() is static, yet all the macros
are used only within it, thus there is no point in having them in the
header file. Moreover, the macros are just making the code much less
readable, so remove them instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce generic function for accessing the JTAG scan chains in the
SCC manager. Make use of this function throughout the SCC manager to
replace the ad-hoc writes to registers and make the code less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Rework this function so it's clear that it is only polling for certain
bits to be cleared. Add kerneldoc. Fix it's return value to be either
0 on success and -ETIMEDOUT on error and propagate this through the
scan manager code.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Zap non-existent functions and place function prototypes at the
beginning of the header file.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Add a small workaround into the platform code which forces the SDMMC
into 8-bit mode (the default configuration for all socfpga platforms)
to work around breakage caused by missing patches in mainline which
switch the probing of SD/MMC to OF instead of static configuraiton.
The patches will hit mainline after the SPL series, so to avoid build
issues, add this small temporary workaround.
Signed-off-by: Marek Vasut <marex@denx.de>
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The GMAC can now be probed from OF, so enable DM ethernet and remove the
old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: Marek Vasut <marex@denx.de>
Add support for printing from which device the SoCFPGA board booted.
This decodes the BSEL settings and prints it in human readable form.
Signed-off-by: Marek Vasut <marex@denx.de>
Write necessary magic value into the Warm Boot from ON-Chip RAM
group Enable register to enable Warm reset support. Instead of
doing this in the reset_cpu() function, we do it in arch early
init to avoid breaking old kernel code which expects this magic
value to be already written into this register.
This magic is originally excavated from common/spl/spl.c in the
u-boot port from altera, where this value was written just before
the SPL jumped to actual U-Boot in the RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework spl_boot_device() such that it reads the BSEL settings from
system manager and decides from where to load U-Boot based on this
information.
Signed-off-by: Marek Vasut <marex@denx.de>
Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.
Signed-off-by: Marek Vasut <marex@denx.de>
Remove the custom SPL linker script, use the generic one instead.
The custom script doesn't bring in anything new and is only burden
to maintain.
Signed-off-by: Marek Vasut <marex@denx.de>
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.
Signed-off-by: Marek Vasut <marex@denx.de>
Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register
must be configured, so we can access all peripherals. The NIC-301 must
be configured so that the BootROM is not mapped into the SDRAM address
space.
Signed-off-by: Marek Vasut <marex@denx.de>
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.
This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.
Signed-off-by: Marek Vasut <marex@denx.de>
It is sufficient to pass in the scan chain ID into the function to determine
the remaining two parameters, so drop those params and determine them locally
in the function. The big-ish switch in the function is temporary and will be
replaced by a proper function call in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
This function is never used outside of scan_manager.c , so make it static.
Zap the prototype in scan_manager.h and move the documentation above the
function. Make the documentation kerneldoc compliant.
Signed-off-by: Marek Vasut <marex@denx.de>
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.
Signed-off-by: Marek Vasut <marex@denx.de>
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.
Signed-off-by: Marek Vasut <marex@denx.de>
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add alias for the SD/MMC controller, so it can be located by U-Boot OF support.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The SPI aliases are completely wrong. First, they point to non-existing
/spi@.* nodes instead of the correct /soc/spi@.* nodes. Second, the use
ad-hoc string instead of a handle. Furthermore, they are copied multiple
times in each board DTS.
So fix it such that we move these into socfpga.dtsi and make them use
the usual handles.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
board. The combination contains SoC, DRAM, eMMC, SD card slot,
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
E2220-1170 is a Tegra210 bringup board with onboard SoC, DRAM,
eMMC, SD card slot, HDMI, USB micro-B port, and sockets for various
expansion modules.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
T124/210 requires some specific configuration (VPR setup) to
be performed by the bootloader before the GPU can be used.
For this reason, the GPU node in the device tree is disabled
by default. This patch enables the node if U-boot has performed
VPR configuration.
Boards enabled by this patch are T124's Jetson TK1 and Venice2
and T210's P2571.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
U-boot is responsible for enabling the GPU DT node after all necessary
configuration (VPR setup for T124) is performed. In order to be able to
check whether this configuration has been performed right before booting
the kernel, make it happen during board_init().
Also move VPR configuration into the more generic gpu.c file, which will
also host other GPU-related functions, and let boards specify
individually whether they need VPR setup or not.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Additionally, ARM64 devices typically run a secure monitor in EL3 and
U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
code and data. These carve-outs are located at the top of 32-bit address
space. Restrict U-Boot's RAM usage to well below the location of those
carve-outs. Ideally, we would the secure monitor would inform U-Boot of
exactly which RAM it could use at run-time. However, I'm not sure how to
do that at present (and even if such a mechanism does exist, it would
likely not be generic across all forms of secure monitor).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
At present lower case is used for the regulator names in the device tree.
The kernel uses upper case and U-Boot will require this also since it will
move to a case-sensitive name check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the character output cannot be any earlier than
car_init_ret, where memory is available for a stack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
While the AP can access the main PMIC on snow, it must coordinate with the
EC which also wants access. Drop the old definition, which can in principle
generate collision errors. We will use the new arbitration driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
The new driver supports driver model and configuration via device tree. Add
a node for pit, which needs this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a description of the snow memory layout to assist flashing tools which
want to be able to deal with any exynos image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Line up the display with the line below, e.g.:
CPU: Exynos5250 @ 1.7 GHz
Model: Google Spring
DRAM: 2 GiB
MMC: EXYNOS DWMMC: 0
Also show the speed as GHz where appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.
Signed-off-by: Simon Glass <sjg@chromium.org>
On pit and pi the TPS65090 regulator is connected only to the EC and we
must use a tunnel to get to it. The existing U-Boot support relies on a
special driver. Add a tunnel definition so that the new device-model
TPS65090 driver can be used unmodified.
Signed-off-by: Simon Glass <sjg@chromium.org>
Snow and smdk5250 use a max77686 PMIC. We have a driver for this, so add
the relevant node to the device tree so it can be used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The kernel uses upper case for I2C unit addresses. Follow the same
convention to reduce differences.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Added PLL variables (dividers mask/shift, lock enable/detect, etc.)
to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210.
Should be equivalent to prior code on T124/114/30/20. Thanks
to Marcel Ziswiler for corrections to the T20/T30 values.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Added 38.4MHz/48MHz entries to pll_x_table for CPU PLL. Needs
to be measured - should be close to 700MHz (1.4G/2).
Note that some freqs aren't in the PLLU table in T210 TRM
(13, 26MHz), so I used the 12MHz table entry for them. They
shouldn't be selected since they're not viable T210 OSC freqs.
Since there are now 2 new OSC defines, all tables (pll_x_table,
PLLU) had to increase by two entries, but since 38.4/48MHz are
not viable osc freqs on T20/30/114, etc, they're just set to 0.
Signed-off-by: Tom Warren <twarren@nvidia.com>
CPU board (E2530) has a fan - turn it on via GPIO to keep
the SoC cool.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Disable a few things which interfere with the EFI init. This allows QEMU to
to boot into EFI, load a U-Boot payload then boot to the U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Disable a few things which interfere with the EFI init. This allows the
Minnowboard MAX to boot into EFI, load a U-Boot payload then boot to the
U-Boot prompt.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot is running from EFI some of the x86 init is replaced with
EFI-specific init. For example, since DRAM has already been set up, we only
need to find it, not init it. Add these functions so that boards can easily
allow booting from EFI if required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When U-Boot runs as an EFI payload it needs to avoid setting up the CPU
again. Also U-Boot currently does not handle interrupts for many devices, so
run with interrupts disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The EFI stub provides information to U-Boot in a table. This includes the
memory map which is needed to decide where to relocate U-Boot. Collect this
information in the early init code and store it in global_data.
Fix up the BIST code at the same time since we don't have it when booting
from EFI and can assume it is 0.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most EFI implementations use 64-bit. Add a way to build U-Boot as a 64-bit
EFI payload. The payload unpacks a (32-bit) U-Boot and starts it. This can
be enabled for x86 boards at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The procedure to drop from 64-bit mode to 32-bit is a bit messy. Add a
function to take care of it. It requires identity-mapped pages and that
the calling code is running below 4GB.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Rather than add these as open-coded values, create an enum with the commonly
used flags.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for building a 32/64-bit EFI stub for x86. This involves
building the startup and relocation code for either i386 or x86_64.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is useful to be able to load U-Boot onto a board even if is it already
running EFI. This can allow access to the U-Boot command interface, flexible
booting options and easier development.
The easiest way to do this is to build U-Boot as a binary blob and have an
EFI stub copy it into RAM. Add support for this feature, targeting 32-bit
initially.
Also add a way to detect when U-Boot has been loaded via a stub. This goes
in common.h since it needs to be widely available so that we avoid redoing
initialisation that should be skipped.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a linker script and relocation code for building 64-bit EFI
applications. This can be used for the EFI stub.
Signed-off-by: Simon Glass <sjg@chromium.org>
Improvements to how the payload is built:
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code currently requires CONFIG_SYS_TEXT_BASE but this should be
unnecessary. As a first step, remove the build-time limitation and report an
error instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This contains just enough to bring up the serial UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add support for the efi-x86 board, which supports running U-Boot as an
EFI 32-bit application.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add the required x86 glue code. This includes the initial start-up,
relocation and jumping to efi_main(). We also need to avoid fiddling with
interrupts.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bring in this file from Linux 4.1. It supports relocation features specific
to x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When running as an EFI application we must skip relocation. Add support for
this in the x86 relocation code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the toolchain flags to build U-Boot as a relocatable shared library,
as required by EFI.
Signed-off-by: Ben Stoltz <stoltz@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
When running as an EFI application, U-Boot must request memory from EFI,
and provide access to the boot services U-Boot needs.
Add library code to perform these tasks. This includes efi_main() which is
the entry point from EFI. U-Boot is built as a shared library.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 the global_data pointer is provided through a somewhat-bizarre and
x86-specific mechanism: the F segment register is set to a pointer to the
start of global_data, so that accesses can use this build-in register.
When running as an EFI application we don't want to mess with the Global
Descriptor Table (GDT) and there is little advantage (in terms of code size)
to doing so.
Allow global_data to be a simple variable in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix a typo, remove an unused field and make sure to use existing #define
constants instead of open-coded values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The GDT works but technically the length is incorrect. Fix this and add a
comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is now handled by generic U-Boot code so we do not need an x86 version.
It is no-longer called, so remove it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These flags now overlap some global ones. Adjust the x86-specific flags to
avoid this. Since this requires a change to the start.S code, add a way for
tools to find the 32-bit cold reset entry point. Previously this was at a
fixed offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Fix a typo, improve some comments and add a little more detail in some
cases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Intel Bayley Bay board is a BayTrail based board. Add this board
with existing baytrail fsp support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit adds the microcode blob for BayTrail-I B0 stepping,
CPUID signature 30671h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
BayTrail FSP Gold4 release adds one UPD parameter to control IGD
enable/disable.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a cpu1 node to the device tree and enable the MP initialization
on QEMU targets (i440fx and q35).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
When running SMP configuration on QEMU (tcg mode, no kvm), there is
a busy loop in start_aps(), calling udelay(), that waits for APs to
show up online. However, there is a chance that VCPU1 will be timeout
waiting, IOW the secondary VCPUs haven't started their execution yet.
This patch adds a 'pause' instruction in __udelay() only for QEMU
target, to give other VCPUs a chance to run. When QEMU sees the
'pause' instruction, it will yeild the execution to other CPUs.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Define base address of both usb xhci controllers in lsch3 config
in the format (IMMR + offset) for LS2085A
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by
USB XHCI stack for alignment
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Update imx register base address for i.MX6UL.
2. Remove duplicated MXS_APBH/GPMI/BCH_BASE.
3. Remove #ifdef for register addresses that equal to
"AIPS2_OFF_BASE_ADDR + 0x34000" for different chips.
4. According fuse map, complete fuse_bank4_regs.
5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX,
because we can use runtime check
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from
DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which
is not real id from DIGPROG register, so change i.MX6D to value 0x67 which
was not occupied.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again
by boards that depend on ARCH_MX6.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
cm-fx6 is an MX6 based board, and the menuconfig hierarchy should
reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3
support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes
A/B/C/D are not available, updated the serdes table accordingly with
some minor fix.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For running Chain of Trust when doing Secure Boot from NAND,
the Bootscript header and bootscript must be copied from NAND
to RAM(DDR).
The addresses and commands for the same have been defined.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Secure Boot Target is added for NAND for P3041.
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In case of secure boot, this default address maps to Boot ROM.
The Boot ROM code requires that the bootloader(U-boot) must lie
in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF.
In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is
configured as SRAM. U-Boot binary will be located on SRAM configured
at address 0xBFF00000.
In the U-Boot code, TLB entries are created to map the virtual address
0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Correct the value CONFIG_USB_MAX_CONTROLLER_COUNT macro to 1
for p1025 as it has one USB controller
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MAC1 acts as 1G/10G dual-role MAC on T1024. We introduce
macro SET_FMAN_RX_10G_TYPE2_LIODN for 10G MACs which have
same Port ID and same offset of address with 1G MAC.
Update it to match with the setting of fman in t1024 device
tree, otherwise there is no 'fsl,liodn' in
/proc/device-tree/soc@ffe000000/fman@400000/port@88000/
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
defconfig files are added and SFP version for these platforms
is updated.
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.
With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.
Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Moved Tegra config options to mach-tegra/Kconfig so that both
32-bit and 64-bit builds can co-exist for Tegra SoCs.
T210 will be 64-bit only (no SPL) and will require a 32-bit
AVP/BPMP loader.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon's 'tegra124: Implement spl_was_boot_source()' needs
a prototype for save_boot_params_ret() to build cleanly
for 64-bit Tegra210.
Signed-off-by: Tom Warren <twarren@nvidia.com>
A subsequent patch will enable the use of the architected timer on
ARMv8. Doing so implies that udelay() will be backed by this timer
implementation, and hence the architected timer must be ready when
udelay() is first called. The first time udelay() is used is while
resetting the debug UART, which happens very early. Make sure that
arch_timer_init() is called before that.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
On 64-bit SoCs the I-cache isn't enabled in early code, so the default
cache enable functions for 64-bit ARM can be used.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Most peripherals on Tegra can do DMA only to the lower 32-bit
address space, even on 64-bit SoCs. This limitation is
typically overcome by the use of an IOMMU. Since the IOMMU is
not entirely trivial to set up and serves no other purpose
(I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to
the lower 32-bit address space for RAM. This ensures that the
physical addresses of buffers that are programmed into the
various DMA engines are valid and don't alias to lower addresses.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.
swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
We should mark PCIe ECAM address range in the E820 table as reserved
otherwise kernel will not attempt to use ECAM.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
