The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host
Signed-off-by: Dave Liu <daveliu@freescale.com>
The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Now that there are no board-specific versions of
"denali_core_search_data_eye()", the weak binding on the common version
can be removed.
Signed-off-by: Larry Johnson <lrj@acm.org>
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.
This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
Signed-off-by: Stefan Roese <sr@denx.de>
This patch makes two additions to GPIO support:
First, it adds function gpio_read_in_bit() to read the a bit from the
GPIO Input Register (GPIOx_IR) in the same way that function
gpio_read_out_bit() reads a bit from the GPIO Output Register
(GPIOx_OR).
Second, it modifies function gpio_set_chip_configuration() to provide
an additional option for configuring the GPIO from the
"CFG_4xx_GPIO_TABLE".
According to the 440EPx User's Manual, when an alternate output is used,
the three-state control is configured in one of two ways, depending on
the particular output. The first option is to select the corresponding
alternate three-state control in the GPIOx_TRSH/L registers. The second
option is to select the GPIO Three-State Control Register (GPIOx_TCR) in
the GPIOx_TRSH/L registers, and set the corresponding bit in the
GPIOx_TCR register to enable the output. For example, the Manual
specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use
the alternate three-state control (first option), and specifies
configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output
enabled in the GPIOx_TCR register (second option).
Currently, gpio_set_chip_configuration() configures all alternate signal
outputs to use the first option. This patch allow the second option to
be selected by setting the "out_val" element in the table entry to
"GPIO_OUT_1". The first option is used when the "out_val" element is
set to "GPIO_OUT_0". Because "out_val" is not currently used when an
alternate signal is selected, and because all current GPIO tables set
"out_val" to "GPIO_OUT_0" for all alternate signals, this patch should
not change any existing configurations.
Signed-off-by: Larry Johnson <lrj@acm.org>
In an attmemt to clean up the 4xx start.S file, I removed the enabling
of the internal 405EP PCI arbiter. This is needed for multiple other
405EP platforms, like most of the esd 405EP. Now the internal PCI
arbiter is enabled again per default as it has been before.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM
controller. It should also work on the 440GRx. It is based on the DDR2
SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.
This code has been tested on prototype Korat boards with three Kingston
DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC
(two ranks). The Korat board has a single DIMM socket, but support has
been provided (though not tested) for boards with two DIMM sockets.
Signed-off-by: Larry Johnson <lrj@acm.org>
This patch creates a non-board-specific file for performing the SDRAM
data-eye search. It also adds ECC error checking to the test of valid
data on readback when ECC is enabled.
Signed-off-by: Larry Johnson <lrj@acm.org>
This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol
is defined, the PHY will advertise it's capabilities for autonegotiation
based on the capabilities shown in the PHY's status registers, including
1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will
advertise hard-coded capabilities, as before.
Signed-off-by: Larry Johnson <lrj@acm.org>
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is
without using the absolute path to the cpu node. This makes it possible
to use this U-Boot version with both versions of cpu-node naming
"cpu@0" and the former "PowerPC,440EPx@0".
Signed-off-by: Stefan Roese <sr@denx.de>
ppc4xx clear_bss() fails if BSS segment size is not
divisible by 4 without remainder. This patch provides
fix for this problem.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
flush + invalidate_dcache_range() expect the start and stop+1 address.
So the stop address is the first address behind (!) the range.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
By using aliases in the dts file, the ethernet node fixup is
much easier with the recently added functions.
Please note that the dts file needs the aliases for this to work.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch update the 4xx fdt support. It enabled fdt booting
on the AMCC Kilauea and Sequoia for now. More can follow later
quite easily.
Signed-off-by: Stefan Roese <sr@denx.de>
CAS-Latency=2, Write Recovery Time tWR=2
The max. supported bus frequency is 66 MHz. Therefore, changed
threshold to switch from 1:1 mode to 2:1 from 80 MHz to 66 MHz.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
As reported by Gerhard Berghofer:
in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
instead of PB18 and PB19.
which is obviously correct. There's currently no code that uses
USART3, but custom boards may run into problems.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Add a chip-features file providing definitions of the form
AT32AP700x_CHIP_HAS_<peripheral>
to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
instead of getting it via &immap->im_cpm.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
instead of getting it via &immap->im_gur.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update libfdt to commit 8eaf5e358366017aa2e846c5038d1aa19958314e from
the device tree compiler (dtc) project.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the generic fixup handling code out of cpu/mpc5xxx and cpu/mpc8260
into common/fdt_support.c and renamed:
do_fixup() -> do_fixup_by_path()
do_fixup_u32() -> do_fixup_by_path_u32()
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
au1x00_eth.c: In function 'au1x00_miiphy_write':
au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
au1x00_eth.c: In function 'au1x00_enet_initialize':
au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function)
au1x00_eth.c:246: error: (Each undeclared identifier is reported only once
au1x00_eth.c:246: error: for each function it appears in.)
au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function)
au1x00_eth.c: In function 'au1x00_miiphy_write':
au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void
make[1]: *** [au1x00_eth.o] Error 1
Fixed by moving these two functions forward.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Ugh. I *hate* to back this change out, but these compiler flags don't
work for relocation on all versions of GCC. I've not been able to
reproduce the environment in my setup (and hence, not been able to
find a combination that *does* work), so I've got no choice but to go
back to the old gcc flags and linker script.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Till now the UTL registers on 405EX were not initialized but left with
their default values. This patch new initializes some of the UTL
registers on 405EX.
Signed-off-by: Stefan Roese <sr@denx.de>
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h
Signed-off-by: Stefan Roese <sr@denx.de>
This patch disables the 44x d-cache on 'usb start' and
reenables it on 'usb stop'. This should be seen as a
temporary fix until the generic usb-ohci driver can
life with d-cache enabled.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch removes some redundant code and decrements the end
address of cache flush and invalidate by 1.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Most 4xx PPC capable of using an I2C bootrom for bootstrap setting
already print a line with the information which I2C bootrom is
used for bootstrap configuration. So we don't need this extra line
with "I2C boot EEPROM en-/dis-abled".
This patch also has a little code cleanup integrated.
Signed-off-by: Stefan Roese <sr@denx.de>
Since December 2003 the timer_interrupt_cpu() function in
cpu/mpc824x/interrupts.c contains what seems to be a superfluous
parameter. Remove it.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.
This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
I lately noticed, that newer 4xx board with GBit support sometimes don't
finish link autonegotiation in 4 seconds. Changing this timeout to 5
seconds seems fine here.
Signed-off-by: Stefan Roese <sr@denx.de>
We now use a value in the gd (global data) structure for the UART input
frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely
in get_sys_info().
Signed-off-by: Stefan Roese <sr@denx.de>
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.
Signed-off-by: Stefan Roese <sr@denx.de>
Change 4xx_uart.c:
- Use in_8/out_8 macros instead of in8/out8
- No need for UART_BASE marco anymore, now really handled via function
parameter
- serial_init_common() introduced
- Further coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch starts the rework of the PPC4xx serial driver. First we split
the file into two seperate files, one 4xx_uart.c with the 405/440 UART
handling code and the other one iop480_uart.c with the UART code for the
PLX-Tech IOP480 PPC (PPC403 based).
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.
Lot's of other macros are good candidates to be consolidated this way
in the future.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds endpoint support for the AMCC Kilauea eval board. It can
be tested by connecting a reworked PCIe cable (only 1x lane singles
connected) to another root-complex.
In this test setup, a 64MB inbound window is configured at BAR0 which maps
to 0 on the PLB side. So accessing this BAR0 from the root-complex will
access the first 64MB of the SDRAM on the PPC side.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Signed-off-by: Stefan Roese <sr@denx.de>
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Signed-off-by: Stefan Roese <sr@denx.de>
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
the SDR registers of the PCIe ports. This makes the overall design
clearer, since it removed a lot of switch statements which are not
needed anymore.
Also, the functions ppc4xx_init_pcie_rootport() and
ppc4xx_init_pcie_entport() are merged into a single function
ppc4xx_init_pcie_port(), since most of the code was duplicated.
This makes maintainance and porting to other 4xx platforms
easier.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Now we load $gp with _GLOBAL_OFFSET_TABLE_, but this is incorrect use.
As a general principle, we should use _gp for $gp.
Thanks to linker script's help we fortunately have _gp which equals to
_GLOBAL_OFFSET_TABLE_. But once _gp gets out of alignment, we will not
be able to access to GOT entires, global variables and procedure entry
points. The right thing to do is to use _gp.
This patch also introduce a new symbol `.gpword _GLOBAL_OFFSET_TABLE_'
which holds the offset from _gp. When updating GOT entries, we use this
offset and _gp to calculate the final _GLOBAL_OFFSET_TABLE_.
This patch is originally submitted by Vlad Lungu <vlad@comsys.ro>, then
I made some change to leave over num_got_entries.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Cc: Vlad Lungu <vlad@comsys.ro>
Hello,
This patch ensures the soft reset of the board for the 85xx boards
by setting the MSR[DE] in the do_reset function.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
The mpc85xx start code uses some magic numbers that we actually
have #defines for in <config.h> so use those instead.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.
Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
- convert frame size settings to be derived from a single base
- set frame size to the recommended default value
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
- correct configuration space mapping
- correct bus numbering
- better access to config space
Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Convert using fixup mechanism to suppressing MCK for the duration of config
read/write transaction: while fixups work fine with the case of a precise
exception, we identified a major drawback with this approach when there's
an imprecise case. In this scenario there is the following race condition:
the fixup is (by design) set to catch the instruction following the one
actually causing the exception; if an interrupt (e.g. decrementer) happens
between those two instructions, the ISR code is executed before the fixup
handler the machine check is no longer protected by the fixup handler as it
appears as within the ISR code. In consequence the fixup approach is being
phased out and replaced with explicit suppressing of MCK during a PCIe
config read/write cycle.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
When frame larger than local RX buffer is received, it is split and handled
by two buffer descriptors. Prior to this patch the FEC driver discarded
contents of a buffer descriptor without the 'LAST' bit set, so the first
part of the frame was lost in case of larger frames. This fix allows to
safely combine the two pieces into the whole frame.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
This patch adds support for multiple serial ports to the PXA target.
FFUART, BTUART and STUART are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
Tested on: lite5200b
Note: the fixup functions have not been moved to a common place. This
patch is targeted for immediate merging as in solves a build issue, but
the final name/location of the fixups is still subject to debate. I
propose to merge this now, and move the fixups in the next merge window
to be usable by all targets.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Fix the following warnings:
- usb.c:xx: warning: function declaration isn't a prototype
- usb_ohci.c:xxx: warning: passing argument 1 of '__fswab32' makes integer
from pointer wihtout a cast
Signed-off-by: Martin Krause <martin.krase@tqs.de>
platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.
this consequently eliminates CONFIG_ADD_RAM_INFO.
Thanks to Stefan for the hint.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
introduced in the implement board_add_ram_info patch as I was cleaning out the
magic numbers. sorry.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:
DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:
SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
this adds libfdt support code for the freescale
mpc8313erdb, mpc832xemds, mpc8349emds, mpc8349itx,
and gp boards.
Boards remain compatible with OF_FLAT_TREE.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
PCI clocks and QE frequencies weren't being updated, and the core clock
was being updated incorrectly. This patch also adds a /memory node if
it doesn't already exist prior to update.
plus some cosmetic trimming to single line comments.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Merge to two at45.c files into a common file, split to at45.c and spi.c
Fix spelling error in DM9161 PHY Support.
Initialize at91rm9200 board (and set LED).
Add PIO control for at91rm9200dk LEDs and Mux.
Change dataflash partition boundaries to be compatible with Linux 2.6.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
The PCI ID select values on the Arcadia main board differ depending
on the version of the hardware. The standard configuration supports
Rev 3.1. The legacy target supports Rev 2.x.
Signed-off-by Randy Vinson <rvinson@mvista.com>
This patch is against u-boot-mpc85xx.git of www.denx.com
Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.
Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
On e500 when we leave the 4k boot page we should use an absolute address since
we don't know where the board code may want us to be really running at.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The current implementation does not set the number of bank address bits
(BA) in the processor. The default assumes 2 logical bank bits. This
works fine for a DIMM that uses devices with 4 internal banks (SPD
byte17 = 0x4) but needs to be set appropriately for a DIMM that uses
devices with 8 internal banks (SPD byte17 = 0x8).
Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
Some patches had inserted warnings into the build:
* mpc8560ads declared data without using it
* cpu_init declared ecm and immap without using it in all CONFIGs
* MPC8548CDS.h had its default filenames changed so that they contained
"\m" in the paths. Made the defaults not Windows-specific (or
anything-specific)
Signed-off-by: Andy Fleming <afleming@freescale.com>
From: Ed Swarthout <Ed.Swarthout@freescale.com>
Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.
Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.
Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl
Move additional code from .text to boot page to make room for
exception vectors at start of image.
Handle Machine Check, External and Critical exceptions.
Fix e500 machine check error determination in traps.c
TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Only check for mpc8548 rev 1 when compiled for 8548.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Allow debugger to override flash cs0/cs1 settings to enable alternate
boot regions
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Calculate the data timeout based on values from the CSD instead of
just using a hardcoded DTOR value. This is a backport of a similar fix
in BSP 2.0, with one additional fix: the DTOCYC value is rounded up
instead of down.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
include/asm-avr32/div64.h was recently moved to include/div64.h, but
cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of
the patch was merged perhaps?)
This patch updates cpu/at32ap/interrupts.c so that the avr32 port
compiles again.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Instead of always using the largest blocksize the card supports, check
if it can support smaller block sizes and use 512 bytes if possible.
Most cards do support this, and other parts of u-boot seem to have
trouble with block sizes different from 512 bytes.
Also enable underrun/overrun protection.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com>
This patch was originall provided by David Mitchell <dmitchell@amcc.com>
and fixes a bug in the PLL clock calculation.
Signed-off-by: Stefan Roese <sr@denx.de>
Add support for the following DaVinci boards:
- DV_EVM
- SCHMOOGIE
- SONATA
Changes:
- Split into separate board directories
- Removed changes to MTD_DEBUG (or whatever it's called)
- New CONFIG_CMD party line followed
- Some cosmetic fixes, cleanup etc.
- Patches against the latest U-Boot tree as of now.
- Fixed CONFIG_CMD_NET in net files.
- Fixed CONFIG_CMD_EEPROM for schmoogie.
- Made sure it compiles and works (forceenv() link problem) on SCHMOOGIE and
DV_EVM. Can't check if it works on SONATA, don't have a board any more,
but it at least compiles.
Here is an excerpt from session log on SCHMOOGIE...
U-Boot 1.2.0-g6c33c785-dirty (Aug 7 2007 - 13:07:17)
DRAM: 128 MB
NAND: 128 MiB
In: serial
Out: serial
Err: serial
ARM Clock : 297MHz
DDR Clock : 162MHz
ETH PHY : DP83848 @ 0x01
U-Boot > iprobe
Valid chip addresses: 1B 38 3A 3D 3F 50 5D 6F
U-Boot > ping 192.168.253.10
host 192.168.253.10 is alive
U-Boot >
Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Zach Sadecki <Zach.Sadecki@ripcode.com>
Acked-by: Stefan Roese <sr@denx.de>
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.
Include MSSSR0 in error message.
Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Remove the duplicated source code of ecc command on the <board>.c,
for reused, move these code to cpu/mpc83xx directory.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
..and not the global fdt. Rename local fdt vars to blob so as not to
be confused with the global var with the same three-letter name.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Several node strings were not correct (trailing slashes and properties
in the strings)
Added setting of the timebase-frequency.
Improved error messages and use debug() instead of printf().
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The new name matches more closely the kernel's name, which is also
a much better description.
These are the mpc83xx changes made necessary by the function name change.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
83xx processor family has many reset sources, such as
power on reset, software hard reset, software soft reset,
JTAG, bus monitor, software watchdog, check stop reset,
external hard reset, external software reset.
sometimes, to figure out the fault of system, we need to
know the cause of reset early before the prompt of
u-boot present.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors. The code to update some bitfields was
compiled only on some processors. Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This change adds 8360 silicon revision 2.1 support to u-boot.
Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c. In a subsequent patch, this will be
utilized by the 85xx ports as well.
Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.
Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.
Fixed a u16 vendor compiler warning in AHCI driver too.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Add the ability for modules from the Schindler cm5200 family to use a
single U-Boot image:
- rename cm1_qp1 to cm5200
- add run-time module detection
- parametrize SDRAM configuration according to the module we are running on
Few minor, board-specific fixes included in this patch:
- better MAC address handling
- updated default environment ('update' command uses +{filesize} now)
- improved error messages in the auto-update code
- allow booting U-Boot from RAM (CFG_RAMBOOT)
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
During config transactions on the PCIe bus an attempt to scan for a
non-existent device can lead to a machine check exception with certain
peripheral devices. In order to avoid crashing in such scenarios the
instrumented versions of the config cycle read routines are introduced, so
the exceptions fixups framework can gracefully recover.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Rafal Jaworowski <raj@semihalf.com>
This brings back separate settings for PCIe bus numbers depending on chip
revision, which got eliminated in 2b393b0f0a
commit. 440SPe rev. A does NOT work properly with the same settings as for
the rev. B (no devices are seen on the bus during enumeration).
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)
Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)
Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map
Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
As spotted by Matthias Fuchs, the default output values for all GPIO1
outputs were not setup correctly. This patch fixes this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
