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Empirically set cpo and clk_adjust for mpc85xx DDR2 support

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This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
This commit is contained in:
Haiying Wang 2007-06-19 14:18:32 -04:00 committed by Andrew Fleming-AFLEMING
parent 3db0bef59e
commit d111d6382c
1 changed files with 7 additions and 5 deletions
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12
cpu/mpc85xx/spd_sdram.c
View File

@ -692,13 +692,10 @@ spd_sdram(void)
*/
cpo = 0;
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
if (effective_data_rate == 266 || effective_data_rate == 333) {
if (effective_data_rate <= 333) {
cpo = 0x7; /* READ_LAT + 5/4 */
} else if (effective_data_rate == 400) {
cpo = 0x9; /* READ_LAT + 7/4 */
} else {
/* Pure speculation */
cpo = 0xb;
cpo = 0x9; /* READ_LAT + 7/4 */
}
}
@ -905,7 +902,12 @@ spd_sdram(void)
if (spd.mem_type == SPD_MEMTYPE_DDR)
clk_adjust = 0x6;
else
#ifdef CONFIG_MPC8568
/* Empirally setting clk_adjust */
clk_adjust = 0x6;
#else
clk_adjust = 0x7;
#endif
ddr->sdram_clk_cntl = (0
| 0x80000000