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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: Rework of 4xx serial driver (4)
Change 4xx_uart.c: - Use in_8/out_8 macros instead of in8/out8 - No need for UART_BASE marco anymore, now really handled via function parameter - serial_init_common() introduced - Further coding style cleanup Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
e61cb8163a
commit
3248f63ad8
@ -20,7 +20,7 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*------------------------------------------------------------------------------+ */
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/*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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@ -40,14 +40,11 @@
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*/
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/*------------------------------------------------------------------------------- */
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/*
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* Travis Sawyer 15 September 2004
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* Added CONFIG_SERIAL_MULTI support
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*/
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#include <common.h>
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#include <commproc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <watchdog.h>
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#include "vecnum.h"
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@ -142,12 +139,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define ACTING_UART1_BASE UART1_BASE
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#endif
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#if defined(CONFIG_SERIAL_MULTI)
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#define UART_BASE dev_base
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#else
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#define UART_BASE ACTING_UART0_BASE
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#endif
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#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
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#error "External serial clock not supported on AMCC PPC405EP!"
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#endif
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@ -168,7 +159,6 @@ DECLARE_GLOBAL_DATA_PTR;
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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@ -178,12 +168,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines.
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+-----------------------------------------------------------------------------*/
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/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
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/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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/*-----------------------------------------------------------------------------+
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| Fifo
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@ -197,8 +181,36 @@ typedef struct {
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volatile static serial_buffer_t buf_info;
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#endif
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#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
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!defined(CFG_EXT_SERIAL_CLOCK)
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static void serial_init_common(u32 base, u32 udiv, u16 bdiv)
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{
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PPC4xx_SYS_INFO sys_info;
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u8 val;
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get_sys_info(&sys_info);
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available
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*/
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#ifdef CFG_EXT_SERIAL_CLOCK
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sys_info.freqUART = CFG_EXT_SERIAL_CLOCK;
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#else
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sys_info.freqUART = sys_info.freqUART / udiv;
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#endif
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out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */
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out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */
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out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */
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out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in_8((u8 *)base + UART_LSR); /* clear line status */
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val = in_8((u8 *)base + UART_RBR); /* read receive buffer */
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out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */
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out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */
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}
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#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \
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!defined(CFG_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv)
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{
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@ -264,8 +276,8 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
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get_sys_info(&sysinfo);
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plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
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sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) /
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sysinfo.pllFwdDivB);
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sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
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sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
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udiv = 256; /* Assume lowest possible serial clk */
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div = plloutb / (16 * baudrate); /* total divisor */
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umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
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@ -303,16 +315,11 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
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*/
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#if defined(CONFIG_440)
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#if defined(CONFIG_SERIAL_MULTI)
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int serial_init_dev (unsigned long dev_base)
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#else
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int serial_init(void)
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#endif
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int serial_init_dev(unsigned long base)
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{
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unsigned long reg;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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#ifdef CFG_EXT_SERIAL_CLOCK
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unsigned long tmp;
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#endif
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@ -325,18 +332,12 @@ int serial_init(void)
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udiv = 1;
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tmp = gd->baudrate * 16;
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bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
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gd->freqUART = CFG_EXT_SERIAL_CLOCK;
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#else
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized"
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* values that are subject to the 1/2 opb clock constraint
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*/
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serial_divs (gd->baudrate, &udiv, &bdiv);
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available
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*/
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gd->freqUART = gd->freqUART / udiv;
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#endif
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reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
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@ -356,34 +357,20 @@ int serial_init(void)
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MTREG(UART3_SDR, reg);
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#endif
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out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
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out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
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out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
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out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in8(UART_BASE + UART_LSR); /* clear line status */
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val = in8(UART_BASE + UART_RBR); /* read receive buffer */
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out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
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out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
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serial_init_common(base, udiv, bdiv);
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return (0);
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}
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#else /* !defined(CONFIG_440) */
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#if defined(CONFIG_SERIAL_MULTI)
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int serial_init_dev (unsigned long dev_base)
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#else
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int serial_init (void)
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#endif
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int serial_init_dev (unsigned long base)
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{
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unsigned long reg;
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unsigned long tmp;
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unsigned long clk;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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#ifdef CONFIG_405EX
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clk = tmp = 0;
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@ -447,88 +434,42 @@ int serial_init (void)
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bdiv = (clk + tmp / 2) / tmp;
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#endif /* CONFIG_405EX */
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/* Correct UART frequency in bd-info struct now that
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* the UART divisor is available
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*/
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#ifdef CFG_EXT_SERIAL_CLOCK
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gd->freqUART = CFG_EXT_SERIAL_CLOCK;
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#else
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gd->freqUART = gd->freqUART / udiv;
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#endif
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out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */
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out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */
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out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */
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out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */
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out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in8(UART_BASE + UART_LSR); /* clear line status */
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val = in8(UART_BASE + UART_RBR); /* read receive buffer */
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out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */
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out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */
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serial_init_common(base, udiv, bdiv);
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return (0);
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}
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#endif /* if defined(CONFIG_440) */
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#if defined(CONFIG_SERIAL_MULTI)
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void serial_setbrg_dev (unsigned long dev_base)
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#else
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void serial_setbrg (void)
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#endif
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void serial_setbrg_dev(unsigned long base)
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{
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#if defined(CONFIG_SERIAL_MULTI)
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serial_init_dev(dev_base);
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#else
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serial_init();
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#endif
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serial_init_dev(base);
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}
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#if defined(CONFIG_SERIAL_MULTI)
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void serial_putc_dev (unsigned long dev_base, const char c)
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#else
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void serial_putc (const char c)
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#endif
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void serial_putc_dev(unsigned long base, const char c)
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{
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int i;
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if (c == '\n')
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#if defined(CONFIG_SERIAL_MULTI)
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serial_putc_dev (dev_base, '\r');
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#else
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serial_putc ('\r');
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#endif
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serial_putc_dev(base, '\r');
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/* check THRE bit, wait for transmiter available */
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for (i = 1; i < 3500; i++) {
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if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20)
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if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20)
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break;
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udelay (100);
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}
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out8 (UART_BASE + UART_THR, c); /* put character out */
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out_8((u8 *)base + UART_THR, c); /* put character out */
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}
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#if defined(CONFIG_SERIAL_MULTI)
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void serial_puts_dev (unsigned long dev_base, const char *s)
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#else
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void serial_puts (const char *s)
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#endif
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void serial_puts_dev (unsigned long base, const char *s)
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{
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while (*s) {
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#if defined(CONFIG_SERIAL_MULTI)
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serial_putc_dev (dev_base, *s++);
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#else
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serial_putc (*s++);
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#endif
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}
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while (*s)
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serial_putc_dev (base, *s++);
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}
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#if defined(CONFIG_SERIAL_MULTI)
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int serial_getc_dev (unsigned long dev_base)
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#else
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int serial_getc (void)
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#endif
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int serial_getc_dev (unsigned long base)
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{
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unsigned char status = 0;
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@ -536,46 +477,45 @@ int serial_getc (void)
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#if defined(CONFIG_HW_WATCHDOG)
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WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
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#endif /* CONFIG_HW_WATCHDOG */
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status = in8 (UART_BASE + UART_LSR);
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if ((status & asyncLSRDataReady1) != 0x0) {
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status = in_8((u8 *)base + UART_LSR);
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if ((status & asyncLSRDataReady1) != 0x0)
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break;
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}
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if ((status & ( asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1 )) != 0) {
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out8 (UART_BASE + UART_LSR,
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out_8((u8 *)base + UART_LSR,
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asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1);
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}
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}
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return (0x000000ff & (int) in8 (UART_BASE));
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return (0x000000ff & (int) in_8((u8 *)base));
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}
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#if defined(CONFIG_SERIAL_MULTI)
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int serial_tstc_dev (unsigned long dev_base)
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#else
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int serial_tstc (void)
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#endif
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int serial_tstc_dev (unsigned long base)
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{
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unsigned char status;
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status = in8 (UART_BASE + UART_LSR);
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if ((status & asyncLSRDataReady1) != 0x0) {
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status = in_8((u8 *)base + UART_LSR);
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if ((status & asyncLSRDataReady1) != 0x0)
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return (1);
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}
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if ((status & ( asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1 )) != 0) {
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out8 (UART_BASE + UART_LSR,
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out_8((u8 *)base + UART_LSR,
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asyncLSRFramingError1 |
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asyncLSROverrunError1 |
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asyncLSRParityError1 |
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asyncLSRBreakInterrupt1);
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}
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return 0;
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}
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@ -588,11 +528,11 @@ void serial_isr (void *arg)
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const int rx_get = buf_info.rx_get;
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int rx_put = buf_info.rx_put;
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if (rx_get <= rx_put) {
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if (rx_get <= rx_put)
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space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
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} else {
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else
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space = rx_get - rx_put;
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}
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while (serial_tstc_dev (ACTING_UART0_BASE)) {
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c = serial_getc_dev (ACTING_UART0_BASE);
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if (space) {
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@ -603,8 +543,9 @@ void serial_isr (void *arg)
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rx_put = 0;
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if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
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/* Stop flow by setting RTS inactive */
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out8 (ACTING_UART0_BASE + UART_MCR,
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in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
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out_8((u8 *)ACTING_UART0_BASE + UART_MCR,
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in_8((u8 *)ACTING_UART0_BASE + UART_MCR) &
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(0xFF ^ 0x02));
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}
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}
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buf_info.rx_put = rx_put;
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@ -617,35 +558,35 @@ void serial_buffered_init (void)
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buf_info.rx_put = 0;
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buf_info.rx_get = 0;
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if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
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if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)
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serial_puts ("Check CTS signal present on serial port: OK.\n");
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} else {
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else
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serial_puts ("WARNING: CTS signal not present on serial port.\n");
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}
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irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
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serial_isr /*interrupt_handler_t *handler */ ,
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(void *) &buf_info /*void *arg */ );
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/* Enable "RX Data Available" Interrupt on UART */
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/* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
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out8 (ACTING_UART0_BASE + UART_IER, 0x01);
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out_8(ACTING_UART0_BASE + UART_IER, 0x01);
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/* Set DTR active */
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out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
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out_8(ACTING_UART0_BASE + UART_MCR,
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in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01);
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/* Start flow by setting RTS active */
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out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
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out_8(ACTING_UART0_BASE + UART_MCR,
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in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
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/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
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out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
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out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
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}
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void serial_buffered_putc (const char c)
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{
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/* Wait for CTS */
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#if defined(CONFIG_HW_WATCHDOG)
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while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
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while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10))
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WATCHDOG_RESET ();
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#else
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while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
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while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10));
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#endif
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serial_putc (c);
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}
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@ -674,14 +615,15 @@ int serial_buffered_getc (void)
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buf_info.rx_get = rx_get;
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rx_put = buf_info.rx_put;
|
||||
if (rx_get <= rx_put) {
|
||||
if (rx_get <= rx_put)
|
||||
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
||||
} else {
|
||||
else
|
||||
space = rx_get - rx_put;
|
||||
}
|
||||
|
||||
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
|
||||
/* Start flow by setting RTS active */
|
||||
out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
|
||||
out_8(ACTING_UART0_BASE + UART_MCR,
|
||||
in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02);
|
||||
}
|
||||
|
||||
return c;
|
||||
@ -706,8 +648,8 @@ int serial_buffered_tstc (void)
|
||||
#if (CONFIG_KGDB_SER_INDEX & 2)
|
||||
void kgdb_serial_init (void)
|
||||
{
|
||||
volatile char val;
|
||||
unsigned short br_reg;
|
||||
u8 val;
|
||||
u16 br_reg;
|
||||
|
||||
get_clocks ();
|
||||
br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
|
||||
@ -715,16 +657,16 @@ void kgdb_serial_init (void)
|
||||
/*
|
||||
* Init onboard 16550 UART
|
||||
*/
|
||||
out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
|
||||
out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
|
||||
out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
|
||||
out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
|
||||
out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
||||
val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
|
||||
val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
|
||||
out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
||||
val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */
|
||||
val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
}
|
||||
|
||||
void putDebugChar (const char c)
|
||||
@ -732,17 +674,16 @@ void putDebugChar (const char c)
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
|
||||
out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */
|
||||
|
||||
/* check THRE bit, wait for transfer done */
|
||||
while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
||||
while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
||||
}
|
||||
|
||||
void putDebugStr (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
while (*s)
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
int getDebugChar (void)
|
||||
@ -750,22 +691,23 @@ int getDebugChar (void)
|
||||
unsigned char status = 0;
|
||||
|
||||
while (1) {
|
||||
status = in8 (ACTING_UART1_BASE + UART_LSR);
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR);
|
||||
if ((status & asyncLSRDataReady1) != 0x0)
|
||||
break;
|
||||
}
|
||||
if ((status & ( asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
out8 (ACTING_UART1_BASE + UART_LSR,
|
||||
|
||||
if ((status & (asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
out_8((u8 *)ACTING_UART1_BASE + UART_LSR,
|
||||
asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1);
|
||||
}
|
||||
}
|
||||
return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
|
||||
|
||||
return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE));
|
||||
}
|
||||
|
||||
void kgdb_interruptible (int yes)
|
||||
@ -813,10 +755,12 @@ int serial1_init(void)
|
||||
{
|
||||
return (serial_init_dev(UART1_BASE));
|
||||
}
|
||||
|
||||
void serial0_setbrg (void)
|
||||
{
|
||||
serial_setbrg_dev(UART0_BASE);
|
||||
}
|
||||
|
||||
void serial1_setbrg (void)
|
||||
{
|
||||
serial_setbrg_dev(UART1_BASE);
|
||||
@ -831,6 +775,7 @@ void serial1_putc(const char c)
|
||||
{
|
||||
serial_putc_dev(UART1_BASE, c);
|
||||
}
|
||||
|
||||
void serial0_puts(const char *s)
|
||||
{
|
||||
serial_puts_dev(UART0_BASE, s);
|
||||
@ -850,6 +795,7 @@ int serial1_getc(void)
|
||||
{
|
||||
return(serial_getc_dev(UART1_BASE));
|
||||
}
|
||||
|
||||
int serial0_tstc(void)
|
||||
{
|
||||
return (serial_tstc_dev(UART0_BASE));
|
||||
@ -883,6 +829,39 @@ struct serial_device serial1_device =
|
||||
serial1_putc,
|
||||
serial1_puts,
|
||||
};
|
||||
#else
|
||||
/*
|
||||
* Wrapper functions
|
||||
*/
|
||||
int serial_init(void)
|
||||
{
|
||||
return serial_init_dev(ACTING_UART0_BASE);
|
||||
}
|
||||
|
||||
void serial_setbrg(void)
|
||||
{
|
||||
serial_setbrg_dev(ACTING_UART0_BASE);
|
||||
}
|
||||
|
||||
void serial_putc(const char c)
|
||||
{
|
||||
serial_putc_dev(ACTING_UART0_BASE, c);
|
||||
}
|
||||
|
||||
void serial_puts(const char *s)
|
||||
{
|
||||
serial_puts_dev(ACTING_UART0_BASE, s);
|
||||
}
|
||||
|
||||
int serial_getc(void)
|
||||
{
|
||||
return serial_getc_dev(ACTING_UART0_BASE);
|
||||
}
|
||||
|
||||
int serial_tstc(void)
|
||||
{
|
||||
return serial_tstc_dev(ACTING_UART0_BASE);
|
||||
}
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
||||
|
||||
#endif /* CONFIG_405GP || CONFIG_405CR */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user