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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'katmai-ddr-gda'
This commit is contained in:
commit
6399b23d60
@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2007
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -246,6 +246,18 @@ int checkboard (void)
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return 0;
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}
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/*
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* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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u32 ddr_wrdtr(u32 default_val) {
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
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}
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u32 ddr_clktr(u32 default_val) {
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return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
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}
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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{
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@ -3,7 +3,7 @@
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* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
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* DDR2 controller (non Denali Core). Those are 440SP/SPe.
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*
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* (C) Copyright 2007
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* (C) Copyright 2007-2008
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* COPYRIGHT AMCC CORPORATION 2004
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@ -111,8 +111,6 @@
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#define NUMMEMWORDS 8
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#define NUMLOOPS 64 /* memory test loops */
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#undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */
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/*
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* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
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* region. Right now the cache should still be disabled in U-Boot because of the
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@ -2268,39 +2266,6 @@ static void program_ecc(unsigned long *dimm_populated,
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return;
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}
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#ifdef CONFIG_ECC_ERROR_RESET
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/*
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* Check for ECC errors and reset board upon any error here
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*
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* On the Katmai 440SPe eval board, from time to time, the first
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* lword write access after DDR2 initializazion with ECC checking
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* enabled, leads to an ECC error. I couldn't find a configuration
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* without this happening. On my board with the current setup it
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* happens about 1 from 10 times.
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*
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* The ECC modules used for testing are:
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* - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
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*
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* This has to get fixed for the Katmai and tested for the other
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* board (440SP/440SPe) that will eventually use this code in the
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* future.
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*
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* 2007-03-01, sr
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*/
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static void check_ecc(void)
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{
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u32 val;
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mfsdram(SDRAM_ECCCR, val);
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if (val != 0) {
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printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
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val, mfdcr(0x4c), mfdcr(0x4e));
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printf("ECC error occured, resetting board...\n");
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do_reset(NULL, 0, 0, NULL);
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}
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}
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#endif
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static void wait_ddr_idle(void)
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{
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u32 val;
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@ -2375,15 +2340,6 @@ static void program_ecc_addr(unsigned long start_address,
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sync();
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eieio();
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wait_ddr_idle();
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#ifdef CONFIG_ECC_ERROR_RESET
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/*
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* One write to 0 is enough to trigger this ECC error
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* (see description above)
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*/
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out_be32(0, 0x12345678);
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check_ecc();
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#endif
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}
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}
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#endif
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@ -2409,17 +2365,10 @@ static void program_DQS_calibration(unsigned long *dimm_populated,
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* Read sample cycle auto-update enable
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*-----------------------------------------------------------------*/
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/*
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* Modified for the Katmai platform: with some DIMMs, the DDR2
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* controller automatically selects the T2 read cycle, but this
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* proves unreliable. Go ahead and force the DDR2 controller
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* to use the T4 sample and disable the automatic update of the
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* RDSS field.
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*/
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mfsdram(SDRAM_RDCC, val);
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mtsdram(SDRAM_RDCC,
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(val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
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| (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
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| SDRAM_RDCC_RSAE_ENABLE);
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/*------------------------------------------------------------------
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* Program RQDC register
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@ -2512,10 +2461,7 @@ static void DQS_calibration_process(void)
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{
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unsigned long rfdc_reg;
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unsigned long rffd;
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unsigned long rqdc_reg;
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unsigned long rqfd;
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unsigned long val;
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long rqfd_average;
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long rffd_average;
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long max_start;
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long min_end;
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@ -2533,10 +2479,14 @@ static void DQS_calibration_process(void)
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long max_end;
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unsigned char fail_found;
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unsigned char pass_found;
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#if !defined(CONFIG_DDR_RQDC_FIXED)
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u32 rqdc_reg;
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u32 rqfd;
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u32 rqfd_start;
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u32 rqfd_average;
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int loopi = 0;
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char str[] = "Auto calibration -";
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char slash[] = "\\|/-\\|/-";
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int loopi = 0;
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/*------------------------------------------------------------------
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* Test to determine the best read clock delay tuning bits.
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@ -2571,6 +2521,16 @@ calibration_loop:
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mfsdram(SDRAM_RQDC, rqdc_reg);
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mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
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SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
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#else /* CONFIG_DDR_RQDC_FIXED */
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/*
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* On Katmai the complete auto-calibration somehow doesn't seem to
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* produce the best results, meaning optimal values for RQFD/RFFD.
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* This was discovered by GDA using a high bandwidth scope,
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* analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
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* so now on Katmai "only" RFFD is auto-calibrated.
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*/
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mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
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#endif /* CONFIG_DDR_RQDC_FIXED */
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max_start = 0;
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min_end = 0;
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@ -2655,6 +2615,7 @@ calibration_loop:
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/* now fix RFDC[RFFD] found and find RQDC[RQFD] */
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mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
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#if !defined(CONFIG_DDR_RQDC_FIXED)
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max_pass_length = 0;
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max_start = 0;
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max_end = 0;
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@ -2727,8 +2688,6 @@ calibration_loop:
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spd_ddr_init_hang ();
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}
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blank_string(strlen(str));
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if (rqfd_average < 0)
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rqfd_average = 0;
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@ -2739,12 +2698,31 @@ calibration_loop:
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(rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
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SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
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blank_string(strlen(str));
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#endif /* CONFIG_DDR_RQDC_FIXED */
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/*
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* Now complete RDSS configuration as mentioned on page 7 of the AMCC
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* PowerPC440SP/SPe DDR2 application note:
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* "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
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*/
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mfsdram(SDRAM_RTSR, val);
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if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
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mfsdram(SDRAM_RDCC, val);
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if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
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val += 0x40000000;
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mtsdram(SDRAM_RDCC, val);
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}
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}
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mfsdram(SDRAM_DLCR, val);
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debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
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mfsdram(SDRAM_RQDC, val);
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debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
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mfsdram(SDRAM_RFDC, val);
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debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
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mfsdram(SDRAM_RDCC, val);
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debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
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}
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#else /* calibration test with hardvalues */
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/*-----------------------------------------------------------------------------+
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
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#undef CONFIG_STRESS
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/*-----------------------------------------------------------------------
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#define SDRAM_ECCCR 0x98 /* ECC error status */
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#define SDRAM_CID 0xA4 /* core ID */
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#define SDRAM_RID 0xA8 /* revision ID */
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#define SDRAM_RTSR 0xB1 /* run time status tracking */
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/*-----------------------------------------------------------------------------+
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| Memory Controller Status
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@ -605,8 +606,8 @@
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#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
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#define SDRAM_RFDC_RFOS_MASK 0x007F0000
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#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
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#define SDRAM_RFDC_RFFD_MASK 0x000003FF
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#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
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#define SDRAM_RFDC_RFFD_MASK 0x000007FF
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#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x7FF)<<0)
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#define SDRAM_RFDC_RFFD_MAX 0x7FF
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@ -690,6 +691,7 @@
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#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
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#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
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#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
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#define SDRAM_CLKTR_CLKP_90_DEG_ADV 0x40000000
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/*-----------------------------------------------------------------------------+
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| SDRAM Write Timing Register
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@ -790,6 +792,12 @@
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#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
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#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
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#define SDRAM_RTSR_TRK1SM_MASK 0xC0000000 /* Tracking State Mach 1*/
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#define SDRAM_RTSR_TRK1SM_ATBASE 0x00000000 /* atbase state */
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#define SDRAM_RTSR_TRK1SM_MISSED 0x40000000 /* missed state */
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#define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */
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#define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */
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#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
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#endif /* CONFIG_440SPE */
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