On some platform we have sufficient memory available early on to allow
setting up and using a basic BSS prior to entering board_init_f(). Doing
so can for example be used to carry state over to board_init_r() without
having to resort to extending U-Boot's global data structure.
To support such scenarios add a Kconfig option called CONFIG_SPL_EARLY_BSS
to allow moving the initialization of BSS prior to entering board_init_f(),
if enabled. Note that using this option usually should go along with using
CONFIG_SPL_SEPARATE_BSS and configuring BSS to be located in memory
actually available prior to board_init_f().
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
With changes in the driver requiring phy related properties,
add the same for the SD card node to prevent breaking boot with
the driver update.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel. This also syncs the main_pmx0 node
as a side effect.
Also change the name of the driver to match the compatible in kernel.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
So far USB was not enabled for the Allwinner H6 boards, as the PHY
driver was not ready and the clock gates were missing. Since this is now
fixed, let's add the PHY and the OHCI/EHCI drivers to the build, for
all existing H6 boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Probably for no particular reason SUNXI_GPIO was still defined the "old
way", in header files only.
Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove
another line from our dreadful config_whitelist.txt.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add some basic line delay values to be used with DDR3 DRAM chips on
some H6 TV boxes.
Taken from a register dump after boot0 initialised the DRAM.
Put them as the default delay values for DDR3 DRAM until we know better.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add a routine to program the timing parameters for DDR3-1333 DRAM chips
connected to the H6 DRAM controller.
The values were gathered from doing back-calculations from a register
dump, trying to match them up with the official JEDEC DDDR3 spec.
If in doubt, the register dump values were taken for now, but the JEDEC
recommendation were added as a comment.
Many thanks to Jernej for contributing fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
At the moment the H6 DRAM driver only supports LPDDR3 DRAM.
Extend the driver to cover DDR3 DRAM as well.
The changes are partly motivated by looking at the ZynqMP register
documentation, partly by looking at register dumps after boot0/libdram
has initialised the controller.
Many thanks to Jernej for contributing some fixes!
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Currently the H6 DRAM driver only supports one kind of LPDDR3 DRAM.
Split the timing parameters for this LPDDR3 configuration into a
separate file, to allow selecting an alternative later at compile time
(as the sunxi-dw driver does).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Using memcpy() is, however tempting, not a good idea: It depends on the
specific implementation of memcpy, also lacks barriers. In this
particular case the first registers were written using 64-bit writes,
and the last register using four separate single-byte writes.
Replace the memcpy with a proper loop using the writel() accessor.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Add mcu cpsw and its components along with scm_conf node
to have ethernet functional.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
A very simple test for DM_MDIO, mimicks a register write/read through the
sandbox bus to a dummy PHY.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a
dual colour LED and an optical S/PDIF connector.
Linux commit details about the sun8i-h3-beelink-x2.dts sync:
"ARM: dts: sun8i: h3: Add ethernet0 alias to Beelink X2"
(sha1: cc4bddade114b696ab27c1a77cfc7040151306da)
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Since we have limited resources in SPL, it is the best interest
to keep the SPL as small as possible and that includes the DTB.
There are a few items in the device tree that can be removed,
because these boards don't use them.
Signed-off-by: Adam Ford <aford173@gmail.com>
The MMC card-detect pin was incorrectly defined which was fixed.
This patch resync's the dts and removes the u-boot specific fix.
Signed-off-by: Adam Ford <aford173@gmail.com>
The USE_TINY_PRINTF symbol only changes things within SPL and TPL
builds, so make it depend on that support. Next, make it default as
within these cases we should rarely have need of more advanced print
formats outside of the debug context.
To do this, in a few cases we need to correct our Kconfig dependencies
as we had cases of non-SPL targets select'ing this symbol. Finally, in
the case of a few boards we really do need the full printf
functionality.
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts LEGO MINDSTORMS EV3 to the driver model. MMC, SERIAL, SPI
and SPI_FLASH are converted.
The device tree contains only the minimal nodes required by U-Boot
since the size of U-Boot is limited to 256K on this device.
Signed-off-by: David Lechner <david@lechnology.com>
Since pinctrl_stm32 driver update, each gpio bank is now binded
by pinctrl driver. The compatible string "st,stm32-gpio" becomes
useless, remove it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
arch/arm/mach-stm32mp/bsec.c: In function 'stm32mp_bsec_read':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (offset >= STM32_BSEC_OTP_OFFSET) {
^~
arch/arm/mach-stm32mp/bsec.c: In function 'stm32mp_bsec_write':
warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (offset >= STM32_BSEC_OTP_OFFSET) {
^~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This patch solves the following warnings:
arch/arm/mach-stm32mp/cpu.c:378:16: warning: comparison between signed
and unsigned integer expressions [-Wsign-compare]
if (instance > ARRAY_SIZE(serial_addr))
^
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of Trusted boot chain with OP-TEE
- reserved 32MB at the end of the DDR for OP-TEE
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Synchronize device tree with v5.2-rc4 label and
update the associated u-boot dtsi.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tested-by: Pierre-Jean Texier <pjtexier@koncepto.io>
U-Boot should disable nodes in device tree if needed according
ETZPC status in ft_system_setup().
ETZPC itself use an array on addresses to do the match between the status
bits and the node.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add IPCC mailbox support on stm32mp157 eval and disco boards.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
- Minor tracing and PCI improvements
- Various other minor fixes
- Conversion of patman, dtoc and binman to support Python 3
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Merge tag 'dm-pull-9jul19-take2' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm
- Sandbox improvements including .dts refactor
- Minor tracing and PCI improvements
- Various other minor fixes
- Conversion of patman, dtoc and binman to support Python 3
- SPL SATA enhancements to allow booting from RAW SATA device
needed for Clearfog (Baruch)
- Enable SATA booting on Clearfog (Baruch)
- Misc changes to Turris Omnia (Marek)
- Enable CMD_BOOTZ and increase SYS_BOOTM_LEN on crs305-1g-4s
(Luka)
- Enable FIT support for db-xc3-24g4xg (Chris)
- Enable DM_SPI on Keymile Kirkwood board with necessary changes
for this (Pascal)
- Set 38x and 39x AVS on lower frequency (Baruch)
- import DT updates from Linux
- add UniPhier SPI controller driver
- make U-Boot image for 64bit SoCs position independent
- tidy up various init code for next generation SoCs
- misc cleanups
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Merge tag 'uniphier-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2019.10
- import DT updates from Linux
- add UniPhier SPI controller driver
- make U-Boot image for 64bit SoCs position independent
- tidy up various init code for next generation SoCs
- misc cleanups
The board_early_init_f() inits clock before initing pinmux. However,
the clock configuration code might need to adjust PMIC settings of a
PMIC on I2C bus (e.g. board/ti/am335x/board.c does that). If the I2C
bus pin muxing is not configured before attempting to communicate
with the PMIC, the communication will silently fail and the prcm_init()
may configure fast enough CPU clock that the default voltage provided
by the PMIC would be insufficient and the platform would become
unstable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Tom Rini <trini@konsulko.com>
The name CONFIG_LEGACY_IMAGE_FORMAT reads slightly better along with
allowing us to avoid a rather nasty Kbuild/Kconfig issue down the line
with CONFIG_IS_ENABLED(IMAGE_FORMAT_LEGACY). In a few places outside of
cmd/ switch to using CONFIG_IS_ENABLED() to test what is set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Overload the weak function board_boot_order() so that besides choosing
the main boot device, we can fallback on USB boot by returning in the
BootROM, eg. if the NOR flash is empty while it was the primary boot
medium.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The _main call is not supposed to return at all: don't link the
branch.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Implement the weak board_return_to_bootrom() function so that when
enabling the spl_bootrom.c driver, one can make use of usbboot on
spear platforms. All necessary information to return to the BootROM
are stored in the BootROM's stack. The SPL stack pointer is reset so
we save the BootROM's stack pointer into the SPL .data section.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
There is no reason to do the few spear-related initialization, in a
different procedure than 'reset'. Spare one branching and get a linear
code flow by removing this indirection.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The link register is stored in R14. ARM assembly code allows to use
the 'lr' name to reference it instead of 'r14' which is not very
meaningful. Do the substitution to ease the reading.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Quoting ARM "RealView Compilation Tools Assembler Guide v4.0":
PUSH and POP are synonyms for STMDB and LDM (or LDMIA), with
the base register sp (r13), and the adjusted address written
back to the base register.
PUSH and POP are the preferred mnemonic in these cases.
Let's follow this recommandation to ease the reading and substitute
LDMIA/STMDB operations with PUSH/POP mnemonics.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Before cleaning a bit further the spear/start.S file, apply a few
cosmetic changes: capital letters, comment indentation and small
rewriting.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This comment describes the board state at the moment where we enter
the SPL. The description is entirely wrong; re-write it to fit the
reality.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
SPL BSS lies in SRAM and is actually initialized to 0 by the SPL in
arch/arm/lib/crt0.S:_main(), which is called by cpu_init_crit.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
It is clearly stated that board_init_f should *not* call
board_init_r. Indeed, board_init_f should return. The code will
continue through arch/arm/lib/crt0.S which will do more setup before
calling board_init_r.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reduce Auto Voltage Scaling VDD limit when core frequency is lower than
1600MHz. This reduces core voltage level from 1.25V to 1.15V, which
saves power.
The code is taken from Marvell's U-Boot 2013.01 revision 18.06.
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
KM Kirkwood boards now implement the driver model for its SPI flash
interface. Therefore, the old board specific claim and release functions
can be deleted. The preprocessor definition CONFIG_SYS_KW_SPI_MPP is yet
unused as well. All its appearances and dependencies are removed in the
kirkwood_spi driver, header files and finally the configuration whitelist.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
In order to migrate the SPI flash interface to the driver model, the SPI
configuration needs to be added in the KM Kirkwood device tree file.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Stefan Roese <sr@denx.de>
As preparation for the upcoming transferring of configurations from header
files to Kconfig, a common Kconfig file for all KM boards was created. For
the moment, it only sources the other three, more specific, Kconfig files.
Therefore, the architecture Kconfig files now include the common Kconfig
file. Also, the configuration selection for KM boards was moved from the
architecture Kconfig files to the board specific Kconfig files.
Signed-off-by: Pascal Linder <pascal.linder@edu.hefr.ch>
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Enable SATA peripherals in SPL to allow boot from SATA.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Add the required Kconfig and macro definitions to allow boot from SATA
on Armada 38x systems.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SPL does not initialize mbus_dram_info. Don't change the ahci mbus
settings of the ROM. This allows the ahci to work in SPL.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This test is built on top of the existing swap_case driver. It adds EA
capability structure support to swap_case and uses that to map BARs.
BAR1 works as it used to, swapping upper/lower case. BARs 2,4 map to a
couple of magic values.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a test to check the management of the U-boot relocation properties
for device tree SPL generation (fdtgrep result) and platdata:
- 'dm-pre-proper' and 'dm-tpl' not included in SPL
- 'dm-pre-reloc' and 'dm-spl' included in SPL
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This struct is not defined in this header file. Add a forward declaration
so that it can be included in any context.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since the SPI nor conversion, 'sf probe' does not work on sandbox. Fix
this by using the expected compatible string in the flash node.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: cd35365762 (mtd: sf_probe: remove spi-flash compatible)
When cross-compiling, sometimes sdl-config must come from a different path
from the default. Add a way to override it, by adding SDL_CONFIG to the
environment before building U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
We normally want to load U-Boot from SPL, but if a board wants to do
something else, it is currently not possible since the standard loader
has the top priority. Lower it to allow other SPL_LOAD_IMAGE_METHOD()
declarations to override it.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present 'sf probe' does not work since it cannot find SPI bus 0. Add
an alias to correct this, now that we no-longer have the --spi_sf option.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present sandbox and sandbox64 have duplicated nodes. This is hard to
maintain since changes in one need to be manually added to the other.
Create a common file to solve this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Various nodes have been added and adjusted with sandbox. Move these
changes over to sandbox64.dts to keep these in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
The base of DRAM will be changed for the next generation SoC.
The addresses needed for booting the kernel should be shifted
according to the DRAM base.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base of DRAM will be changed for the next generation SoC.
Set the base address to the 'dram_base' environment variable, which
will be useful for scripting.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base of DRAM will be changed for the next generation SoC.
To support it along with existing SoCs in the single defconfig,
set 'loadaddr' at boot-time by adding the offset to the DRAM base.
CONFIG_SYS_LOAD_ADDR is still hard-coded for compilation, but the
value from environment variable 'loadaddr' should be used.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The base address of DRAM was 0x80000000 for all the ARM SoCs of this
family in the past. It will be changed to 0x20000000 for a planned new
SoC. To support multiple SoCs by the single uniphier_v8_defconfig, the
base must be run-time determined.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, mem_map is hard-coded, and it worked well until the last
SoC. For a planned new SoC, the addresses of peripherals and DRAM
will be changed. Set it up run-time.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, dram_init() code relies on the fact the DRAM size
configuration exists in the SG_MEMCONF register.
This will no longer be true for a planned new SoC, which will
replace SG_MEMCONF with a different register.
Refactor the hook in a more generic way.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Until the last SoC, the register addresses have been hard-coded because
they are always constant. For a planned new SoC, the register bases
will be completely changed. I insist on supporting multiple SoCs/boards
by a single defconfig (uniphier_v8_defconfig) since duplicating similar
defconfig files is a maintenance burden. The base addresses must be
fixed-up at run-time somehow.
Previously, the board init code identified the SoC by reading out the
SG_REVISION register. This is much easier than parsing DT.
You cannot do it any more because the base address of SG will be
changed. The SG_REVISION register exists to read out the SoC ID, but
you never know its address before identifying the SoC. Oh well.
So, the possible solution is to parse the DT, and find out the node
with "*-soc-glue" compatible string. Then, sg_base is set to the value
of the "reg" property. The sc_base is set up likewise.
It is worth noting a pit-fall. Having sc_base and sg_base in the global
scope will make the life easier, but the global variables are poorly
supported before the relocation. In fact, the .bss section overwraps
with DT. Allocating them in the .bss section would break DT. So, I gave
dummy initializers to assign them in the .data section.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SC_* macros represent the address of SysCtrl registers.
For a planned new SoC, its base address will be changed.
Turn the SC_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The SG_* macros represent the address of SoC-glue registers.
For a planned new SoC, its base address will be changed.
Turn the SG_* macros into the offset from the base address.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The planned new SoC does not have SBC (System Bus Controller) block.
Make boot_is_swapped() an optional hook.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot initialize SBC
(System Bus Controller), which may not be really necessary.
Check the "socionext,uniphier-system-bus" node in DT run-time.
If and only if it is found and its "status" property is okay,
initialize the SBC block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_MICRO_SUPPORT_CARD is enabled, U-Boot tries to get access
to the devices on the support card, which may not actually exist.
Check the DT and search for the on-board devices run-time. If the
nodes are not found in DT, then disable the code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This file calls readl(), so needs to include <linux/io.h>.
Currently, it relies on someone else including it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now that 64-bit SoCs of this SoC family no longer support SPL,
this Makefile can be slightly simpler.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The .boot_device_fixup() is only called by SPL.
Now that 64-bit SoCs of this SoC family no longer support SPL,
debug-uart-ld20.c is never compiled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[ Linux commit aa38571246c6ac279ebebd141157297bcb959d76 ]
The memory regions specified by /memreserve/ are passed to
early_init_dt_reserve_memory_arch() with nomap=false, so it is
not suitable for reserving memory for Trusted Firmware-A etc.
Use the more robust /reserved-memory node with the no-map property
to prevent the kernel from mapping it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.
The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.
Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.
With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.
I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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Merge tag 'u-boot-atmel-2019.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features and fixes for 2019.10 cycle
This includes the Atmel QSPI driver and support for the at91 boards.
This is the port of the driver from Linux, mostly done by Tudor Ambarus.
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus@microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
- add support for unique generated MAC adresses from SoC serial,
limited to Amlogic GXL/GXM boards for now
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Merge tag 'u-boot-amlogic-20190704' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- fix khadas-vim README
- add support for unique generated MAC adresses from SoC serial,
limited to Amlogic GXL/GXM boards for now
The watchdog of mediatek chips is enabled by bootrom before u-boot is
running. Previously we choose to enable the wdt driver only to disable the
watchdog hardware.
Now wdt service is enabled by default. The function arch_misc_init which is
only used to disable wdt is no longer needed.
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
With commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.
Unfortunately adding CONFIG_SYS_MALLOC_CLEAR_ON_INIT also did not fix
this issue. With v2019.07-rc3 it shows again. The time of accessing
the data seems to be very important here. It needs to be "very late"
in the boot process.
Testing has shown, that copying a 64KiB area in DDR at a very late
bootup time, directly before calling into the prompt, fixes this issue.
Flushing of the complete d-cache does not seem to necessary, as this
copy alone seems to fix this problem.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This uclass is intended for devices that do not need any features from the
uclass, including binding children.
This will typically be used by devices that are used to bind child devices
but do not use dm_scan_fdt_dev() to do it. That is for example the case of
several USB wrappers that have 2 child devices (1 for device and 1 for
host) but bind only one at a any given time.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit b238e4b00c ("rockchip: Cleanup of make_fit_atf.py.") set
firmware = "atf_1";
loadables = "uboot","atf_1","atf_2";
Actually it should be:
firmware = "atf_1";
loadables = "uboot","atf_2","atf_3";
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for generating an unique MAC address using the SoC internal
serial number from the Secure Monitor interface.
The algorithm generates an unicast locally administered 6bytes minus 2bits
address using an crc16 of the serial for the top 16bits with the lower 2 bits
masked to setup the unicast locally administered property and a crc24 for
the lower 24bits.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Secure Monitor interface permits retrieving the SoC Serial Number,
add a function to retrieve it.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
After the transition to DM, only the mx6dl/solo wandboard
is supported.
Add FIT image support so that all the wandboard variants
can be supported, like it was prior to the DM conversion.
Successfully booted Linux on mx6q/solo/qp wandboards.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Place dtbs under SoC level rather than board level.
imx6q-novena.dtb and imx6dl-wandboard-revb1.dtb were
placed under the board config option, so move them
to SoC level.
This also aligns with the kernel dts Makefile format.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
rockchip pinctrl driver has update to use dts, so we need
to add the pinctrl config in SPL for sdmmc.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Migrate all the "u-boot,dm-pre-reloc" tag from rk3288-tinker.dts
into rk3288-tinker-u-boot.dtsi.
When both board level and soc level '-u-boot.dtsi' files exist,
we need to include the soc level 'rk3288-u-boot.dtsi' manually.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
TPL is at SRAM while other stage is at SDRAM, so it needs
separate STACK.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
More boards other than vyasa needs TPL, so enable the TPL configs
at chip level instead of board level.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Move the sg_set_pinsel macro to arch/arm/mach-uniphier/arm32/debug_ll.S
since it is not used anywhere else.
Move the C functions sg_set_{pinsel,iectrl} to debug-uart.c since they
are not used anywhere else.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
debug_uart_init() is called from spl_board_init(), which is only
compiled for SPL. For U-boot proper, _debug_uart_init() is unreachable,
so dropped by the dead code elimination.
Now that 64-bit SoCs of this SoC family no longer support SPL,
debug-uart-ld20.c is never compiled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This file calls readl(), so needs to include <linux/io.h>.
Currently, it relies on someone else including it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The MPU region dedicated for SDRAM for STM32F4 SoCs family
was set to 16MB, but STM32F429 Evaluation board have 32MB of SDRAM.
When kernel starts, only first 16MB of SDRAM are configured with XN
(eXecute Never) bit disabled, whereas kernel is using 32MB.
To avoid such situation in the future, extend this MPU region to 512MB
as for STM32F7/H7.
It fixes the following user land exception on STM32F429 Evaluation
board :
[ 1.713002] VFS: Mounted root (ext4 filesystem) readonly on device 179:2.
[ 1.722605] devtmpfs: mounted
[ 1.733057] Freeing unused kernel memory: 72K
[ 1.737622] This architecture does not have kernel memory protection.
[ 1.744070] Run /sbin/init as init process
[ 1.906850]
[ 1.906850] Unhandled exception: IPSR = 00000004 LR = fffffffd
[ 1.914282] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6
[ 1.921433] Hardware name: STM32 (Device Tree Support)
[ 1.926601] PC is at 0x1a00b64
[ 1.929642] LR is at (null)
[ 1.932669] pc : [<01a00b64>] lr : [<00000000>] psr: 01000000
[ 1.938993] sp : 01a5cfb0 ip : 00000000 fp : 00000000
[ 1.944269] r10: 01a43b00 r9 : 00000000 r8 : 00000000
[ 1.949564] r7 : 00000000 r6 : 00000000 r5 : 00000000 r4 : 00000000
[ 1.956168] r3 : 00000000 r2 : 00000000 r1 : 00000000 r0 : 00000000
[ 1.962701] xPSR: 01000000
[ 1.965506] CPU: 0 PID: 1 Comm: init Not tainted 5.1.0-00002-gcf9ca5719954 #6
[ 1.972658] Hardware name: STM32 (Device Tree Support)
[ 1.978132] [<0000c009>] (unwind_backtrace) from [<0000b24f>] (show_stack+0xb/0xc)
[ 1.986024] [<0000b24f>] (show_stack) from [<0000b947>] (__invalid_entry+0x4b/0x4c)
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
As in stm32f7-u-boot.dtsi these nodes already have "u-bootdm-pre-reloc"
property, no need to add them again in stm32f746-disco-u-boot.dtsi.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Import iMX53 M53Menlo device tree from Linux next-20190607 3f310e51ceb1 .
Enable DT control in full U-Boot . Add U-Boot extras into separate DTSi,
the GPIO controllers need to be inited early, otherwise m53_set_clock()
won't be able to detect the correct CPU clock frequency by reading the
GPIO.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Synchronize iMX53 device tree from Linux next-20190607 3f310e51ceb1 ,
this is needed to get NFC, UART, USBOTG DT nodes.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
According to hab.c code we have to notify the ROM code if the MMU is
enabled or not. This is achieved by setting the "pu_irom_mmu_enabled"
to 0x1.
The current address in hab.c code is wrong for i.MX6SL, according to ROM
map file the correct address is 0x00901c60.
As we are writing in the wrong address the ROM code is not flushing the
caches when needed, and the following HAB event is observed in certain
scenarios:
--------- HAB Event 1 -----------------
event data:
0xdb 0x00 0x14 0x41 0x33 0x18 0xc0 0x00
0xca 0x00 0x0c 0x00 0x01 0xc5 0x00 0x00
0x00 0x00 0x07 0xe4
STS = HAB_FAILURE (0x33)
RSN = HAB_INV_SIGNATURE (0x18)
CTX = HAB_CTX_COMMAND (0xC0)
ENG = HAB_ENG_ANY (0x00)
Update MX6SL_PU_IROM_MMU_EN_VAR to address this issue.
Reported-by: Frank Zhang <frank.zhang@nxp.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Enable TPL_BOARD_INIT, this would help us to show
TPL boot prints.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now, we have spl_board_init which has TPL banner prints.
So mark the 'U-Boot TPL board init' print into debug.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add spl_board_init for TPL, that have TPL banner will help
to print tpl boot prints.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable SPL_BOARD_INIT globally to rk3399, this would
help to print the SPL banner during bootup.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
u-boot,dm-pre-reloc for uart0, uart2 indeed u-boot specific
properties. Move them into rk3399-u-boot.dtsi so the boards
which enabled these node will available during SPL.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Now, we have spl_board_init with preloader_console_init that
indeed show SPL banner.
So mark the 'U-Boot SPL board init' print into debug.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Support common spl_board_init by moving code from puma
board file into, common rk3399-board-spl.c.
Part of the code has sysreset-gpio, regulators_enable_boot_on
but right now only puma board is using this with relevant
config options rest remains common for all targets.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Right now rockchip platform need to copy bl31.elf into u-boot
source directory to make use of building u-boot.itb.
So, add environment variable BL31 like Allwinner SoC so-that the
bl31.elf would available via BL31.
If the builds are not exporting BL31 env, the make_fit_atf.py
explicitly create dummy bl31.elf in u-boot root directory to
satisfy travis builds and it will show the warning on console as
WARNING: BL31 file bl31.elf NOT found, resulting binary is non-functional
WARNING: Please read Building section in doc/README.rockchip
Note, that the dummy bl31 files were created during not exporting
BL31 case would be removed via clean target in Makefile.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
rk3328-rock64.dts has been taken from Linux kernel commit
cff6d1d6f88b ("arm64: dts: rockchip: enable HS200 for eMMC on rock64")
with minor modifications (drop nodes not known by rk3328.dtsi).
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable SPL support and some related option in Kconfig.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 430b01462b with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
rk3328 SPL is locate at dram, so do not have strict size limit,
suppose to enable storage media controller driver, load ATF and
U-Boot, then boot into ATF.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
[cherry picked from 4ebe3968b6 with minor modifications]
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Converted to use fsl_esdhc_imx for i.MX platforms.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Tested-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Jason Liu <Jason.hui.liu@nxp.com>
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.
Reverts commit 665cb18ea6 for now
till better solution will be proposed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
