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u-boot-brain
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rockchip: dts: rk3288: move reloc tag into -u-boot dts 

Move all the tag "u-boot,dm-pre-reloc" from rk3288.dtsi
into rk3288-u-boot.dtsi.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-07-01 11:49:10 +08:00
parent 45290847df
commit 590dc42620
4 changed files with 40 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
arch/arm/dts/rk3288-u-boot.dtsi Normal file
View File

@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Rockchip Electronics Co., Ltd
*/
&dmc {
u-boot,dm-pre-reloc;
};
&pmu {
u-boot,dm-pre-reloc;
};
&sgrf {
u-boot,dm-pre-reloc;
};
&cru {
u-boot,dm-pre-reloc;
};
&grf {
u-boot,dm-pre-reloc;
};
&vopb {
u-boot,dm-pre-reloc;
};
&vopl {
u-boot,dm-pre-reloc;
};
&noc {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2015 Google, Inc
*/
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6

2
arch/arm/dts/rk3288-vyasa-u-boot.dtsi
View File

@ -3,6 +3,8 @@
* Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
*/
#include "rk3288-u-boot.dtsi"
&dmc {
rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7

8
arch/arm/dts/rk3288.dtsi
View File

@ -468,7 +468,6 @@
};
dmc: dmc@ff610000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
@ -584,13 +583,11 @@
};
pmu: power-management@ff730000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
};
sgrf: syscon@ff740000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-sgrf", "syscon";
reg = <0xff740000 0x1000>;
};
@ -599,7 +596,6 @@
compatible = "rockchip,rk3288-cru";
reg = <0xff760000 0x1000>;
rockchip,grf = <&grf>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
@ -615,7 +611,6 @@
};
grf: syscon@ff770000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-grf", "syscon";
reg = <0xff770000 0x1000>;
};
@ -660,7 +655,6 @@
};
vopb: vop@ff930000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-vop";
reg = <0xff930000 0x19c>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@ -715,7 +709,6 @@
iommus = <&vopl_mmu>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
u-boot,dm-pre-reloc;
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
@ -911,7 +904,6 @@
};
noc: syscon@ffac0000 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac0000 0x2000>;
};