mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Fixes for 2019.07
- menlo board - allow SDB on Sabre - HAB for mx6sl - apalis board -----BEGIN PGP SIGNATURE----- iQHDBAABCgAtFiEEiZClFGvhzbUNsmAvKMTY0yrV63cFAl0VwBcPHHNiYWJpY0Bk ZW54LmRlAAoJECjE2NMq1et3k4AL/iaMEhY5e43krMSmlnWDfS2DsTVpyUBX1Q7X JHkuKQ8iH3bBSquwLNFju2hGNK8whCHfsIB5QgSh4uK3JIzWAh+/5TCGXbPDkGMJ PI/hyxKy2EB245SMshcJMHbyLK6PeHi4V/WA4WyY2c91Dz/DNx7UhMZOlFm8wyMl TwDCwtlqHodz0tXKUziCjSqTfxj7WSThwuyQ0SEHAccglM1MzM1JHq1RcdV7Pjdh bDpMC0rjcxYl5MM7gIig5OMtx+26HgP6JM+QfeoEuBm0PbhxV6ZFyHlafb8W/ba0 SjzMWIknZWYA9GTAkdUgN+E0ChZVID0oSVoVh51eKiOG1z+LpkJEKE7xsaCAeBiQ BupLRgd0tBtqVK345EFDCy5UkYrnkLOnI+3JQNZ9bxBoPmKAf6wvhqa9Jf3bc+rP iSYh9Lm3sWVlXKcLR4ltS39D48OT8GZqun8zLpZkwpAWxRMuFvR+R7Q+VMVKmEF2 1dn3EJhMsvbmTj0lYRp+ObEEpJDL9A== =DFoX -----END PGP SIGNATURE----- Merge tag 'u-boot-imx-20190628' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2019.07 - menlo board - allow SDB on Sabre - HAB for mx6sl - apalis board
This commit is contained in:
Tom Rini
commit
0352e878d2
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@ -537,7 +537,8 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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vf610-bk4r1.dtb
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dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
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imx53-kp.dtb
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imx53-kp.dtb \
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imx53-m53menlo.dtb
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dtb-$(CONFIG_MX6Q) += \
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imx6-apalis.dtb \
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132
arch/arm/dts/imx53-m53.dtsi
Normal file
132
arch/arm/dts/imx53-m53.dtsi
Normal file
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2014 Marek Vasut <marex@denx.de>
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*/
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#include "imx53.dtsi"
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/ {
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model = "Aries/DENX M53";
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compatible = "aries,imx53-m53", "denx,imx53-m53", "fsl,imx53";
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memory@70000000 {
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device_type = "memory";
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reg = <0x70000000 0x20000000>,
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<0xb0000000 0x20000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3p2v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3P2V";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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regulator-always-on;
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};
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reg_backlight: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "lcd-supply";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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regulator-always-on;
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};
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};
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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clock-frequency = <400000>;
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status = "okay";
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touchscreen@41 {
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compatible = "st,stmpe610";
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reg = <0x41>;
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id = <0>;
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blocks = <0x5>;
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interrupts = <6 0x0>;
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interrupt-parent = <&gpio7>;
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irq-trigger = <0x1>;
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stmpe_touchscreen {
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compatible = "st,stmpe-ts";
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st,sample-time = <4>;
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st,mod-12b = <1>;
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st,ref-sel = <0>;
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st,adc-freq = <1>;
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st,ave-ctrl = <3>;
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st,touch-det-delay = <3>;
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st,settling = <4>;
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st,fraction-z = <7>;
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st,i-drive = <1>;
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};
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};
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eeprom: eeprom@50 {
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compatible = "atmel,24c128";
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reg = <0x50>;
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pagesize = <32>;
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};
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rtc: rtc@68 {
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compatible = "st,m41t62";
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reg = <0x68>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-m53evk {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
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MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
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MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_nand: nandgrp {
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fsl,pins = <
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MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
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MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
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MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
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MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
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MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
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MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
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MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
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MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
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MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
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MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
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MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
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MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
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MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
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MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
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MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
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>;
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};
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};
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nand>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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status = "okay";
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};
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42
arch/arm/dts/imx53-m53menlo-u-boot.dtsi
Normal file
42
arch/arm/dts/imx53-m53menlo-u-boot.dtsi
Normal file
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@ -0,0 +1,42 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marek Vasut <marex@denx.de>
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*/
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/ {
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soc {
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u-boot,dm-pre-reloc;
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aips@50000000 {
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u-boot,dm-pre-reloc;
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};
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};
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};
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&gpio1 {
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u-boot,dm-pre-reloc;
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};
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&gpio2 {
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u-boot,dm-pre-reloc;
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};
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&gpio3 {
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u-boot,dm-pre-reloc;
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};
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&gpio4 {
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u-boot,dm-pre-reloc;
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};
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&gpio5 {
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u-boot,dm-pre-reloc;
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};
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&gpio6 {
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u-boot,dm-pre-reloc;
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};
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&gpio7 {
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u-boot,dm-pre-reloc;
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};
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312
arch/arm/dts/imx53-m53menlo.dts
Normal file
312
arch/arm/dts/imx53-m53menlo.dts
Normal file
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@ -0,0 +1,312 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2019 Marek Vasut <marex@denx.de>
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*/
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/dts-v1/;
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#include "imx53-m53.dtsi"
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#include "imx53-m53menlo-u-boot.dtsi"
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/ {
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model = "MENLO M53 EMBEDDED DEVICE";
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compatible = "menlo,m53menlo", "fsl,imx53";
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_led>;
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user1 {
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label = "TestLed601";
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gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc0";
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};
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user2 {
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label = "TestLed602";
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gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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eth {
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label = "EthLedYe";
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gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "none";
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};
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};
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panel {
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compatible = "edt,etm070080dh6";
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enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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};
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reg_usbh1_vbus: regulator-usbh1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can2>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>,
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<&clks IMX5_CLK_CKO1_PODF>,
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<&clks IMX5_CLK_CKO1>;
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assigned-clock-parents = <&clks IMX5_CLK_AHB>;
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assigned-clock-rates = <133333334>, <33333334>, <33333334>;
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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touchscreen@38 {
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compatible = "edt,edt-ft5x06";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_edt_ft5x06>;
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interrupt-parent = <&gpio6>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
|
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wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
|
||||
};
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|
||||
eeprom@50 {
|
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compatible = "atmel,24c64";
|
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reg = <0x50>;
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||||
pagesize = <32>;
|
||||
};
|
||||
|
||||
dac@60 {
|
||||
compatible = "microchip,mcp4725";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
touchscreen@41 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
imx53-m53evk {
|
||||
hoggrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
|
||||
MX53_PAD_EIM_EB3__GPIO2_31 0x1d5
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5
|
||||
MX53_PAD_GPIO_19__CCM_CLKO 0x1d5
|
||||
MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5
|
||||
MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5
|
||||
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5
|
||||
MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5
|
||||
MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5
|
||||
MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5
|
||||
MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5
|
||||
MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5
|
||||
MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5
|
||||
MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_led: ledgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5
|
||||
MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can1: can1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4
|
||||
MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_can2: can2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4
|
||||
MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_display_gpio: display-gpiogrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */
|
||||
MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_edt_ft5x06: edt-ft5x06grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */
|
||||
MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */
|
||||
MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esdhc1: esdhc1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
|
||||
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
|
||||
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
|
||||
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
|
||||
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
|
||||
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_FEC_MDC__FEC_MDC 0x4
|
||||
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
|
||||
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
|
||||
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
|
||||
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
|
||||
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
|
||||
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
|
||||
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
|
||||
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
|
||||
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4
|
||||
MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4
|
||||
MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds0: lvds0grp {
|
||||
/* LVDS pins only have pin mux configuration */
|
||||
fsl,pins = <
|
||||
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
|
||||
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
|
||||
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
|
||||
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
|
||||
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
|
||||
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb: usbgrp {
|
||||
fsl,pins = <
|
||||
MX53_PAD_GPIO_2__GPIO1_2 0x1d5
|
||||
MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lvds0>;
|
||||
status = "okay";
|
||||
|
||||
lvds0: lvds-channel@0 {
|
||||
reg = <0>;
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb>;
|
||||
vbus-supply = <®_usbh1_vbus>;
|
||||
phy_type = "utmi";
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,17 +1,8 @@
|
|||
/*
|
||||
* Copyright 2016 Beckhoff Automation
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Copyright 2011 Linaro Ltd.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
//
|
||||
// Copyright 2011 Freescale Semiconductor, Inc.
|
||||
// Copyright 2011 Linaro Ltd.
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include "imx53-pinfunc.h"
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
|
@ -19,8 +10,17 @@
|
|||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
/*
|
||||
* The decompressor and also some bootloaders rely on a
|
||||
* pre-existing /chosen node to be available to insert the
|
||||
* command line and merge other ATAGS info.
|
||||
*/
|
||||
chosen {};
|
||||
|
||||
aliases {
|
||||
serial1 = &uart2;
|
||||
ethernet0 = &fec;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
|
|
@ -36,7 +36,45 @@
|
|||
mmc1 = &esdhc2;
|
||||
mmc2 = &esdhc3;
|
||||
mmc3 = &esdhc4;
|
||||
usb1 = &usbh1;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &cspi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
clocks = <&clks IMX5_CLK_ARM>;
|
||||
clock-latency = <61036>;
|
||||
voltage-tolerance = <5>;
|
||||
operating-points = <
|
||||
/* kHz */
|
||||
166666 850000
|
||||
400000 900000
|
||||
800000 1050000
|
||||
1000000 1200000
|
||||
1200000 1300000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
display-subsystem {
|
||||
compatible = "fsl,imx-display-subsystem";
|
||||
ports = <&ipu_di0>, <&ipu_di1>;
|
||||
};
|
||||
|
||||
capture_subsystem {
|
||||
compatible = "fsl,imx-capture-subsystem";
|
||||
ports = <&ipu_csi0>, <&ipu_csi1>;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@fffc000 {
|
||||
|
|
@ -46,13 +84,143 @@
|
|||
reg = <0x0fffc000 0x4000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupt-parent = <&tzic>;
|
||||
interrupts = <77>;
|
||||
};
|
||||
|
||||
usbphy0: usbphy-0 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
|
||||
clock-names = "main_clk";
|
||||
#phy-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy-1 {
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
|
||||
clock-names = "main_clk";
|
||||
#phy-cells = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&tzic>;
|
||||
ranges;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
sata: sata@10000000 {
|
||||
compatible = "fsl,imx53-ahci";
|
||||
reg = <0x10000000 0x1000>;
|
||||
interrupts = <28>;
|
||||
clocks = <&clks IMX5_CLK_SATA_GATE>,
|
||||
<&clks IMX5_CLK_SATA_REF>,
|
||||
<&clks IMX5_CLK_AHB>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipu: ipu@18000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x08000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
|
||||
ipu_csi0: port@0 {
|
||||
reg = <0>;
|
||||
|
||||
ipu_csi0_from_parallel_sensor: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
ipu_csi1: port@1 {
|
||||
reg = <1>;
|
||||
|
||||
ipu_csi1_from_parallel_sensor: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
ipu_di0: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu_di0_disp0: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di0_lvds0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_di1: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu_di1_disp1: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di1_lvds1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds1_in>;
|
||||
};
|
||||
|
||||
ipu_di1_tve: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tve_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@30000000 {
|
||||
compatible = "amd,imageon-200.0", "amd,imageon";
|
||||
reg = <0x30000000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <12>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
|
||||
clock-names = "core_clk", "mem_iface_clk";
|
||||
};
|
||||
|
||||
aips@50000000 { /* AIPS1 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
|
|
@ -92,6 +260,47 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@5000c000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x5000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART3_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: spi@50010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x50010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi2: ssi@50014000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx53-ssi",
|
||||
"fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_SSI2_ROOT_GATE>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc3: esdhc@50020000 {
|
||||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50020000 0x4000>;
|
||||
|
|
@ -117,25 +326,18 @@
|
|||
};
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
aipstz1: bridge@53f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x53f00000 0x60>;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-gpr", "syscon";
|
||||
reg = <0x53fa8000 0xc>;
|
||||
};
|
||||
|
||||
uart2: serial@53fc0000 {
|
||||
compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
usbotg: usb@53f80000 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80000 0x0200>;
|
||||
interrupts = <18>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 0>;
|
||||
fsl,usbphy = <&usbphy0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -144,15 +346,37 @@
|
|||
reg = <0x53f80200 0x0200>;
|
||||
interrupts = <14>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 1>;
|
||||
fsl,usbphy = <&usbphy1>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
usbh2: usb@53f80400 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80400 0x0200>;
|
||||
interrupts = <16>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 2>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbh3: usb@53f80600 {
|
||||
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
|
||||
reg = <0x53f80600 0x0200>;
|
||||
interrupts = <17>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
fsl,usbmisc = <&usbmisc 3>;
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbmisc: usbmisc@53f80800 {
|
||||
#index-cells = <1>;
|
||||
compatible = "fsl,imx53-usbmisc";
|
||||
reg = <0x53f80800 0x200>;
|
||||
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
|
||||
};
|
||||
|
||||
gpio1: gpio@53f84000 {
|
||||
|
|
@ -195,177 +419,56 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
interrupts = <103 104>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@53fe0000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe0000 0x4000>;
|
||||
interrupts = <105 106>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@53fe4000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe4000 0x4000>;
|
||||
interrupts = <107 108>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2c3: i2c@53fec000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
sdma: sdma@63fb0000 {
|
||||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||
<&clks IMX5_CLK_SDMA_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
fec: ethernet@63fec000 {
|
||||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
kpp: kpp@53f94000 {
|
||||
compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x53f94000 0x4000>;
|
||||
interrupts = <60>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@63fc4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
||||
wdog1: wdog@53f98000 {
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
wdog2: wdog@53f9c000 {
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks IMX5_CLK_DUMMY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@63fc8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ipu: ipu@18000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ipu";
|
||||
reg = <0x18000000 0x08000000>;
|
||||
interrupts = <11 10>;
|
||||
clocks = <&clks IMX5_CLK_IPU_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI0_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_GATE>;
|
||||
clock-names = "bus", "di0", "di1";
|
||||
resets = <&src 2>;
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
ipu_csi0: port@0 {
|
||||
reg = <0>;
|
||||
gpt: timer@53fa0000 {
|
||||
compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x53fa0000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
|
||||
<&clks IMX5_CLK_GPT_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
ipu_csi1: port@1 {
|
||||
reg = <1>;
|
||||
srtc: rtc@53fa4000 {
|
||||
compatible = "fsl,imx53-rtc";
|
||||
reg = <0x53fa4000 0x4000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks IMX5_CLK_SRTC_GATE>;
|
||||
};
|
||||
|
||||
ipu_di0: port@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
ipu_di0_disp0: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di0_lvds0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
iomuxc: iomuxc@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc";
|
||||
reg = <0x53fa8000 0x4000>;
|
||||
};
|
||||
|
||||
ipu_di1: port@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
ipu_di1_disp1: endpoint@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
ipu_di1_lvds1: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&lvds1_in>;
|
||||
};
|
||||
|
||||
ipu_di1_tve: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint = <&tve_in>;
|
||||
};
|
||||
gpr: iomuxc-gpr@53fa8000 {
|
||||
compatible = "fsl,imx53-iomuxc-gpr", "syscon";
|
||||
reg = <0x53fa8000 0xc>;
|
||||
};
|
||||
};
|
||||
|
||||
tve: tve@63ff0000 {
|
||||
compatible = "fsl,imx53-tve";
|
||||
reg = <0x63ff0000 0x1000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
||||
clock-names = "tve", "di_sel";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
tve_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_tve>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
src: src@53fd0000 {
|
||||
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
||||
reg = <0x53fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
ldb: ldb@53fa8008 {
|
||||
ldb: ldb@53fa8008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ldb";
|
||||
|
|
@ -419,6 +522,334 @@
|
|||
reg = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@53fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM1_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@53fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb8000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_PWM2_HF_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@53fc0000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@53fc8000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CAN1_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can2: can@53fcc000 {
|
||||
compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CAN2_SERIAL_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
src: src@53fd0000 {
|
||||
compatible = "fsl,imx53-src", "fsl,imx51-src";
|
||||
reg = <0x53fd0000 0x4000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
interrupts = <103 104>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio6: gpio@53fe0000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe0000 0x4000>;
|
||||
interrupts = <105 106>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio7: gpio@53fe4000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fe4000 0x4000>;
|
||||
interrupts = <107 108>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
i2c3: i2c@53fec000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clocks = <&clks IMX5_CLK_I2C3_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@53ff0000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART4_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
aips@60000000 { /* AIPS2 */
|
||||
compatible = "fsl,aips-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
aipstz2: bridge@63f00000 {
|
||||
compatible = "fsl,imx53-aipstz";
|
||||
reg = <0x63f00000 0x60>;
|
||||
};
|
||||
|
||||
iim: iim@63f98000 {
|
||||
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
||||
reg = <0x63f98000 0x4000>;
|
||||
interrupts = <69>;
|
||||
clocks = <&clks IMX5_CLK_IIM_GATE>;
|
||||
};
|
||||
|
||||
uart5: serial@63f90000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
interrupts = <86>;
|
||||
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
|
||||
<&clks IMX5_CLK_UART5_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tigerp: tigerp@63fa0000 {
|
||||
compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp";
|
||||
reg = <0x63fa0000 0x28>;
|
||||
};
|
||||
|
||||
owire: owire@63fa4000 {
|
||||
compatible = "fsl,imx53-owire", "fsl,imx21-owire";
|
||||
reg = <0x63fa4000 0x4000>;
|
||||
clocks = <&clks IMX5_CLK_OWIRE_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi2: spi@63fac000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x63fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI2_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdma: sdma@63fb0000 {
|
||||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks IMX5_CLK_SDMA_GATE>,
|
||||
<&clks IMX5_CLK_AHB>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
cspi: spi@63fc0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x63fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
|
||||
<&clks IMX5_CLK_CSPI_IPG_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@63fc4000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks IMX5_CLK_I2C2_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@63fc8000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks IMX5_CLK_I2C1_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi1: ssi@63fcc000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_SSI1_ROOT_GATE>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
audmux: audmux@63fd0000 {
|
||||
compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
|
||||
reg = <0x63fd0000 0x4000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand@63fdb000 {
|
||||
compatible = "fsl,imx53-nand";
|
||||
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks IMX5_CLK_NFC_GATE>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssi3: ssi@63fe8000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
|
||||
"fsl,imx21-ssi";
|
||||
reg = <0x63fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
|
||||
<&clks IMX5_CLK_SSI3_ROOT_GATE>;
|
||||
clock-names = "ipg", "baud";
|
||||
dmas = <&sdma 46 0 0>,
|
||||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fec: ethernet@63fec000 {
|
||||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>,
|
||||
<&clks IMX5_CLK_FEC_GATE>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tve: tve@63ff0000 {
|
||||
compatible = "fsl,imx53-tve";
|
||||
reg = <0x63ff0000 0x1000>;
|
||||
interrupts = <92>;
|
||||
clocks = <&clks IMX5_CLK_TVE_GATE>,
|
||||
<&clks IMX5_CLK_IPU_DI1_SEL>;
|
||||
clock-names = "tve", "di_sel";
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
tve_in: endpoint {
|
||||
remote-endpoint = <&ipu_di1_tve>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vpu: vpu@63ff4000 {
|
||||
compatible = "fsl,imx53-vpu", "cnm,coda7541";
|
||||
reg = <0x63ff4000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
|
||||
<&clks IMX5_CLK_VPU_GATE>;
|
||||
clock-names = "per", "ahb";
|
||||
resets = <&src 1>;
|
||||
iram = <&ocram>;
|
||||
};
|
||||
|
||||
sahara: crypto@63ff8000 {
|
||||
compatible = "fsl,imx53-sahara";
|
||||
reg = <0x63ff8000 0x4000>;
|
||||
interrupts = <19 20>;
|
||||
clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
|
||||
<&clks IMX5_CLK_SAHARA_IPG_GATE>;
|
||||
clock-names = "ipg", "ahb";
|
||||
};
|
||||
};
|
||||
|
||||
ocram: sram@f8000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xf8000000 0x20000>;
|
||||
clocks = <&clks IMX5_CLK_OCRAM>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
#define ALIGN_SIZE 0x1000
|
||||
#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
|
||||
#define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
|
||||
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
|
||||
#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60
|
||||
#define IS_HAB_ENABLED_BIT \
|
||||
(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
|
||||
(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
|
@ -28,6 +29,7 @@
|
|||
#include <spl.h>
|
||||
#include <splash.h>
|
||||
#include <usb/ehci-ci.h>
|
||||
#include <video_console.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -80,33 +82,6 @@ static void setup_iomux_uart(void)
|
|||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX5
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
if (port == 0) {
|
||||
/* USB OTG PWRON */
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_4__GPIO1_4,
|
||||
PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_HIGH));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
|
||||
|
||||
/* USB OTG Over Current */
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_18__GPIO7_13);
|
||||
} else if (port == 1) {
|
||||
/* USB Host PWRON */
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_2__GPIO1_2,
|
||||
PAD_CTL_PKE |
|
||||
PAD_CTL_DSE_HIGH));
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 2), 0);
|
||||
|
||||
/* USB Host Over Current */
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_3__USBOH3_USBH1_OC);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_fec(void)
|
||||
{
|
||||
static const iomux_v3_cfg_t fec_pads[] = {
|
||||
|
|
@ -150,44 +125,6 @@ static void setup_iomux_fec(void)
|
|||
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg esdhc_cfg = {
|
||||
MMC_SDHC1_BASE_ADDR,
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
|
||||
gpio_direction_input(IMX_GPIO_NR(1, 1));
|
||||
|
||||
return !gpio_get_value(IMX_GPIO_NR(1, 1));
|
||||
}
|
||||
|
||||
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP)
|
||||
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
|
||||
PAD_CTL_DSE_HIGH)
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
static const iomux_v3_cfg_t sd1_pads[] = {
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
|
||||
NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
|
||||
};
|
||||
|
||||
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
|
||||
|
||||
return fsl_esdhc_initialize(bis, &esdhc_cfg);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
|
||||
{
|
||||
static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
|
||||
|
|
@ -215,6 +152,8 @@ static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
|
|||
|
||||
static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
|
||||
{
|
||||
gpio_request(IMX_GPIO_NR(6, 0), "LCD");
|
||||
|
||||
/* For ETM0430G0DH6 model, this must be enabled before the clock. */
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
|
||||
|
||||
|
|
@ -227,6 +166,8 @@ static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
|
|||
|
||||
static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
|
||||
{
|
||||
gpio_request(IMX_GPIO_NR(6, 0), "LCD");
|
||||
|
||||
/*
|
||||
* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
|
||||
* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
|
||||
|
|
@ -330,7 +271,6 @@ struct display_info_t const displays[] = {
|
|||
};
|
||||
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPLASH_SCREEN
|
||||
static struct splash_location default_splash_locations[] = {
|
||||
|
|
@ -349,6 +289,50 @@ int splash_screen_prepare(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#if defined(CONFIG_VIDEO_IPUV3)
|
||||
struct udevice *dev;
|
||||
int xpos, ypos, ret;
|
||||
char *s;
|
||||
void *dst;
|
||||
ulong addr, len;
|
||||
|
||||
splash_get_pos(&xpos, &ypos);
|
||||
|
||||
s = env_get("splashimage");
|
||||
if (!s)
|
||||
return 0;
|
||||
|
||||
addr = simple_strtoul(s, NULL, 16);
|
||||
dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
|
||||
if (!dst)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = splash_screen_prepare();
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
|
||||
ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
|
||||
(uchar *)addr, &len);
|
||||
if (ret) {
|
||||
printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
|
||||
free(dst);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
|
||||
|
||||
|
|
@ -424,6 +408,8 @@ static void m53_set_clock(void)
|
|||
const u32 dramclk = 400;
|
||||
u32 cpuclk;
|
||||
|
||||
gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
|
||||
|
||||
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
|
||||
gpio_direction_input(IMX_GPIO_NR(4, 0));
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ $ make mrproper
|
|||
$ make pico-imx7d_defconfig
|
||||
$ make
|
||||
|
||||
This generates the SPL and u-boot.img binaries.
|
||||
This generates the SPL and u-boot-dtb.img binaries.
|
||||
|
||||
1. Loading U-Boot via USB Serial Download Protocol
|
||||
|
||||
|
|
@ -32,15 +32,15 @@ to use an externally powered USB hub between the board and the host computer.
|
|||
|
||||
Open a terminal program such as minicom.
|
||||
|
||||
Copy SPL and u-boot.img to the imx_usb_loader folder.
|
||||
Copy SPL and u-boot-dtb.img to the imx_usb_loader folder.
|
||||
|
||||
Load the SPL binary via USB:
|
||||
|
||||
$ sudo ./imx_usb SPL
|
||||
|
||||
Load the u-boot.img binary via USB:
|
||||
Load the u-boot-dtb.img binary via USB:
|
||||
|
||||
$ sudo ./imx_usb u-boot.img
|
||||
$ sudo ./imx_usb u-boot-dtb.img
|
||||
|
||||
Then U-Boot starts and its messages appear in the console program.
|
||||
|
||||
|
|
@ -55,11 +55,11 @@ Run the DFU agent so we can flash the new images using dfu-util tool:
|
|||
|
||||
=> dfu 0 mmc 0
|
||||
|
||||
Flash SPL and u-boot.img into the eMMC running the following commands on a PC:
|
||||
Flash SPL and u-boot-dtb.img into the eMMC running the following commands on a PC:
|
||||
|
||||
$ sudo dfu-util -D SPL -a spl
|
||||
|
||||
$ sudo dfu-util -D u-boot.img -a u-boot
|
||||
$ sudo dfu-util -D u-boot-dtb.img -a u-boot
|
||||
|
||||
Remove power from the pico board.
|
||||
|
||||
|
|
|
|||
|
|
@ -29,10 +29,14 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image,
|
|||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* This command typically does not return but jumps to an image */
|
||||
sdp_handle(controller_index);
|
||||
pr_err("SDP ended\n");
|
||||
/*
|
||||
* This command either loads a legacy image, jumps and never returns,
|
||||
* or it loads a FIT image and returns it to be handled by the SPL
|
||||
* code.
|
||||
*/
|
||||
ret = spl_sdp_handle(controller_index, spl_image);
|
||||
debug("SDP ended\n");
|
||||
|
||||
return -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD("USB SDP", 0, BOOT_DEVICE_BOARD, spl_sdp_load_image);
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x71000000
|
|||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x8000
|
||||
CONFIG_TARGET_M53MENLO=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
|
|
@ -17,9 +18,8 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/menlo/m53menlo/imximage.cfg"
|
|||
CONFIG_BOOTDELAY=1
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttymxc0,115200"
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_TEXT_BASE=0x70008000
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
|
|
@ -27,11 +27,14 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
|
|||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_DM=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND_TRIMFFS=y
|
||||
# CONFIG_CMD_PINMUX is not set
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
|
|
@ -48,27 +51,37 @@ CONFIG_CMD_MTDPARTS=y
|
|||
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:1m(u-boot),512k(env1),512k(env2),-(ubi)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx53-m53menlo"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_BOOTCOUNT_LIMIT=y
|
||||
CONFIG_BOOTCOUNT_BOOTLIMIT=3
|
||||
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_NAND=y
|
||||
CONFIG_NAND_MXC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX5=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_RTC_M41T62=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_MX5=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_DM_VIDEO=y
|
||||
CONFIG_SYS_WHITE_ON_BLACK=y
|
||||
CONFIG_VIDEO_IPUV3=y
|
||||
CONFIG_VIDEO=y
|
||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
|
|||
|
|
@ -638,7 +638,20 @@ static u32 sdp_jump_imxheader(void *address)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void sdp_handle_in_ep(void)
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
static ulong sdp_fit_read(struct spl_load_info *load, ulong sector,
|
||||
ulong count, void *buf)
|
||||
{
|
||||
debug("%s: sector %lx, count %lx, buf %lx\n",
|
||||
__func__, sector, count, (ulong)buf);
|
||||
memcpy(buf, (void *)(load->dev + sector), count);
|
||||
return count;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static void sdp_handle_in_ep(struct spl_image_info *spl_image)
|
||||
{
|
||||
u8 *data = sdp_func->in_req->buf;
|
||||
u32 status;
|
||||
|
|
@ -690,10 +703,25 @@ static void sdp_handle_in_ep(void)
|
|||
/* If imx header fails, try some U-Boot specific headers */
|
||||
if (status) {
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
image_header_t *header =
|
||||
sdp_ptr(sdp_func->jmp_address);
|
||||
#ifdef CONFIG_SPL_LOAD_FIT
|
||||
if (image_get_magic(header) == FDT_MAGIC) {
|
||||
struct spl_load_info load;
|
||||
|
||||
debug("Found FIT\n");
|
||||
load.dev = header;
|
||||
load.bl_len = 1;
|
||||
load.read = sdp_fit_read;
|
||||
spl_load_simple_fit(spl_image, &load, 0,
|
||||
header);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
/* In SPL, allow jumps to U-Boot images */
|
||||
struct spl_image_info spl_image = {};
|
||||
spl_parse_image_header(&spl_image,
|
||||
(struct image_header *)sdp_func->jmp_address);
|
||||
spl_parse_image_header(&spl_image, header);
|
||||
jump_to_image_no_args(&spl_image);
|
||||
#else
|
||||
/* In U-Boot, allow jumps to scripts */
|
||||
|
|
@ -715,19 +743,32 @@ static void sdp_handle_in_ep(void)
|
|||
};
|
||||
}
|
||||
|
||||
void sdp_handle(int controller_index)
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
int sdp_handle(int controller_index)
|
||||
#else
|
||||
int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image)
|
||||
#endif
|
||||
{
|
||||
printf("SDP: handle requests...\n");
|
||||
while (1) {
|
||||
if (ctrlc()) {
|
||||
puts("\rCTRL+C - Operation aborted.\n");
|
||||
return;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
if (spl_image->flags & SPL_FIT_FOUND)
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
WATCHDOG_RESET();
|
||||
usb_gadget_handle_interrupts(controller_index);
|
||||
|
||||
sdp_handle_in_ep();
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
sdp_handle_in_ep(spl_image);
|
||||
#else
|
||||
sdp_handle_in_ep(NULL);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@
|
|||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */
|
||||
#define CONFIG_FEC_MXC_PHYADDR 6
|
||||
#define CONFIG_TFTP_TSIZE
|
||||
|
||||
|
|
@ -121,8 +122,8 @@
|
|||
"imx6q-apalis-cam-eval.dtb fat 0 1"
|
||||
|
||||
#define EMMC_BOOTCMD \
|
||||
"set_emmcargs emmcargs ip=off root=PARTUUID=${uuid} ro,noatime " \
|
||||
"rootfstype=ext4 rootwait\0" \
|
||||
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \
|
||||
"ro,noatime rootfstype=ext4 rootwait\0" \
|
||||
"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
|
||||
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
|
||||
"${vidargs}; echo Booting from internal eMMC chip...; " \
|
||||
|
|
|
|||
|
|
@ -136,7 +136,6 @@
|
|||
/*
|
||||
* LCD
|
||||
*/
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
|
@ -145,7 +144,6 @@
|
|||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
|
||||
#endif
|
||||
|
||||
/* LVDS display */
|
||||
#define CONFIG_SYS_LDB_CLOCK 33260000
|
||||
|
|
@ -205,6 +203,8 @@
|
|||
"splashfile=boot/usplash.bmp.gz\0" \
|
||||
"splashimage=0x88000000\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0" \
|
||||
"addcons=" \
|
||||
"setenv bootargs ${bootargs} " \
|
||||
"console=${consdev},${baudrate}\0" \
|
||||
|
|
|
|||
|
|
@ -79,7 +79,6 @@
|
|||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"splashpos=m,m\0" \
|
||||
"console=ttymxc4\0" \
|
||||
|
|
|
|||
|
|
@ -10,6 +10,13 @@
|
|||
#define __SDP_H_
|
||||
|
||||
int sdp_init(int controller_index);
|
||||
void sdp_handle(int controller_index);
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <spl.h>
|
||||
|
||||
int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image);
|
||||
#else
|
||||
int sdp_handle(int controller_index);
|
||||
#endif
|
||||
|
||||
#endif /* __SDP_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user