u-boot-brain/arch
Masahiro Yamada 382de4a7e9 arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET
By default, CONFIG_SYS_INIT_SP_BSS_OFFSET was made invisible by not
giving a prompt to it.

The only way to define it is to hard-code an extra entry in SoC/board
Kconfig, like arch/arm/mach-tegra/tegra{186,210}/Kconfig.

Add a prompt to it in order to allow defconfig files to specify the
value of CONFIG_SYS_INIT_SP_BSS_OFFSET.

With this, CONFIG_SYS_INIT_SP_BSS_OFFSET would become always visible.
So, we need a new bool option to turn it off by default.

I move the 'default 524288' to the common place. This value is not too
big, but is big enough to avoid the overwrap of DT in most platforms.
If 512KB is not a suitable choice for your platform, you can change it
from your defconfig or menuconfig etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2019-07-10 22:37:23 +09:00
..
arc CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
arm arm64: add an option to switch visibility of CONFIG_SYS_INIT_SP_BSS_OFFSET 2019-07-10 22:37:23 +09:00
m68k Convert to use fsl_esdhc_imx for i.MX platforms 2019-06-23 14:18:34 +08:00
microblaze spl: fix linker size check off-by-one errors 2019-05-05 08:48:50 -04:00
mips mips: mt76xx: Implement new d-cache fix in last_stage_init() 2019-07-05 17:12:27 +02:00
nds32 CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
nios2 .gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore 2018-06-18 14:43:12 -04:00
powerpc t2080: dts: Added PCIe DT nodes 2019-06-20 10:44:25 +05:30
riscv riscv: Add Microchip MPFS Icicle board support 2019-06-05 13:19:24 +08:00
sandbox dm: Add a No-op uclass 2019-07-05 14:19:41 +02:00
sh sh: r0p7734: Remove the board 2019-06-14 12:42:06 +02:00
x86 watchdog: tangier: Convert to use WDT class 2019-06-22 22:27:13 +08:00
xtensa CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
.gitignore
Kconfig Kconfig: Add SPI / SPI_FLASH as dependencies 2019-06-13 12:51:06 +05:30