riscv: Add Microchip MPFS Icicle board support

This patch adds Microchip MPFS Icicle board support.
For now, NS16550 serial driver is only enabled.
The Microchip MPFS Icicle defconfig by default builds
U-Boot for M-Mode with SMP support.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
This commit is contained in:
Padmarao Begari 2019-05-28 15:47:51 +05:30 committed by Andes
parent e64db0d92e
commit 39494822e3
7 changed files with 145 additions and 0 deletions

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@ -11,6 +11,9 @@ choice
config TARGET_AX25_AE350
bool "Support ax25-ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
@ -48,6 +51,7 @@ config SPL_SYS_DCACHE_OFF
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
# platform-specific options below

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@ -0,0 +1,26 @@
if TARGET_MICROCHIP_ICICLE
config SYS_BOARD
default "mpfs_icicle"
config SYS_VENDOR
default "microchip"
config SYS_CPU
default "generic"
config SYS_CONFIG_NAME
default "microchip_mpfs_icicle"
config SYS_TEXT_BASE
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
imply SMP
imply SYS_NS16550
endif

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@ -0,0 +1,7 @@
Microchip MPFS icicle
M: Padmarao Begari <padmarao.begari@microchip.com>
M: Cyril Jean <cyril.jean@microchip.com>
S: Maintained
F: board/microchip/mpfs_icicle/
F: include/configs/microchip_mpfs_icicle.h
F: configs/microchip_mpfs_icicle_defconfig

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@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2019 Microchip Technology Inc.
# Padmarao Begari <padmarao.begari@microchip.com>
#
obj-y += mpfs_icicle.o

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@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/io.h>
#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
int board_init(void)
{
/* For now nothing to do here. */
return 0;
}
int board_early_init_f(void)
{
unsigned int val;
/* Reset uart peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
val = (val & ~(1u << 5u));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}

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@ -0,0 +1,8 @@
CONFIG_RISCV=y
CONFIG_ARCH_RV64I=y
CONFIG_NR_CPUS=5
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_PROMPT="RISC-V # "
CONFIG_FIT=y
CONFIG_OF_PRIOR_STAGE=y

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@ -0,0 +1,63 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019 Microchip Technology Inc.
* Padmarao Begari <padmarao.begari@microchip.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* CPU and Board Configuration Options
*/
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/*
* Print Buffer Size
*/
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/*
* max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Boot Argument Buffer Size
*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* Size of malloc() pool
* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough
*/
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* Physical Memory Map
*/
#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
/* Init Stack Pointer */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000)
#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */
/*
* memtest works on DRAM
*/
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)
/* When we use RAM as ENV */
#define CONFIG_ENV_SIZE 0x2000
#endif /* __CONFIG_H */