With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.
Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.
Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
At least on the "33MHz Pilot" board crystal is actually 33.3MHz.
This patch fixes "system time drifting" problem.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Plus modify environment to use it and remove bootfile env variable,
it is internal and CONFIG_BOOTFILE is used for these purposes.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Current DDR setup easily causes memory corruption, this patch fixes it.
Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Use available shift/mask macros to define DDR configuration.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
These defines embedded the u-boot env variables and/or the bd_t structure
in the fdt blob. The conclusion of discussion on the u-boot email list
was that embedding these in the fdt blob is not useful: there are better
ways of passing the data (in fact, the fdt blob itself replaces the
bd_t struct).
The only board that enables these is the stxxtc and they don't appear
to be used by linux.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
- insert partition for dtb blob to TQM5200B MTD layout
- set env variables dependent on the configured board
(TQM5200 or TQM5200B)
Signed-off-by: Martin Krause <martin.krause@tqs.de>
To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).
The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory),
the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ...,
PPC440EPX_GPT0_COMP5).
To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).
The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
The parallel flash on the BF537-STAMP is CFI compliant, so there is no need
for the board specific driver at all. Just use the common CFI driver.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Stop tying things to the processor that should be tied to other defines and
change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build
system to select the -mcpu option.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.
This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.
Tested with 512 byte page NAND device (32MByte) on Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
Cleanup: Remove custom flash driver for 8 bit boot-eprom and replace it with
the FLASH_CFI_LEGACY et al. config options.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
the dts file basenames were updated in linux - this helps avoid
inadvertently loading any old dtbs laying around.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
1. Make the CSB bus pipeline depth as 4, and enable
the repeat mode;
2. Raise the eTSEC emergency priority;
3. Use the highest IP blocks clock.
Signed-off-by: Dave Liu <daveliu@freescale.com>
The latter version stops when "run load" fails for whatever reasons
rendering the combination *a lot* more secure.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Adds PCI support for MPC5121
Tested with drivers/net/rtl8139.c
Support is conditional since PCI on old silicon does not work.
ads5121_PCI_config turns on PCI
In this version, condition compilation of PCI code has been moved
from ifdef in board/ads5121/pci.c to board/ads5121/Makefile as
suggested by Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by: John Rigby <jrigby@freescale.com>
The Linux commit fac8b209b1084bc85748bd54e13d00c1262b220f ("Remove
final traces of long-deprecated "ramdisk" kernel parm") makes these
changes neccessary.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Some boards (e.g. lwmon5) may use rather small watchdog intervals, so
causing it to reboot the board if U-Boot does a long busy-wait with
udelay(). Thus, for these boards we have to restart WD more
frequently.
This patch splits the busy-wait udelay() into smaller, predefined,
intervals, so that the watchdog timer may be resetted with the
configurable (CONFIG_WD_PERIOD) interval.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Adds configuration option for ATI Radeon 9200 card
support to sequoia config file. If CONFIG_VIDEO
is enabled, TEXT_BASE should be changed to 0xFFF80000.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Without an actual supported video card hooked up, enabling
the CONFIG_VIDEO by default just makes it look broken by
routing all console output to the video card. Don't.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
This is the proper fix for a missing closing brace in the function
ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com.
The ft_cpu_setup() function in mpc8641hpcn.c should have been
removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE,
but was missed. Only, the sbc8641d was nominally still using it.
It all got ripped out, and the funcality that was in ft_board_setup()
was refactored to remove the CPU portions into the new file
cpu/mpc86xx/fdt.c instead. Make sbc8641d use this now.
Based loosely on an original patch from joe.hamman@embeddedspecialties.com
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Remove the "#undef DEBUG" line from all Freescale 83xx board header files.
The inclusion of this line makes it impossible to enable debug code in
other source files, because "#define DEBUG" typically needs to be defined
before any header files are included.
Signed-off-by: Timur Tabi <timur@freescale.com>
Changes to match 5121 device tree going mainline in 2.6.25.
Change OF_SOC from "soc5121" to plain "soc".
Remove unneeded "ref-frequency" fixups.
Remove "address" enetaddr fixup.
Add bus-frequency fixup for old OF_SOC so old
kernels with old device trees will work with new
u-boot with 66MHz IPS clock
Signed-off-by: John Rigby <jrigby@freescale.com>
The default load address is SDRAM + 2MB, not SDRAM + 4MB. The latter
wouldn't have worked anyway since the board can only access 4MB of
SDRAM.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Many people run into problems when they compile a big kernel and load
the uImage at the default SDRAM + 2MB address as the kernel will
overwrite the uImage as it is being unpacked. Increase the default
load address so that we can load a 4MB kernel image without any
problems.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Somewhere during development of U-Boot-1.1.3 CONFIG_BOOTBINFUNC was
renamed into CONFIG_INIT_CRITICAL which was 04 Apr 2005 replaced
with CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT.
However CONFIG_SKIP_LOWLEVEL_INIT has oposite meaning to
CONFIG_BOOTBINFUNC, so fix configuration to reflect this fact.
I'm sending this patch 4th (!) time in hope it produces at least some
reaction.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Fix at91rm9200dk base and environment address.
This driver should only compile if CONFIG_MPC8XXX_SPI is set
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Adds the support code in cpu/mpc86xx for the new law setup code
recently created fsl_law.c, and changes the MPC8641HPCN config
to use this code.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Add support for the ATNGW100 Network Gateway reference design,
including flash, ethernet and MMC support.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Definition update and change from 16bit to 32bit
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>
This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board.
This board has an ST M25P40 4Mbit EEPROM on its SPI bus
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
- Various fixes
- Reduced rom_size from 384 to 320 kB
- Environment is now in flash
- Added POST
- Support for OF
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
- Various fixes
- Reduced rom_size from 384 to 320 kB
- Environment is now in flash
- Added POST
- Support for OF
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Now that all boards have been converted, remove old config code and the
config option for the new style.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
With serial, NE2000, IDE support. Tested in big-endian mode.
Memory size hard-coded to 128M for now, so don't play with
the -m option.
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
MPC837xERDB board support includes:
* DDR2 330MHz hardcoded (soldered on the board)
* Local Bus NOR Flash
* I2C, UART and RTC
* eTSEC RGMII (TSEC0 - RTL8211B with MII;
* TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware
* load)
Signed-off-by: Kevin Lam <kevin.lam@freescale.com>
Signed-off-by: Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Convert the board/freescale/common/Makefile to use
CONFIG_* options to select which files to conditionally
compile into the board/freescale/common library rather
than conditionally compiling entire files.
Now handles::
CONFIG_FSL_PIXIS
CONFIG_FSL_DIU_FB
CONFIG_PQ_MDS_PIB
CONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Use driver/net/uli526x.c as MPC8610HPCD default Ethernet driver.
Remove unused ethernet CONFIG_ options.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
These changes were identified by HighSmith Bill ,Mazzyar and Joseph for
DDR configuration in u-boot code. Some are related to performance, some
affect stability and some correct few basic errors in the current
configuration.
The changes have been tested and found to give better memory latency
figures on MPC8313eRDB.LMBench figures prove it.
The changes are:
- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0
(this may improve performance for application with many read
or write to open pages).
- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to
001 (activating all the CS when only one is used may cause
unwanted noise on the system)
- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on
Tras=45ns)
- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.
- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to
comply with the 3 ODT clk requirements)
- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.
- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.
- DDR_SDRAM_MODE[AL]changed from 0 to 1.
- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.
- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.
- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.
The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git
The last commit on this tree was 6775c68683
Signed-off-by: Poonam Aggrwal-b10812 <b10812@freescale.com>
Cc: Bill HighSmith <Bill.Highsmith@freescale.com>
Cc: Razzaz Mazyar <MRazzaz@freescale.com>
Cc: Josep P J <PJ.Joseph@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
