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https://github.com/brain-hackers/u-boot-brain
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ColdFire: PCI and misc updates for MCF5445x
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
This commit is contained in:
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d2b1649348
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@ -113,7 +113,6 @@ int cpu_init_r(void)
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#ifdef CONFIG_MCFTMR
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volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
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u32 oscillator = CFG_RTC_OSCILLATOR;
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rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
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rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
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@ -46,48 +46,18 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose, \
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u16 cfg_type = 0; \
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addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
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out_be32(hose->cfg_addr, addr); \
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__asm__ __volatile__("nop"); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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out_be32(hose->cfg_addr, addr & 0x7fffffff); \
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__asm__ __volatile__("nop"); \
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return 0; \
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}
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PCI_OP(read, byte, u8 *, in_8, 3)
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PCI_OP(read, word, u16 *, in_le16, 2)
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PCI_OP(read, dword, u32 *, in_le32, 0)
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PCI_OP(write, byte, u8, out_8, 3)
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PCI_OP(write, word, u16, out_le16, 2)
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PCI_OP(write, dword, u32, out_le32, 0)
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int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
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int offset, u32 * val)
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{
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u32 addr;
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u32 tmpv;
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u32 mask = 2; /* word access */
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/* Read lower 16 bits */
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addr = ((offset & 0xfc) | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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__asm__ __volatile__("nop");
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*val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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__asm__ __volatile__("nop");
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/* Read upper 16 bits */
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offset += 2;
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addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000);
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out_be32(hose->cfg_addr, addr);
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__asm__ __volatile__("nop");
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tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask)));
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out_be32(hose->cfg_addr, addr & 0x7fffffff);
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__asm__ __volatile__("nop");
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/* combine results into dword value */
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*val = (tmpv << 16) | *val;
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return 0;
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}
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void pci_mcf5445x_init(struct pci_controller *hose)
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{
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volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
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@ -95,7 +65,7 @@ void pci_mcf5445x_init(struct pci_controller *hose)
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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u32 barEn = 0;
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pciarb->acr = 0x001f001f;
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pciarb->acr = 0x001F001F;
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/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
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PCIREQ2, PCIGNT2 */
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@ -104,53 +74,58 @@ void pci_mcf5445x_init(struct pci_controller *hose)
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GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
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GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
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/* Assert reset bit */
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pci->gscr |= PCI_GSCR_PR;
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pci->tcr1 |= PCI_TCR1_P;
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/* Initiator windows */
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pci->iw0btar = CFG_PCI_MEM_PHYS;
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pci->iw1btar = CFG_PCI_IO_PHYS;
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pci->iw2btar = CFG_PCI_CFG_PHYS;
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pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
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pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
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pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
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pci->iwcr =
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PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
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PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
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pci->icr = 0;
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/* Enable bus master and mem access */
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pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M;
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pci->scr = PCI_SCR_B | PCI_SCR_M;
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/* Cache line size and master latency */
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pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF);
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pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
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pci->cr2 = 0;
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#ifdef CFG_PCI_BAR0
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pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
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pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B0E;
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barEn |= PCI_TCR2_B0E;
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#endif
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#ifdef CFG_PCI_BAR1
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pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
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pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B1E;
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barEn |= PCI_TCR2_B1E;
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#endif
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#ifdef CFG_PCI_BAR2
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pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
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pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B2E;
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barEn |= PCI_TCR2_B2E;
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#endif
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#ifdef CFG_PCI_BAR3
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pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
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pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B3E;
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barEn |= PCI_TCR2_B3E;
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#endif
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#ifdef CFG_PCI_BAR4
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pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
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pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B4E;
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barEn |= PCI_TCR2_B4E;
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#endif
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#ifdef CFG_PCI_BAR5
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pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
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pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
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barEn |= PCI_TCR1_B5E;
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barEn |= PCI_TCR2_B5E;
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#endif
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pci->tcr2 = barEn;
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@ -279,14 +279,13 @@ icache_enable:
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move.l (%a1), %d1
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move.l #0x00040100, %d0 /* Invalidate icache */
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or.l %d1, %d0
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movec %d0, %CACR
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move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */
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move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */
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movec %d0, %ACR2
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or.l #0x00088400, %d1 /* Enable bcache and icache */
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movec %d1, %CACR
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move.l #0x04088020, %d0 /* Enable bcache and icache */
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movec %d0, %CACR
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move.l #(ICACHE_STATUS), %a1
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moveq #1, %d0
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@ -298,7 +297,7 @@ icache_disable:
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move.l #(CACR_STATUS), %a1 /* read CACR Status */
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move.l (%a1), %d0
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and.l #0xFFF77BFF, %d0
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move.l #0xFFF77BFF, %d0
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or.l #0x00040100, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Invalidate icache */
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clr.l %d0
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@ -321,7 +320,7 @@ icache_invalid:
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move.l #(CACR_STATUS), %a1 /* read CACR Status */
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move.l (%a1), %d0
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or.l #0x00040100, %d0 /* Invalidate icache */
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move.l #0x00040100, %d0 /* Invalidate icache */
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movec %d0, %CACR /* Enable and invalidate cache */
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rts
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@ -330,17 +329,11 @@ dcache_enable:
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move.l #(CACR_STATUS), %a1 /* read CACR Status */
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move.l (%a1), %d1
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move.l #0x01000000, %d0
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or.l %d1, %d0
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move.l #0x01040100, %d0
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movec %d0, %CACR /* Invalidate dcache */
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move.l #(CFG_SDRAM_BASE + 0xc000), %d0
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movec %d0, %ACR0
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move.l #0, %d0
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movec %d0, %ACR1
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or.l #0x80000000, %d1 /* Enable bcache and icache */
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movec %d1, %CACR
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move.l #0x80088020, %d0 /* Enable bcache and icache */
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movec %d0, %CACR
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move.l #(DCACHE_STATUS), %a1
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moveq #1, %d0
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@ -369,7 +362,7 @@ dcache_invalid:
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move.l #(CACR_STATUS), %a1 /* read CACR Status */
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move.l (%a1), %d0
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or.l #0x01000000, %d0 /* Setup cache mask */
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move.l #0x81088020, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable and invalidate cache */
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rts
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@ -232,10 +232,10 @@
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#define CFG_NUM_IRQS (128)
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#ifdef CONFIG_PCI
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#define CFG_PCI_BAR0 CFG_SDRAM_BASE
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#define CFG_PCI_BAR4 CFG_SDRAM_BASE
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#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE)
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#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE)
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#define CFG_PCI_BAR0 (CFG_MBAR)
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#define CFG_PCI_BAR5 (CFG_SDRAM_BASE)
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#define CFG_PCI_TBATR0 (CFG_MBAR)
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#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE)
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#endif
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#endif /* CONFIG_M54455 */
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@ -1204,13 +1204,13 @@
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#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
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#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
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#define PCI_TCR1_B5E (0x00002000) /* */
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#define PCI_TCR1_B4E (0x00001000) /* */
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#define PCI_TCR1_B3E (0x00000800) /* */
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#define PCI_TCR1_B2E (0x00000400) /* */
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#define PCI_TCR1_B1E (0x00000200) /* */
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#define PCI_TCR1_B0E (0x00000100) /* */
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#define PCI_TCR1_CR (0x00000001) /* */
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#define PCI_TCR2_B5E (0x00002000) /* */
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#define PCI_TCR2_B4E (0x00001000) /* */
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#define PCI_TCR2_B3E (0x00000800) /* */
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#define PCI_TCR2_B2E (0x00000400) /* */
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#define PCI_TCR2_B1E (0x00000200) /* */
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#define PCI_TCR2_B0E (0x00000100) /* */
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#define PCI_TCR2_CR (0x00000001) /* */
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#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
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#define PCI_TBATR_EN (0x00000001) /* Enable */
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@ -176,6 +176,10 @@
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/* PCI */
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#ifdef CONFIG_CMD_PCI
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#define CONFIG_PCI 1
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#define CONFIG_PCI_PNP 1
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#define CONFIG_SKIPPCI_HOSTBRIDGE
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#define CFG_PCI_CACHE_LINE_SIZE 4
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#define CFG_PCI_MEM_BUS 0xA0000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
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@ -192,9 +196,7 @@
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/* FPGA - Spartan 2 */
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/* experiment
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#define CONFIG_FPGA
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#define CONFIG_FPGA_XILINX
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#define CONFIG_FPGA_SPARTAN3
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#define CONFIG_FPGA CFG_SPARTAN3
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#define CONFIG_FPGA_COUNT 1
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#define CFG_FPGA_PROG_FEEDBACK
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#define CFG_FPGA_CHECK_CTRLC
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@ -286,9 +288,9 @@
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
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# define CFG_ENV_SECT_SIZE 0x2000
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#else
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# define CFG_FLASH_BASE CFG_FLASH0_BASE
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# define CFG_FLASH0_BASE CFG_CS1_BASE
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# define CFG_FLASH1_BASE CFG_CS0_BASE
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# define CFG_FLASH_BASE CFG_CS0_BASE
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# define CFG_FLASH0_BASE CFG_CS0_BASE
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# define CFG_FLASH1_BASE CFG_CS1_BASE
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# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
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# define CFG_ENV_SECT_SIZE 0x20000
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#endif
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