brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-11 05:36:17 +09:00
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-avr32

Browse Source
This commit is contained in:
Wolfgang Denk 2008-02-15 00:14:26 +01:00
commit 92915741fc
9 changed files with 46 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
board/atmel/atngw100/atngw100.c
View File

@ -23,6 +23,7 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
@ -40,6 +41,8 @@ static const struct sdram_info sdram = {
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
int board_early_init_f(void)

3
board/atmel/atstk1000/atstk1000.c
View File

@ -23,6 +23,7 @@
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix2.h>
@ -40,6 +41,8 @@ static const struct sdram_info sdram = {
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)

33
board/atmel/atstk1000/flash.c
View File

@ -159,7 +159,7 @@ int __flashprog write_buff(flash_info_t *info, uchar *src,
{
unsigned long flags;
uint16_t *base, *p, *s, *end;
uint16_t word, status;
uint16_t word, status, status1;
int ret = ERR_OK;
if (addr < info->start[0]
@ -194,20 +194,33 @@ int __flashprog write_buff(flash_info_t *info, uchar *src,
sync_write_buffer();
/* Wait for completion */
status1 = readw(p);
do {
/* TODO: Timeout */
status = readw(p);
} while ((status != word) && !(status & 0x28));
status = status1;
status1 = readw(p);
} while (((status ^ status1) & 0x40) /* toggled */
&& !(status1 & 0x28)); /* error bits */
/*
* We'll need to check once again for toggle bit
* because the toggle bit may stop toggling as I/O5
* changes to "1" (ref at49bv642.pdf p9)
*/
status1 = readw(p);
status = readw(p);
if ((status ^ status1) & 0x40) {
printf("Flash write error at address 0x%p: "
"0x%02x != 0x%02x\n",
p, status,word);
ret = ERR_PROG_ERROR;
writew(0xf0, base);
readw(base);
break;
}
writew(0xf0, base);
readw(base);
if (status != word) {
printf("Flash write error at address 0x%p: 0x%02x\n",
p, status);
ret = ERR_PROG_ERROR;
break;
}
}
if (flags)

6
cpu/at32ap/hsdramc.c
View File

@ -38,6 +38,10 @@ unsigned long sdram_init(const struct sdram_info *info)
unsigned long bus_hz;
unsigned int i;
if (!info->refresh_period)
panic("ERROR: SDRAM refresh period == 0. "
"Please update the board code\n");
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
| HSDRAMC1_BF(NR, info->row_bits - 11)
| HSDRAMC1_BF(NB, info->bank_bits - 1)
@ -113,7 +117,7 @@ unsigned long sdram_init(const struct sdram_info *info)
* 15.6 us is a typical value for a burst of length one
*/
bus_hz = get_sdram_clk_rate();
hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000);
hsdramc1_writel(TR, info->refresh_period);
printf("SDRAM: %u MB at address 0x%08lx\n",
sdram_size >> 20, info->phys_addr);

3
include/asm-avr32/arch-at32ap700x/clk.h
View File

@ -75,4 +75,7 @@ static inline unsigned long get_mci_clk_rate(void)
}
#endif
/* Board code may need the SDRAM base clock as a compile-time constant */
#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
#endif /* __ASM_AVR32_ARCH_CLK_H__ */

3
include/asm-avr32/sdram.h
View File

@ -26,6 +26,9 @@ struct sdram_info {
unsigned long phys_addr;
unsigned int row_bits, col_bits, bank_bits;
unsigned int cas, twr, trc, trp, trcd, tras, txsr;
/* SDRAM refresh period in cycles */
unsigned long refresh_period;
};
extern unsigned long sdram_init(const struct sdram_info *info);

10
include/configs/atngw100.h
View File

@ -170,13 +170,9 @@
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP 1
#define CFG_MEMTEST_START \
({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; })
#define CFG_MEMTEST_END \
({ \
DECLARE_GLOBAL_DATA_PTR; \
gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \
})
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
#endif /* __CONFIG_H */

4
include/configs/atstk1002.h
View File

@ -184,8 +184,8 @@
#define CFG_MALLOC_LEN (256*1024)
#define CFG_DMA_ALLOC_LEN (16384)
/* Allow 2MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)
/* Other configuration settings that shouldn't have to change all that often */

2
include/configs/atstk1004.h
View File

@ -167,7 +167,7 @@
#define CFG_MALLOC_LEN (256*1024)
/* Allow 4MB for the kernel run-time image */
/* Allow 2MB for the kernel run-time image */
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000)
#define CFG_BOOTPARAMS_LEN (16 * 1024)