mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ppc4xx: Netstal HCU5 board. Added POST. Various fixes
- Various fixes - Reduced rom_size from 384 to 320 kB - Environment is now in flash - Added POST - Support for OF Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
This commit is contained in:
Niklaus Giger
Stefan Roese
parent
4bd5036e60
commit
4371090e5d
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@ -21,7 +21,7 @@
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# Netstal Maschinen AG: HCU5 boards
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#
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TEXT_BASE = 0xFFFa0000
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TEXT_BASE = 0xFFFB0000
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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@ -137,7 +137,7 @@ SECTIONS
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*(COMMON)
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}
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ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
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ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
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_end = . ;
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PROVIDE (end = .);
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@ -48,14 +48,16 @@
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_TLB_FOR_BOOT_FLASH 3
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#define CFG_BOOT_BASE_ADDR 0xfff00000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff80000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_OCM_BASE 0xe0010000 /* ocm */
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#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
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#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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@ -78,14 +80,15 @@
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#define CONFIG_BAUDRATE 9600
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#undef CONFIG_SERIAL_MULTI /* needed to be able to define
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#define CONFIG_SERIAL_MULTI 1
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/* needed to be able to define
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CONFIG_SERIAL_SOFTWARE_FIFO, but
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CONFIG_SERIAL_SOFTWARE_FIFO (16) does not work */
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/* Size (bytes) of interrupt driven serial port buffer.
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@ -95,6 +98,7 @@
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#undef CONFIG_UART1_CONSOLE
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#undef CONFIG_CMD_HWFLOW
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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@ -103,8 +107,8 @@
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*----------------------------------------------------------------------*/
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#undef CFG_ENV_IS_IN_NVRAM
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_IN_EEPROM
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#define CFG_ENV_IS_IN_FLASH
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#undef CFG_ENV_IS_IN_EEPROM
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#undef CFG_ENV_IS_NOWHERE
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#ifdef CFG_ENV_IS_IN_EEPROM
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@ -117,22 +121,28 @@
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Put the environment in Flash */
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#define CFG_ENV_SIZE 8*1024 /* 8 KB Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
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#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
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#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
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#define CONFIG_DDR_ECC 1 /* enable ECC */
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#define CFG_MBYTES_SDRAM (128) /* 128 MB or 256 MB */
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#define CFG_DDR_CACHED_ADDR 0x50000000 /* setup 2nd TLB cached here */
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#undef CONFIG_DDR_DATA_EYE /* Do not use DDR2 optimization */
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#define CONFIG_DDR_ECC 1 /* enable ECC */
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/* Following two definitions must be kept in sync with config.h of vxWorks */
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#define USER_RESERVED_MEM ( 0) /* in kB */
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#define PM_RESERVED_MEM ( 64) /* in kB: pmLib reserved area size */
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#define CONFIG_PRAM ( USER_RESERVED_MEM + PM_RESERVED_MEM )
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/*-----------------------------------------------------------------------
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* I2C stuff for a ATMEL AT24C16 (2kB holding ENV, we are using the
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@ -165,8 +175,8 @@
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/* Setup some board specific values for the default environment variables */
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#define CONFIG_HOSTNAME hcu5
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#define CONFIG_IPADDR 172.25.1.42
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#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
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#define CONFIG_IPADDR 172.25.1.99
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#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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#define CONFIG_SERVERIP 172.25.1.3
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@ -187,21 +197,27 @@
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"bootfile=hcu5/uImage\0" \
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"rootpath=/home/hcu/eldk/ppc_4xxFP\0" \
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"load=tftp 100000 hcu5/u-boot.bin\0" \
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"update=protect off FFFa0000 FFFFFFFF;era FFFa0000 FFFFFFFF;" \
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"cp.b 100000 FFFa0000 60000\0" \
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"update=protect off FFFb0000 FFFFFFFF;era FFFb0000 FFFFFFFF;" \
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"cp.b 100000 FFFb0000 50000\0" \
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"upd=run load;run update\0" \
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"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom;" \
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"setenv bootargs emac(0,0)hcu5_vx_rom e=${ipaddr} " \
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" h=${serverip} u=dpu pw=netstal8752 tn=hcu5 f=0x3008;" \
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"bootvx ${loadaddr}\0" \
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"vx=tftp ${loadaddr} hcu5/hcu5_vx_rom; run vxboot\0" \
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"vxusb=usb start; fatload usb 0 ${loadaddr} vxWorks.st; run vxboot\0" \
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"vxargs=emac(0,0)c:hcu5/hcu5_vx_rom e=${ipaddr} h=${serverip}" \
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" u=dpu pw=netstal8752 tn=hcu5 f=0x3008\0" \
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"vxboot=setenv bootargs $(vxargs); bootvx ${loadaddr}\0" \
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"usbargs=setenv bootargs root=/dev/sda1 ro\0" \
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"linux=usb start; ext2load usb 0 ${loadaddr} /boot/uImage;" \
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"run usbargs addip addtty; bootm\0" \
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"net_nfs_fdt=tftp 200000 ${bootfile};" \
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"tftp ${fdt_addr} ${fdt_file};" \
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"run nfsargs addip addtty;" \
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"bootm 200000 - ${fdt_addr}\0" \
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"fdt_file=hcu5/hcu5.dtb\0" \
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"fdt_addr=400000\0" \
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""
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#define CONFIG_BOOTCOMMAND "run vx"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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@ -214,7 +230,7 @@
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#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & desc. */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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@ -246,7 +262,6 @@
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_EEPROM
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@ -264,6 +279,21 @@
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_USB
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_CACHE | \
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CFG_POST_FPU | \
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CFG_POST_ETHER | \
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CFG_POST_SPR)
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#define CFG_POST_UART_TABLE {UART0_BASE}
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
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#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#define CONFIG_SUPPORT_VFAT
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/*-----------------------------------------------------------------------
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@ -276,7 +306,7 @@
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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@ -291,17 +321,16 @@
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*----------------------------------------------------------------------*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI 1 /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr map to CFG_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Flash
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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@ -324,40 +363,30 @@
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#define CFG_CS_1 0xC8000000 /* CAN */
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#define CFG_CS_2 0xCC000000 /* CPLD and IMC-Bus Standard */
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#define CFG_CPLD CFG_CS_2
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#define CFG_CS_3 0xCD000000 /* CPLD and IMC-Bus Fast */
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#define CFG_CS_3 0xCE000000 /* CPLD and IMC-Bus Fast */
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/*-----------------------------------------------------------------------
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* FLASH organization
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* Memory Bank 0 (BOOT-FLASH) initialization
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*/
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#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
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#define CFG_BOOTFLASH_CS 0 /* Boot Flash chip connected to CSx */
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#define CFG_EBC_PB0AP 0x02005400
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#define CFG_EBC_PB0CR 0xFFF18000 /* (CFG_FLASH | 0xda000) */
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* Memory Bank 1 CAN-Chips initialization */
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/* Memory Bank 1 CAN-Chips initialization */
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#define CFG_EBC_PB1AP 0x02054500
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#define CFG_EBC_PB1CR 0xC8018000
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/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
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/* Memory Bank 2 CPLD/IMC-Bus standard initialization */
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#define CFG_EBC_PB2AP 0x01840300
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#define CFG_EBC_PB2CR 0xCC0BA000
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/* Memory Bank 3 IMC-Bus fast mode initialization */
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/* Memory Bank 3 IMC-Bus fast mode initialization */
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#define CFG_EBC_PB3AP 0x01800300
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#define CFG_EBC_PB3CR 0xCE0BA000
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/* Memory Bank 4 (not used) initialization */
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/* Memory Bank 4 (not used) initialization */
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#undef CFG_EBC_PB4AP
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#undef CFG_EBC_PB4CR
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/* Memory Bank 5 (not used) initialization */
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/* Memory Bank 5 (not used) initialization */
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#undef CFG_EBC_PB5AP
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#undef CFG_EBC_PB5CR
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@ -369,8 +398,8 @@
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_HUSH_PARSER /* use "hush" command parser */
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#ifdef CFG_HUSH_PARSER
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@ -381,4 +410,9 @@
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#endif /* __CONFIG_H */
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