mirror of
https://github.com/brain-hackers/u-boot-brain
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Merge branch 'for-1.3.2'
This commit is contained in:
Stefan Roese
commit
f90e69c634
2
Makefile
2
Makefile
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@ -1220,9 +1220,11 @@ G2000_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
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hcu4_config: unconfig
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@mkdir -p $(obj)board/netstal/common
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
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hcu5_config: unconfig
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@mkdir -p $(obj)board/netstal/common
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@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
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HH405_config: unconfig
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@ -1,5 +1,5 @@
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#
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# (C) Copyright 2007 Netstal Maschinen AG
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# (C) Copyright 2007-2008 Netstal Maschinen AG
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# Niklaus Giger (ng@netstal.com)
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#
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# This program is free software; you can redistribute it and/or
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@ -22,18 +22,14 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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vpath fixed_sdram.c ../common
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vpath hcu_flash.c ../common
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vpath nm_bsp.c ../common
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# NOBJS : Netstal common objects
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NOBJS = ../common/fixed_sdram.o ../common/hcu_flash.o ../common/nm_bsp.o
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NOBJS = fixed_sdram.o hcu_flash.o nm_bsp.o
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COBJS = $(BOARD).o
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SOBJS =
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(COBJS))
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NOBJS := $(addprefix $(obj),$(NOBJS))
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NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
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@ -1,5 +1,5 @@
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#
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# (C) Copyright 2007 Netstal Maschinen AG
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# (C) Copyright 2007-2008 Netstal Maschinen AG
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# Niklaus Giger (ng@netstal.com)
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#
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# This program is free software; you can redistribute it and/or
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@ -22,17 +22,15 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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vpath hcu_flash.c ../common
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vpath nm_bsp.c ../common
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# NOBJS : Netstal common objects
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NOBJS = ../common/hcu_flash.o ../common/nm_bsp.o
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NOBJS = hcu_flash.o nm_bsp.o
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COBJS = $(BOARD).o sdram.o
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SOBJS = init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(NOBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix ../common/,$(NOBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(COBJS))
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NOBJS := $(addprefix $(obj),$(NOBJS))
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NOBJS := $(addprefix $(obj)../common/,$(NOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) $(NOBJS)
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@ -175,7 +175,7 @@ int board_early_init_f(void)
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*-------------------------------------------------------------------*/
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
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mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
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return 0;
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@ -3,7 +3,7 @@
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* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
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* DDR2 controller, specifically the 440EPx/GRx.
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*
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* (C) Copyright 2007
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* (C) Copyright 2007-2008
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* Larry Johnson, lrj@acm.org.
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*
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* Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
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@ -77,10 +77,10 @@
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* memory.
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*
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* If at some time this restriction doesn't apply anymore, just define
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* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
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* CONFIG_4xx_DCACHE in the board config file and this code should setup
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* everything correctly.
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*/
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#if defined(CFG_ENABLE_SDRAM_CACHE)
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#if defined(CONFIG_4xx_DCACHE)
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#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
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#else
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#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
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@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
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/* The NDFC uses Smart Media (SMC) bytes order
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*/
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ecc_code[0] = p[2];
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ecc_code[1] = p[1];
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ecc_code[0] = p[1];
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ecc_code[1] = p[2];
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ecc_code[2] = p[3];
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return 0;
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@ -110,6 +110,10 @@
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# endif
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#endif /* CFG_INIT_DCACHE_CS */
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#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10)))
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#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END!
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#endif
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#define function_prolog(func_name) .text; \
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.align 2; \
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.globl func_name; \
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@ -66,7 +66,7 @@
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (8 << 10)
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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@ -75,7 +75,7 @@
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CFG_INIT_RAM_END (8 << 10)
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#define CFG_INIT_RAM_END (4 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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