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u-boot-brain
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Driver model: make some udevice fields private 

Driver model: Rename U_BOOT_DEVICE et al.
 dtoc: Tidy up and add more tests
 ns16550 code clean-up
 x86 and sandbox minor fixes for of-platdata
 dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next

Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
This commit is contained in:
Tom Rini 2021-01-05 22:34:43 -05:00
parent 720620e691 970349a96d
commit b11f634b1c
410 changed files with 2798 additions and 1955 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
arch/arc/include/asm/spl.h Normal file
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4
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -52,7 +52,11 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
continue;
}
#ifdef CONFIG_DM_ETH
priv = dev_get_priv(dev);
#else
priv = dev->priv;
#endif
if (priv->flags & TSEC_SGMII)
continue;

5
arch/arm/cpu/armv8/fsl-layerscape/spl.c
View File

@ -38,6 +38,9 @@ u32 spl_boot_device(void)
#ifdef CONFIG_SPL_BUILD
/* Define board data structure */
static struct bd_info bdata __attribute__ ((section(".data")));
void spl_board_init(void)
{
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_LSCH2)
@ -74,7 +77,7 @@ void board_init_f(ulong dummy)
get_clocks();
preloader_console_init();
spl_set_bd();
gd->bd = &bdata;
#ifdef CONFIG_SYS_I2C
#ifdef CONFIG_SPL_I2C_SUPPORT

10
arch/arm/lib/gic-v3-its.c
View File

@ -43,10 +43,10 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv)
int ret;
ret = uclass_get_device_by_driver(UCLASS_IRQ,
DM_GET_DRIVER(arm_gic_v3_its), &dev);
DM_DRIVER_GET(arm_gic_v3_its), &dev);
if (ret) {
pr_err("%s: failed to get %s irq device\n", __func__,
DM_GET_DRIVER(arm_gic_v3_its)->name);
DM_DRIVER_GET(arm_gic_v3_its)->name);
return ret;
}
@ -74,17 +74,17 @@ static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv)
int ret;
ret = uclass_get_device_by_driver(UCLASS_SYSCON,
DM_GET_DRIVER(gic_lpi_syscon), &dev);
DM_DRIVER_GET(gic_lpi_syscon), &dev);
if (ret) {
pr_err("%s: failed to get %s syscon device\n", __func__,
DM_GET_DRIVER(gic_lpi_syscon)->name);
DM_DRIVER_GET(gic_lpi_syscon)->name);
return ret;
}
regmap = syscon_get_regmap(dev);
if (!regmap) {
pr_err("%s: failed to regmap for %s syscon device\n", __func__,
DM_GET_DRIVER(gic_lpi_syscon)->name);
DM_DRIVER_GET(gic_lpi_syscon)->name);
return -ENODEV;
}
priv->lpi_base = regmap->ranges[0].start;

2
arch/arm/mach-aspeed/ast2500/clk_ast2500.c
View File

@ -12,7 +12,7 @@
int ast_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(aspeed_ast2500_scu), devp);
DM_DRIVER_GET(aspeed_ast2500_scu), devp);
}
void *ast_get_scu(void)

2
arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c
View File

@ -219,7 +219,7 @@ static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOC, "PC" },
};
U_BOOT_DEVICES(at91sam9260_gpios) = {
U_BOOT_DRVINFOS(at91sam9260_gpios) = {
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },

2
arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
View File

@ -175,7 +175,7 @@ static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOE, "PE" },
};
U_BOOT_DEVICES(at91sam9260_gpios) = {
U_BOOT_DRVINFOS(at91sam9260_gpios) = {
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
{ "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },

4
arch/arm/mach-davinci/da850_lowlevel.c
View File

@ -290,8 +290,8 @@ int arch_cpu_init(void)
board_gpio_init();
#if !CONFIG_IS_ENABLED(DM_SERIAL)
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM1),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif
/*
* Fix Power and Emulation Management Register

4
arch/arm/mach-davinci/spl.c
View File

@ -27,9 +27,9 @@ void puts(const char *str)
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), '\r');
ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
ns16550_putc((struct ns16550 *)(CONFIG_SYS_NS16550_COM1), c);
}
#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */

2
arch/arm/mach-imx/mx6/soc.c
View File

@ -44,7 +44,7 @@ static const struct imx_thermal_plat imx6_thermal_plat = {
.fuse_word = 6,
};
U_BOOT_DEVICE(imx6_thermal) = {
U_BOOT_DRVINFO(imx6_thermal) = {
.name = "imx_thermal",
.plat = &imx6_thermal_plat,
};

2
arch/arm/mach-imx/mx7/soc.c
View File

@ -60,7 +60,7 @@ static const struct imx_thermal_plat imx7_thermal_plat = {
.fuse_word = 3,
};
U_BOOT_DEVICE(imx7_thermal) = {
U_BOOT_DRVINFO(imx7_thermal) = {
.name = "imx_thermal",
.plat = &imx7_thermal_plat,
};

2
arch/arm/mach-k3/am6_init.c
View File

@ -238,7 +238,7 @@ void board_init_f(ulong dummy)
do_board_detect();
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
&dev);
if (ret)
printf("AVS init failed: %d\n", ret);

2
arch/arm/mach-k3/common.c
View File

@ -33,7 +33,7 @@ struct ti_sci_handle *get_ti_sci_handle(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
DM_GET_DRIVER(ti_sci), &dev);
DM_DRIVER_GET(ti_sci), &dev);
if (ret)
panic("Failed to get SYSFW (%d)\n", ret);

2
arch/arm/mach-k3/j721e_init.c
View File

@ -206,7 +206,7 @@ void board_init_f(ulong dummy)
do_board_detect();
#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(k3_avs),
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
&dev);
if (ret)
printf("AVS init failed: %d\n", ret);

2
arch/arm/mach-keystone/init.c
View File

@ -185,7 +185,7 @@ int arch_cpu_init(void)
* driver doesn't handle this.
*/
#ifndef CONFIG_DM_SERIAL
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
ns16550_init((struct ns16550 *)(CONFIG_SYS_NS16550_COM2),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif

4
arch/arm/mach-lpc32xx/devices.c
View File

@ -62,7 +62,7 @@ static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
};
#endif
U_BOOT_DEVICES(lpc32xx_uarts) = {
U_BOOT_DRVINFOS(lpc32xx_uarts) = {
#if defined(CONFIG_LPC32XX_HSUART)
{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
@ -124,7 +124,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
writel(ctrl, &clk->i2cclk_ctrl);
}
U_BOOT_DEVICE(lpc32xx_gpios) = {
U_BOOT_DRVINFO(lpc32xx_gpios) = {
.name = "gpio_lpc32xx"
};

4
arch/arm/mach-mediatek/mt7629/init.c
View File

@ -40,7 +40,7 @@ int mtk_pll_early_init(void)
int ret, i;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
if (ret)
return ret;
@ -59,7 +59,7 @@ int mtk_pll_early_init(void)
/* setup mcu bus */
ret = uclass_get_device_by_driver(UCLASS_SYSCON,
DM_GET_DRIVER(mtk_mcucfg), &dev);
DM_DRIVER_GET(mtk_mcucfg), &dev);
if (ret)
return ret;

2
arch/arm/mach-mediatek/mt8516/init.c
View File

@ -52,7 +52,7 @@ int mtk_pll_early_init(void)
int ret, i;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
if (ret)
return ret;

10
arch/arm/mach-omap2/am33xx/board.c
View File

@ -99,7 +99,7 @@ static const struct ns16550_plat am33xx_serial[] = {
# endif
};
U_BOOT_DEVICES(am33xx_uarts) = {
U_BOOT_DRVINFOS(am33xx_uarts) = {
{ "ns16550_serial", &am33xx_serial[0] },
# ifdef CONFIG_SYS_NS16550_COM2
{ "ns16550_serial", &am33xx_serial[1] },
@ -119,7 +119,7 @@ static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
};
U_BOOT_DEVICES(am33xx_i2c) = {
U_BOOT_DRVINFOS(am33xx_i2c) = {
{ "i2c_omap", &am33xx_i2c[0] },
{ "i2c_omap", &am33xx_i2c[1] },
{ "i2c_omap", &am33xx_i2c[2] },
@ -138,7 +138,7 @@ static const struct omap_gpio_plat am33xx_gpio[] = {
#endif
};
U_BOOT_DEVICES(am33xx_gpios) = {
U_BOOT_DRVINFOS(am33xx_gpios) = {
{ "gpio_omap", &am33xx_gpio[0] },
{ "gpio_omap", &am33xx_gpio[1] },
{ "gpio_omap", &am33xx_gpio[2] },
@ -155,7 +155,7 @@ static const struct omap3_spi_plat omap3_spi_pdata = {
.pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT,
};
U_BOOT_DEVICE(am33xx_spi) = {
U_BOOT_DRVINFO(am33xx_spi) = {
.name = "omap3_spi",
.plat = &omap3_spi_pdata,
};
@ -234,7 +234,7 @@ static struct ti_musb_plat usb1 = {
},
};
U_BOOT_DEVICES(am33xx_usbs) = {
U_BOOT_DRVINFOS(am33xx_usbs) = {
#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
{ "ti-musb-peripheral", &usb0 },
#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST

2
arch/arm/mach-omap2/omap3/board.c
View File

@ -47,7 +47,7 @@ static const struct omap_gpio_plat omap34xx_gpio[] = {
{ 5, OMAP34XX_GPIO6_BASE },
};
U_BOOT_DEVICES(omap34xx_gpios) = {
U_BOOT_DRVINFOS(omap34xx_gpios) = {
{ "gpio_omap", &omap34xx_gpio[0] },
{ "gpio_omap", &omap34xx_gpio[1] },
{ "gpio_omap", &omap34xx_gpio[2] },

4
arch/arm/mach-rockchip/misc.c
View File

@ -67,10 +67,10 @@ int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
/* retrieve the device */
#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(rockchip_efuse), &dev);
DM_DRIVER_GET(rockchip_efuse), &dev);
#elif CONFIG_IS_ENABLED(ROCKCHIP_OTP)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(rockchip_otp), &dev);
DM_DRIVER_GET(rockchip_otp), &dev);
#endif
if (ret) {
debug("%s: could not find efuse device\n", __func__);

2
arch/arm/mach-rockchip/px30/clk_px30.c
View File

@ -13,7 +13,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_px30_cru), devp);
DM_DRIVER_GET(rockchip_px30_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3036/clk_rk3036.c
View File

@ -14,7 +14,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3036_cru), devp);
DM_DRIVER_GET(rockchip_rk3036_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3128/clk_rk3128.c
View File

@ -13,7 +13,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3128_cru), devp);
DM_DRIVER_GET(rockchip_rk3128_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3188/clk_rk3188.c
View File

@ -14,7 +14,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3188_cru), devp);
DM_DRIVER_GET(rockchip_rk3188_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk322x/clk_rk322x.c
View File

@ -13,7 +13,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk322x_cru), devp);
DM_DRIVER_GET(rockchip_rk322x_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3288/clk_rk3288.c
View File

@ -14,7 +14,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3288_cru), devp);
DM_DRIVER_GET(rockchip_rk3288_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3308/clk_rk3308.c
View File

@ -13,7 +13,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3308_cru), devp);
DM_DRIVER_GET(rockchip_rk3308_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3328/clk_rk3328.c
View File

@ -12,7 +12,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3328_cru), devp);
DM_DRIVER_GET(rockchip_rk3328_cru), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-rockchip/rk3368/clk_rk3368.c
View File

@ -14,7 +14,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3368_cru), devp);
DM_DRIVER_GET(rockchip_rk3368_cru), devp);
}
void *rockchip_get_cru(void)

4
arch/arm/mach-rockchip/rk3399/clk_rk3399.c
View File

@ -14,7 +14,7 @@
static int rockchip_get_cruclk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(clk_rk3399), devp);
DM_DRIVER_GET(clk_rk3399), devp);
}
void *rockchip_get_cru(void)
@ -35,7 +35,7 @@ void *rockchip_get_cru(void)
static int rockchip_get_pmucruclk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp);
DM_DRIVER_GET(rockchip_rk3399_pmuclk), devp);
}
void *rockchip_get_pmucru(void)

2
arch/arm/mach-rockchip/rv1108/clk_rv1108.c
View File

@ -14,7 +14,7 @@
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(clk_rv1108), devp);
DM_DRIVER_GET(clk_rv1108), devp);
}
void *rockchip_get_cru(void)

2
arch/arm/mach-socfpga/clock_manager_agilex.c
View File

@ -24,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(socfpga_agilex_clk),
DM_DRIVER_GET(socfpga_agilex_clk),
&dev);
if (ret)
return 0;

2
arch/arm/mach-stm32mp/bsec.c
View File

@ -525,7 +525,7 @@ bool bsec_dbgswenable(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec), &dev);
DM_DRIVER_GET(stm32mp_bsec), &dev);
if (ret || !dev) {
pr_debug("bsec driver not available\n");
return false;

2
arch/arm/mach-stm32mp/cmd_stm32key.c
View File

@ -31,7 +31,7 @@ static void fuse_hash_value(u32 addr, bool print)
int i, ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
pr_err("Can't find stm32mp_bsec driver\n");

6
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c
View File

@ -1340,7 +1340,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
pr_debug("%s: %x %lx\n", __func__, offset, *size);
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stpmic1_nvm),
DM_DRIVER_GET(stpmic1_nvm),
&dev);
if (ret)
return ret;
@ -1351,7 +1351,7 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
memset(data->pmic_part, 0, PMIC_SIZE);
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stpmic1_nvm),
DM_DRIVER_GET(stpmic1_nvm),
&dev);
if (ret)
return ret;
@ -1389,7 +1389,7 @@ int stm32prog_pmic_start(struct stm32prog_data *data)
}
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stpmic1_nvm),
DM_DRIVER_GET(stpmic1_nvm),
&dev);
if (ret)
return ret;

6
arch/arm/mach-stm32mp/cpu.c
View File

@ -318,7 +318,7 @@ static u32 get_otp(int index, int shift, int mask)
u32 otp = 0;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (!ret)
@ -563,7 +563,7 @@ __weak int setup_mac_address(void)
return 0;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret)
return ret;
@ -601,7 +601,7 @@ static int setup_serial_number(void)
return 0;
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret)
return ret;

5
arch/arm/mach-stm32mp/pwr_regulator.c
View File

@ -9,6 +9,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <power/pmic.h>
@ -80,7 +81,7 @@ static int stm32mp_pwr_bind(struct udevice *dev)
{
int children;
children = pmic_bind_children(dev, dev->node, pwr_children_info);
children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info);
if (!children)
dev_dbg(dev, "no child found\n");
@ -165,7 +166,7 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev)
}
uc_pdata->type = REGULATOR_TYPE_FIXED;
dev->priv = (void *)*p;
dev_set_priv(dev, (void *)*p);
return 0;
}

2
arch/arm/mach-tegra/board.c
View File

@ -264,7 +264,7 @@ static struct ns16550_plat ns16550_com1_pdata = {
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(ns16550_com1) = {
U_BOOT_DRVINFO(ns16550_com1) = {
"ns16550_serial", &ns16550_com1_pdata
};
#endif

2
arch/arm/mach-tegra/board2.c
View File

@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
U_BOOT_DEVICE(tegra_gpios) = {
U_BOOT_DRVINFO(tegra_gpios) = {
"gpio_tegra"
};
#endif

2
arch/arm/mach-uniphier/micro-support-card.c
View File

@ -95,7 +95,7 @@ void support_card_init(void)
/* The system bus must be initialized for access to the support card. */
ret = uclass_get_device_by_driver(UCLASS_SIMPLE_BUS,
DM_GET_DRIVER(uniphier_system_bus_driver),
DM_DRIVER_GET(uniphier_system_bus_driver),
&dev);
if (ret)
return;

4
arch/arm/mach-zynq/clk.c
View File

@ -40,7 +40,7 @@ int set_cpu_clk_info(void)
int i, ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(zynq_clk), &dev);
DM_DRIVER_GET(zynq_clk), &dev);
if (ret)
return ret;
@ -75,7 +75,7 @@ int soc_clk_dump(void)
int i, ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(zynq_clk), &dev);
DM_DRIVER_GET(zynq_clk), &dev);
if (ret)
return ret;

2
arch/arm/mach-zynq/timer.c
View File

@ -68,7 +68,7 @@ int timer_init(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_GET_DRIVER(zynq_clk), &dev);
DM_DRIVER_GET(zynq_clk), &dev);
if (ret)
return ret;

0
arch/m68k/include/asm/spl.h Normal file
View File

2
arch/mips/mach-mtmips/mt7628/init.c
View File

@ -74,7 +74,7 @@ int print_cpuinfo(void)
ddr ? "" : "2", chipmode & 0x01 ? 4 : 3,
chipmode & 0x02 ? "XTAL" : "CPLL");
ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(mt7628_clk),
ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(mt7628_clk),
&clkdev);
if (ret)
return ret;

0
arch/nds32/include/asm/spl.h Normal file
View File

0
arch/nios2/include/asm/spl.h Normal file
View File

2
arch/riscv/lib/sifive_clint.c
View File

@ -25,7 +25,7 @@ int riscv_init_ipi(void)
struct udevice *dev;
ret = uclass_get_device_by_driver(UCLASS_TIMER,
DM_GET_DRIVER(sifive_clint), &dev);
DM_DRIVER_GET(sifive_clint), &dev);
if (ret)
return ret;

5
arch/sandbox/cpu/os.c
View File

@ -790,6 +790,11 @@ int os_find_u_boot(char *fname, int maxlen)
int os_spl_to_uboot(const char *fname)
{
struct sandbox_state *state = state_get_current();
printf("%s\n", __func__);
/* U-Boot will delete ram buffer after read: "--rm_memory"*/
state->ram_buf_rm = true;
return os_jump_to_file(fname);
}

7
arch/sandbox/cpu/start.c
View File

@ -457,6 +457,13 @@ int main(int argc, char *argv[])
if (os_parse_args(state, argc, argv))
return 1;
/* Remove old memory file if required */
if (state->ram_buf_rm && state->ram_buf_fname) {
os_unlink(state->ram_buf_fname);
state->write_ram_buf = false;
state->ram_buf_fname = NULL;
}
ret = sandbox_read_state(state, state->state_fname);
if (ret)
goto err;

4
arch/sandbox/cpu/state.c
View File

@ -415,10 +415,6 @@ int state_uninit(void)
}
}
/* Remove old memory file if required */
if (state->ram_buf_rm && state->ram_buf_fname)
os_unlink(state->ram_buf_fname);
/* Delete this at the last moment so as not to upset gdb too much */
if (state->jumped_fname)
os_unlink(state->jumped_fname);

4
arch/sandbox/dts/sandbox.dts
View File

@ -41,7 +41,7 @@
cros_ec: cros-ec {
reg = <0 0>;
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
compatible = "google,cros-ec-sandbox";
};
@ -83,7 +83,7 @@
};
spi: spi@0 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
#address-cells = <1>;
#size-cells = <0>;
reg = <0 0>;

16
arch/sandbox/dts/sandbox.dtsi
View File

@ -56,7 +56,7 @@
};
gpio_a: gpios@0 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <1>;
@ -65,7 +65,7 @@
};
gpio_b: gpios@1 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
gpio-controller;
compatible = "sandbox,gpio";
#gpio-cells = <2>;
@ -120,7 +120,7 @@
};
lcd {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
compatible = "sandbox,lcd-sdl";
xres = <1366>;
yres = <768>;
@ -209,7 +209,7 @@
spi@0 {
firmware_storage_spi: flash@0 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
reg = <0>;
compatible = "spansion,m25p16", "jedec,spi-nor";
spi-max-frequency = <40000000>;
@ -248,11 +248,6 @@
stringarray = "one";
};
spl-test4 {
u-boot,dm-pre-reloc;
compatible = "sandbox,spl-test.2";
};
spl-test5 {
u-boot,dm-tpl;
compatible = "sandbox,spl-test";
@ -283,7 +278,6 @@
};
tpm {
u-boot,dm-pre-reloc;
compatible = "google,sandbox-tpm";
};
@ -420,6 +414,6 @@
};
keyboard-controller {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
};
};

14
arch/sandbox/include/asm/i2c.h Normal file
View File

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#ifndef __asn_i2c_h
#define __asn_i2c_h
struct sandbox_i2c_priv {
bool test_mode;
};
#endif /* __asn_i2c_h */

30
arch/sandbox/include/asm/serial.h Normal file
View File

@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#ifndef __asm_serial_h
#define __asm_serial_h
#include <dt-structs.h>
struct sandbox_serial_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_sandbox_serial dtplat;
#endif
int colour; /* Text colour to use for output, -1 for none */
};
/**
* struct sandbox_serial_priv - Private data for this driver
*
* @buf: holds input characters available to be read by this driver
*/
struct sandbox_serial_priv {
struct membuff buf;
char serial_buf[16];
bool start_of_line;
};
#endif /* __asm_serial_h */

0
arch/sh/include/asm/spl.h Normal file
View File

1
arch/x86/cpu/apollolake/Kconfig
View File

@ -19,6 +19,7 @@ config INTEL_APOLLOLAKE
select SMP_AP_WORK
select INTEL_GMA_SWSMISCI
select ACPI_GNVS_EXTERNAL
select TPL_OF_PLATDATA_PARENT
imply ENABLE_MRC_CACHE
imply AHCI_PCI
imply SCSI

5
arch/x86/cpu/apollolake/fsp_m.c
View File

@ -32,7 +32,10 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
node = dev_ofnode(dev);
if (!ofnode_valid(node))
return log_msg_ret("fsp-m settings", -ENOENT);
return log_msg_ret("node", -ENOENT);
node = ofnode_find_subnode(node, "fsp-m");
if (!ofnode_valid(node))
return log_msg_ret("fspm", -ENOENT);
ret = fsp_m_update_config_from_dtb(node, cfg);
if (ret)

34
arch/x86/cpu/apollolake/hostbridge.c
View File

@ -24,6 +24,7 @@
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/acpi.h>
#include <asm/arch/hostbridge.h>
#include <asm/arch/systemagent.h>
#include <dt-bindings/sound/nhlt.h>
#include <dm/acpi.h>
@ -41,25 +42,7 @@ enum {
TOLUD = 0xbc,
};
/**
* struct apl_hostbridge_plat - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
* @early_pads_count: Number of pads to process
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
struct apl_hostbridge_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
u32 *early_pads;
int early_pads_count;
uint pciex_region_size;
pci_dev_t bdf;
};
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
static const struct nhlt_format_config dmic_1ch_formats[] = {
/* 48 KHz 16-bits per sample. */
{
@ -155,6 +138,7 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
.num_formats = ARRAY_SIZE(dmic_4ch_formats),
},
};
#endif
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
{
@ -283,7 +267,7 @@ static int apl_acpi_hb_get_name(const struct udevice *dev, char *out_name)
return acpi_copy_name(out_name, "RHUB");
}
#ifdef CONFIG_GENERATE_ACPI_TABLE
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
static int apl_acpi_hb_write_tables(const struct udevice *dev,
struct acpi_ctx *ctx)
{
@ -322,7 +306,6 @@ static int apl_acpi_hb_write_tables(const struct udevice *dev,
return 0;
}
#endif
static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx)
{
@ -347,6 +330,7 @@ static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx)
return log_msg_ret("channels", -EINVAL);
}
#endif
static int apl_hostbridge_remove(struct udevice *dev)
{
@ -385,21 +369,23 @@ ulong sa_get_tseg_base(struct udevice *dev)
struct acpi_ops apl_hostbridge_acpi_ops = {
.get_name = apl_acpi_hb_get_name,
#ifdef CONFIG_GENERATE_ACPI_TABLE
#if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)
.write_tables = apl_acpi_hb_write_tables,
#endif
.setup_nhlt = apl_acpi_setup_nhlt,
#endif
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
};
#endif
U_BOOT_DRIVER(intel_apl_hostbridge) = {
.name = "intel_apl_hostbridge",
.id = UCLASS_NORTHBRIDGE,
.of_match = apl_hostbridge_ids,
.of_match = of_match_ptr(apl_hostbridge_ids),
.of_to_plat = apl_hostbridge_of_to_plat,
.probe = apl_hostbridge_probe,
.remove = apl_hostbridge_remove,

13
arch/x86/cpu/apollolake/lpc.c
View File

@ -81,10 +81,11 @@ int lpc_open_pmio_window(uint base, uint size)
lgir_reg_num = find_unused_pmio_window();
if (lgir_reg_num < 0) {
log_err("LPC: Cannot open IO window: %lx size %lx\n",
bridge_base, size - bridged_size);
log_err("No more IO windows\n");
if (spl_phase() > PHASE_TPL) {
log_err("LPC: Cannot open IO window: %lx size %lx\n",
bridge_base, size - bridged_size);
log_err("No more IO windows\n");
}
return -ENOSPC;
}
lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
@ -127,15 +128,17 @@ struct acpi_ops apl_lpc_acpi_ops = {
.inject_dsdt = southbridge_inject_dsdt,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
};
#endif
/* All pads are LPC already configured by the hostbridge, so no probing here */
U_BOOT_DRIVER(intel_apl_lpc) = {
.name = "intel_apl_lpc",
.id = UCLASS_LPC,
.of_match = apl_lpc_ids,
.of_match = of_match_ptr(apl_lpc_ids),
ACPI_OPS_PTR(&apl_lpc_acpi_ops)
};

4
arch/x86/cpu/apollolake/pch.c
View File

@ -23,14 +23,16 @@ static const struct pch_ops apl_pch_ops = {
.set_spi_protect = apl_set_spi_protect,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id apl_pch_ids[] = {
{ .compatible = "intel,apl-pch" },
{ }
};
#endif
U_BOOT_DRIVER(intel_apl_pch) = {
.name = "intel_apl_pch",
.id = UCLASS_PCH,
.of_match = apl_pch_ids,
.of_match = of_match_ptr(apl_pch_ids),
.ops = &apl_pch_ops,
};

14
arch/x86/cpu/apollolake/pmc.c
View File

@ -16,6 +16,7 @@
#include <acpi/acpi_s3.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/pmc.h>
#include <linux/bitops.h>
#include <power/acpi_pmc.h>
@ -53,13 +54,6 @@ enum {
CF9_GLB_RST = 1 << 20,
};
struct apl_pmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
pci_dev_t bdf;
};
static int apl_pmc_fill_power_state(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
@ -205,22 +199,24 @@ static int apl_pmc_probe(struct udevice *dev)
return 0;
}
static struct acpi_pmc_ops apl_pmc_ops = {
static const struct acpi_pmc_ops apl_pmc_ops = {
.init = apl_pmc_fill_power_state,
.prev_sleep_state = apl_prev_sleep_state,
.disable_tco = apl_disable_tco,
.global_reset_set_enable = apl_global_reset_set_enable,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id apl_pmc_ids[] = {
{ .compatible = "intel,apl-pmc" },
{ }
};
#endif
U_BOOT_DRIVER(intel_apl_pmc) = {
.name = "intel_apl_pmc",
.id = UCLASS_ACPI_PMC,
.of_match = apl_pmc_ids,
.of_match = of_match_ptr(apl_pmc_ids),
.of_to_plat = apl_pmc_ofdata_to_uc_plat,
.probe = apl_pmc_probe,
.ops = &apl_pmc_ops,

30
arch/x86/cpu/apollolake/spl.c
View File

@ -83,33 +83,6 @@ static int apl_flash_probe(struct udevice *dev)
return spi_flash_std_probe(dev);
}
/*
* Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
* need to allocate the parent_plat since by the time this function is
* called device_bind() has already gone past that step.
*/
static int apl_flash_bind(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
!CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
struct dm_spi_slave_plat *plat;
struct udevice *spi;
int ret;
ret = uclass_first_device_err(UCLASS_SPI, &spi);
if (ret)
return ret;
dev->parent = spi;
plat = calloc(sizeof(*plat), 1);
if (!plat)
return -ENOMEM;
dev->parent_plat = plat;
}
return 0;
}
static const struct dm_spi_flash_ops apl_flash_ops = {
.read = apl_flash_std_read,
};
@ -123,9 +96,8 @@ U_BOOT_DRIVER(winbond_w25q128fw) = {
.name = "winbond_w25q128fw",
.id = UCLASS_SPI_FLASH,
.of_match = apl_flash_ids,
.bind = apl_flash_bind,
.probe = apl_flash_probe,
.priv_auto = sizeof(struct spi_flash),
.priv_auto = sizeof(struct spi_nor),
.ops = &apl_flash_ops,
};

50
arch/x86/cpu/apollolake/uart.c
View File

@ -16,6 +16,8 @@
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/lpss.h>
#include <dm/device-internal.h>
#include <asm/arch/uart.h>
/* Low-power Subsystem (LPSS) clock register */
enum {
@ -68,7 +70,7 @@ void apl_uart_init(pci_dev_t bdf, ulong base)
* This driver uses its own compatible string but almost everything else from
* the standard ns16550 driver. This allows us to provide an of-platdata
* implementation, since the platdata produced by of-platdata does not match
* struct ns16550_plat.
* struct apl_ns16550_plat.
*
* When running with of-platdata (generally TPL), the platdata is converted to
* something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
@ -77,10 +79,10 @@ void apl_uart_init(pci_dev_t bdf, ulong base)
static int apl_ns16550_probe(struct udevice *dev)
{
struct ns16550_plat *plat = dev_get_plat(dev);
struct apl_ns16550_plat *plat = dev_get_plat(dev);
if (!CONFIG_IS_ENABLED(PCI))
apl_uart_init(plat->bdf, plat->base);
apl_uart_init(plat->ns16550.bdf, plat->ns16550.base);
return ns16550_serial_probe(dev);
}
@ -88,24 +90,28 @@ static int apl_ns16550_probe(struct udevice *dev)
static int apl_ns16550_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
struct ns16550_plat *plat;
struct dtd_intel_apl_ns16550 *dtplat;
struct apl_ns16550_plat *plat = dev_get_plat(dev);
struct ns16550_plat ns;
/*
* Convert our plat to the ns16550's plat, so we can just use
* that driver
* The device's plat uses struct apl_ns16550_plat which starts with the
* dtd struct, but the ns16550 driver expects it to be struct ns16550.
* Set up what that driver expects. Note that this means that the values
* cannot be read in this driver when using of-platdata.
*
* TODO(sjg@chromium.org): Consider having a separate plat pointer for
* of-platdata so that it is not necessary to overwrite this.
*/
plat = malloc(sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->base = dtplat->early_regs[0];
plat->reg_width = 1;
plat->reg_shift = dtplat->reg_shift;
plat->reg_offset = 0;
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
dev->plat = plat;
dtplat = &plat->dtplat;
ns.base = dtplat->early_regs[0];
ns.reg_width = 1;
ns.reg_shift = dtplat->reg_shift;
ns.reg_offset = 0;
ns.clock = dtplat->clock_frequency;
ns.fcr = UART_FCR_DEFVAL;
ns.bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
memcpy(plat, &ns, sizeof(ns));
#else
int ret;
@ -117,17 +123,19 @@ static int apl_ns16550_of_to_plat(struct udevice *dev)
return 0;
}
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id apl_ns16550_serial_ids[] = {
{ .compatible = "intel,apl-ns16550" },
{ },
};
#endif
U_BOOT_DRIVER(intel_apl_ns16550) = {
.name = "intel_apl_ns16550",
.id = UCLASS_SERIAL,
.of_match = apl_ns16550_serial_ids,
.plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.of_match = of_match_ptr(apl_ns16550_serial_ids),
.plat_auto = sizeof(struct apl_ns16550_plat),
.priv_auto = sizeof(struct ns16550),
.ops = &ns16550_serial_ops,
.of_to_plat = apl_ns16550_of_to_plat,
.probe = apl_ns16550_probe,

1
arch/x86/cpu/i386/call64.S
View File

@ -11,6 +11,7 @@
#include <asm/processor-flags.h>
.code32
.section .text_call64
.globl cpu_call64
cpu_call64:
/*

2
arch/x86/cpu/intel_common/Makefile
View File

@ -26,7 +26,7 @@ obj-y += cpu.o
obj-y += fast_spi.o
obj-y += lpc.o
obj-y += lpss.o
obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o
obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o
ifndef CONFIG_TARGET_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64

23
arch/x86/cpu/intel_common/itss.c
View File

@ -19,25 +19,6 @@
#include <spl.h>
#include <asm/itss.h>
struct itss_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_itss dtplat;
#endif
};
/* struct pmc_route - Routing for PMC to GPIO */
struct pmc_route {
u32 pmc;
u32 gpio;
};
struct itss_priv {
struct pmc_route *route;
uint route_count;
u32 irq_snapshot[NUM_IPC_REGS];
};
static int set_polarity(struct udevice *dev, uint irq, bool active_low)
{
u32 mask;
@ -230,15 +211,17 @@ static const struct irq_ops itss_ops = {
#endif
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id itss_ids[] = {
{ .compatible = "intel,itss", .data = X86_IRQT_ITSS },
{ }
};
#endif
U_BOOT_DRIVER(intel_itss) = {
.name = "intel_itss",
.id = UCLASS_IRQ,
.of_match = itss_ids,
.of_match = of_match_ptr(itss_ids),
.ops = &itss_ops,
.bind = itss_bind,
.of_to_plat = itss_of_to_plat,

15
arch/x86/cpu/intel_common/p2sb.c
View File

@ -13,20 +13,13 @@
#include <log.h>
#include <p2sb.h>
#include <spl.h>
#include <asm/p2sb.h>
#include <asm/pci.h>
#include <linux/bitops.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
struct p2sb_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
#endif
ulong mmio_base;
pci_dev_t bdf;
};
/* PCI config space registers */
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT BIT(7)
@ -180,19 +173,21 @@ static int p2sb_child_post_bind(struct udevice *dev)
return 0;
}
struct p2sb_ops p2sb_ops = {
static const struct p2sb_ops p2sb_ops = {
.set_hide = intel_p2sb_set_hide,
};
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id p2sb_ids[] = {
{ .compatible = "intel,p2sb" },
{ }
};
#endif
U_BOOT_DRIVER(intel_p2sb) = {
.name = "intel_p2sb",
.id = UCLASS_P2SB,
.of_match = p2sb_ids,
.of_match = of_match_ptr(p2sb_ids),
.probe = p2sb_probe,
.remove = p2sb_remove,
.ops = &p2sb_ops,

4
arch/x86/cpu/slimbootloader/serial.c
View File

@ -18,7 +18,7 @@ static int slimbootloader_serial_of_to_plat(struct udevice *dev)
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
struct ns16550_plat *plat = dev->plat;
struct ns16550_plat *plat = dev_get_plat(dev);
if (!gd->arch.hob_list)
panic("hob list not found!");
@ -59,7 +59,7 @@ U_BOOT_DRIVER(serial_slimbootloader) = {
.of_match = slimbootloader_serial_ids,
.of_to_plat = slimbootloader_serial_of_to_plat,
.plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.priv_auto = sizeof(struct ns16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
};

5
arch/x86/cpu/turbo.c
View File

@ -35,12 +35,15 @@ static inline void set_global_turbo_state(int state)
}
#endif
/* gcc 7.3 does not wwant to drop strings, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
static const char *const turbo_state_desc[] = {
[TURBO_UNKNOWN] = "unknown",
[TURBO_UNAVAILABLE] = "unavailable",
[TURBO_DISABLED] = "available but hidden",
[TURBO_ENABLED] = "available and visible"
};
#endif
/*
* Determine the current state of Turbo and cache it for later.
@ -76,7 +79,9 @@ int turbo_get_state(void)
}
set_global_turbo_state(turbo_state);
#ifndef CONFIG_TPL_BUILD
debug("Turbo is %s\n", turbo_state_desc[turbo_state]);
#endif
return turbo_state;
}

22
arch/x86/dts/chromebook_coral.dts
View File

@ -102,12 +102,13 @@
};
cpus {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
#address-cells = <1>;
#size-cells = <0>;
cpu_0: cpu@0 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
u-boot,dm-spl;
device_type = "cpu";
compatible = "intel,apl-cpu";
reg = <0>;
@ -174,6 +175,9 @@
*/
fsp_s: fsp-s {
};
fsp_m: fsp-m {
u-boot,dm-spl;
};
nhlt {
intel,dmic-channels = <4>;
@ -181,12 +185,14 @@
};
punit@0,1 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
u-boot,dm-spl;
reg = <0x00000800 0 0 0 0>;
compatible = "intel,apl-punit";
};
gma@2,0 {
u-boot,dm-pre-proper;
reg = <0x00001000 0 0 0 0>;
compatible = "fsp-fb";
};
@ -321,7 +327,8 @@
};
spi: fast-spi@d,2 {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
u-boot,dm-spl;
reg = <0x02006a10 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
@ -332,7 +339,8 @@
fwstore_spi: spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
u-boot,dm-spl;
reg = <0>;
compatible = "winbond,w25q128fw",
"jedec,spi-nor";
@ -574,7 +582,7 @@
#size-cells = <0>;
u-boot,dm-pre-reloc;
cros_ec: cros-ec {
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
@ -650,7 +658,9 @@
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
>;
};
&fsp_m {
fspm,package = <PACKAGE_BGA>;
fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
fspm,memory-down = <MEMORY_DOWN_YES>;

2
arch/x86/dts/rtc.dtsi
View File

@ -1,7 +1,7 @@
/ {
rtc: rtc {
compatible = "motorola,mc146818";
u-boot,dm-pre-reloc;
u-boot,dm-pre-proper;
reg = <0x70 2>;
};
};

18
arch/x86/include/asm/arch-apollolake/gpio.h
View File

@ -485,4 +485,22 @@
/* This is needed by ACPI */
#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */
#ifndef __ASSEMBLY__
#include <dt-structs.h>
/**
* struct apl_gpio_plat - platform data for each device
*
* @dtplat: of-platdata data from C struct
*/
struct apl_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_apl_pinctrl dtplat;
#endif
};
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_GPIO_H_ */

28
arch/x86/include/asm/arch-apollolake/hostbridge.h Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
*/
#ifndef _ASM_ARCH_HOSTBRIDGE_H_
#define _ASM_ARCH_HOSTBRIDGE_H_
/**
* struct apl_hostbridge_plat - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
* @early_pads_count: Number of pads to process
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
struct apl_hostbridge_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
u32 *early_pads;
int early_pads_count;
uint pciex_region_size;
pci_dev_t bdf;
};
#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */

16
arch/x86/include/asm/arch-apollolake/pmc.h Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
*/
#ifndef ASM_ARCH_PMC_H
#define ASM_ARCH_PMC_H
struct apl_pmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
pci_dev_t bdf;
};
#endif /* ASM_ARCH_PMC_H */

19
arch/x86/include/asm/arch-apollolake/uart.h
View File

@ -6,6 +6,23 @@
#ifndef _ASM_ARCH_UART_H
#define _ASM_ARCH_UART_H
#include <ns16550.h>
/**
* struct apl_ns16550_plat - platform data for the APL UART
*
* Note that when of-platdata is in use, apl_ns16550_of_to_plat() actually
* copies the ns16550_plat contents to the start of this struct, meaning that
* dtplat is no-longer valid. This is done so that the ns16550 driver can use
* dev_get_plat() without any offsets or adjustments.
*/
struct apl_ns16550_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_ns16550 dtplat;
#endif
struct ns16550_plat ns16550;
};
/**
* apl_uart_init() - Set up the APL UART device and clock
*
@ -15,6 +32,6 @@
* The UART won't actually work unless the GPIO settings are correct and the
* signals actually exit the SoC. See board_debug_uart_init() for that.
*/
int apl_uart_init(pci_dev_t bdf, ulong base);
void apl_uart_init(pci_dev_t bdf, ulong base);
#endif

21
arch/x86/include/asm/itss.h
View File

@ -11,6 +11,8 @@
#ifndef _ASM_ARCH_ITSS_H
#define _ASM_ARCH_ITSS_H
#include <irq.h>
#define GPIO_IRQ_START 50
#define GPIO_IRQ_END ITSS_MAX_IRQ
@ -42,4 +44,23 @@
/* ITSS Power reduction control */
#define PCR_ITSS_ITSSPRC 0x3300
struct itss_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_itss dtplat;
#endif
};
/* struct pmc_route - Routing for PMC to GPIO */
struct pmc_route {
u32 pmc;
u32 gpio;
};
struct itss_priv {
struct pmc_route *route;
uint route_count;
u32 irq_snapshot[NUM_IPC_REGS];
};
#endif /* _ASM_ARCH_ITSS_H */

18
arch/x86/include/asm/p2sb.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
*/
#ifndef ASM_P2SB_H
#define ASM_P2SB_H
/* Platform data for the P2SB */
struct p2sb_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
#endif
ulong mmio_base;
pci_dev_t bdf;
};
#endif /* ASM_P2SB_H */

6
arch/x86/include/asm/pmu.h
View File

@ -2,9 +2,9 @@
/*
* Copyright (c) 2017 Intel Corporation
*/
#ifndef _X86_ASM_PMU_IPC_H_
#define _X86_ASM_PMU_IPC_H_
#ifndef _X86_ASM_PMU_H_
#define _X86_ASM_PMU_H_
int pmu_turn_power(unsigned int lss, bool on);
#endif /* _X86_ASM_PMU_IPC_H_ */
#endif /* _X86_ASM_PMU_H_ */

18
arch/x86/include/asm/sysreset.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 Google LLC
*/
#ifndef _X86_ASM_SYSRESET_H_
#define _X86_ASM_SYSRESET_H_
#include <dt-structs.h>
struct x86_sysreset_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_x86_reset dtplat;
#endif
struct udevice *pch;
};
#endif /* _X86_ASM_SYSRESET_H_ */

4
arch/x86/lib/tpl.c
View File

@ -133,14 +133,16 @@ void spl_board_init(void)
* for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
* the auto allocation (after relocation).
*/
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
static const struct udevice_id tpl_fake_pci_ids[] = {
{ .compatible = "pci-x86" },
{ }
};
#endif
U_BOOT_DRIVER(pci_x86) = {
.name = "pci_x86",
.id = UCLASS_SIMPLE_BUS,
.of_match = tpl_fake_pci_ids,
.of_match = of_match_ptr(tpl_fake_pci_ids),
};
#endif

0
arch/xtensa/include/asm/spl.h Normal file
View File

2
board/Arcturus/ucp1020/spl.c
View File

@ -58,7 +58,7 @@ void board_init_f(ulong bootflag)
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
gd->bus_clk = bus_clk;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
bus_clk / 16 / CONFIG_BAUDRATE);
#ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");

6
board/Arcturus/ucp1020/spl_minimal.c
View File

@ -34,7 +34,7 @@ void board_init_f(ulong bootflag)
plat_ratio >>= 1;
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM1,
gd->bus_clk / 16 / CONFIG_BAUDRATE);
puts("\nNAND boot... ");
@ -55,9 +55,9 @@ void board_init_r(gd_t *gd, ulong dest_addr)
void putc(char c)
{
if (c == '\n')
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, '\r');
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM1, c);
}
void puts(const char *str)

9
board/Synology/ds109/ds109.c
View File

@ -106,10 +106,11 @@ void reset_misc(void)
printf("Synology reset...");
udelay(50000);
b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
CONFIG_SYS_NS16550_CLK, 9600);
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
b_d = ns16550_calc_divisor((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
CONFIG_SYS_NS16550_CLK, 9600);
ns16550_init((struct ns16550 *)CONFIG_SYS_NS16550_COM2, b_d);
ns16550_putc((struct ns16550 *)CONFIG_SYS_NS16550_COM2,
SOFTWARE_REBOOT);
}
/* Support old kernels */

2
board/armltd/integrator/integrator.c
View File

@ -43,7 +43,7 @@ static const struct pl01x_serial_plat serial_plat = {
#endif
};
U_BOOT_DEVICE(integrator_serials) = {
U_BOOT_DRVINFO(integrator_serials) = {
.name = "serial_pl01x",
.plat = &serial_plat,
};

2
board/armltd/total_compute/total_compute.c
View File

@ -15,7 +15,7 @@ static const struct pl01x_serial_plat serial_plat = {
.clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(total_compute_serials) = {
U_BOOT_DRVINFO(total_compute_serials) = {
.name = "serial_pl01x",
.plat = &serial_plat,
};

2
board/armltd/vexpress64/vexpress64.c
View File

@ -26,7 +26,7 @@ static const struct pl01x_serial_plat serial_plat = {
.clock = CONFIG_PL011_CLOCK,
};
U_BOOT_DEVICE(vexpress_serials) = {
U_BOOT_DRVINFO(vexpress_serials) = {
.name = "serial_pl01x",
.plat = &serial_plat,
};

2
board/bluewater/gurnard/gurnard.c
View File

@ -420,7 +420,7 @@ static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
U_BOOT_DRVINFO(at91sam9260_serial) = {
.name = "serial_atmel",
.plat = &at91sam9260_serial_plat,
};

2
board/bluewater/snapper9260/snapper9260.c
View File

@ -147,7 +147,7 @@ static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
U_BOOT_DRVINFO(at91sam9260_serial) = {
.name = "serial_atmel",
.plat = &at91sam9260_serial_plat,
};

4
board/cadence/xtfpga/xtfpga.c
View File

@ -93,7 +93,7 @@ int misc_init_r(void)
return 0;
}
U_BOOT_DEVICE(sysreset) = {
U_BOOT_DRVINFO(sysreset) = {
.name = "xtfpga_sysreset",
};
@ -104,7 +104,7 @@ static struct ethoc_eth_pdata ethoc_pdata = {
.packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
};
U_BOOT_DEVICE(ethoc) = {
U_BOOT_DRVINFO(ethoc) = {
.name = "ethoc",
.plat = &ethoc_pdata,
};

4
board/cavium/thunderx/thunderx.c
View File

@ -25,7 +25,7 @@ static const struct pl01x_serial_plat serial0 = {
.skip_init = true,
};
U_BOOT_DEVICE(thunderx_serial0) = {
U_BOOT_DRVINFO(thunderx_serial0) = {
.name = "serial_pl01x",
.plat = &serial0,
};
@ -37,7 +37,7 @@ static const struct pl01x_serial_plat serial1 = {
.skip_init = true,
};
U_BOOT_DEVICE(thunderx_serial1) = {
U_BOOT_DRVINFO(thunderx_serial1) = {
.name = "serial_pl01x",
.plat = &serial1,
};

2
board/compulab/cm_fx6/cm_fx6.c
View File

@ -728,7 +728,7 @@ static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART4_BASE,
};
U_BOOT_DEVICE(cm_fx6_serial) = {
U_BOOT_DRVINFO(cm_fx6_serial) = {
.name = "serial_mxc",
.plat = &cm_fx6_mxc_serial_plat,
};

4
board/davinci/da8xxevm/omapl138_lcdk.c
View File

@ -363,7 +363,7 @@ static const struct ns16550_plat serial_pdata = {
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(omapl138_uart) = {
U_BOOT_DRVINFO(omapl138_uart) = {
.name = "ns16550_serial",
.plat = &serial_pdata,
};
@ -379,7 +379,7 @@ static const struct davinci_mmc_plat mmc_plat = {
.name = "da830-mmc",
},
};
U_BOOT_DEVICE(omapl138_mmc) = {
U_BOOT_DRVINFO(omapl138_mmc) = {
.name = "ti_da830_mmc",
.plat = &mmc_plat,
};

6
board/dhelectronics/dh_stm32mp1/board.c
View File

@ -343,7 +343,7 @@ int g_dnl_board_usb_cable_connected(void)
int ret;
ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
DM_GET_DRIVER(dwc2_udc_otg),
DM_DRIVER_GET(dwc2_udc_otg),
&dwc2_udc_otg);
if (!ret)
debug("dwc2_udc_otg init failed\n");
@ -475,11 +475,11 @@ static void sysconf_init(void)
* but this value need to be consistent with board design
*/
ret = uclass_get_device_by_driver(UCLASS_PMIC,
DM_GET_DRIVER(stm32mp_pwr_pmic),
DM_DRIVER_GET(stm32mp_pwr_pmic),
&pwr_dev);
if (!ret) {
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_GET_DRIVER(stm32mp_bsec),
DM_DRIVER_GET(stm32mp_bsec),
&dev);
if (ret) {
pr_err("Can't find stm32mp_bsec driver\n");

4
board/freescale/ls1012afrdm/eth.c
View File

@ -114,12 +114,12 @@ static struct pfe_eth_pdata pfe_pdata1 = {
},
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
U_BOOT_DRVINFO(ls1012a_pfe0) = {
.name = "pfe_eth",
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
U_BOOT_DRVINFO(ls1012a_pfe1) = {
.name = "pfe_eth",
.plat = &pfe_pdata1,
};

4
board/freescale/ls1012aqds/eth.c
View File

@ -298,12 +298,12 @@ static struct pfe_eth_pdata pfe_pdata1 = {
},
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
U_BOOT_DRVINFO(ls1012a_pfe0) = {
.name = "pfe_eth",
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
U_BOOT_DRVINFO(ls1012a_pfe1) = {
.name = "pfe_eth",
.plat = &pfe_pdata1,
};

4
board/freescale/ls1012ardb/eth.c
View File

@ -160,12 +160,12 @@ static struct pfe_eth_pdata pfe_pdata1 = {
},
};
U_BOOT_DEVICE(ls1012a_pfe0) = {
U_BOOT_DRVINFO(ls1012a_pfe0) = {
.name = "pfe_eth",
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
U_BOOT_DRVINFO(ls1012a_pfe1) = {
.name = "pfe_eth",
.plat = &pfe_pdata1,
};

4
board/freescale/lx2160a/lx2160a.c
View File

@ -63,7 +63,7 @@ static struct pl01x_serial_plat serial0 = {
.type = TYPE_PL011,
};
U_BOOT_DEVICE(nxp_serial0) = {
U_BOOT_DRVINFO(nxp_serial0) = {
.name = "serial_pl01x",
.plat = &serial0,
};
@ -73,7 +73,7 @@ static struct pl01x_serial_plat serial1 = {
.type = TYPE_PL011,
};
U_BOOT_DEVICE(nxp_serial1) = {
U_BOOT_DRVINFO(nxp_serial1) = {
.name = "serial_pl01x",
.plat = &serial1,
};

6
board/freescale/mpc8313erdb/mpc8313erdb.c
View File

@ -132,7 +132,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
@ -152,8 +152,8 @@ void putc(char c)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif

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