mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1d2b8585f6
At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL. Move them to a subnode so that TPL does not included them. Signed-off-by: Simon Glass <sjg@chromium.org>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/fsp_bindings.h>
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#include <asm/fsp2/fsp_internal.h>
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#include <dm/uclass-internal.h>
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int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
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{
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struct fsp_m_config *cfg = &upd->config;
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struct fspm_arch_upd *arch = &upd->arch;
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int cache_ret = 0;
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ofnode node;
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int ret;
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arch->nvs_buffer_ptr = NULL;
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cache_ret = prepare_mrc_cache(upd);
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if (cache_ret && cache_ret != -ENOENT)
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return log_msg_ret("mrc", cache_ret);
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arch->stack_base = (void *)(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE -
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arch->stack_size);
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arch->boot_loader_tolum_size = 0;
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arch->boot_mode = cache_ret ? FSP_BOOT_WITH_FULL_CONFIGURATION :
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FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
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node = dev_ofnode(dev);
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if (!ofnode_valid(node))
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return log_msg_ret("node", -ENOENT);
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node = ofnode_find_subnode(node, "fsp-m");
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if (!ofnode_valid(node))
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return log_msg_ret("fspm", -ENOENT);
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ret = fsp_m_update_config_from_dtb(node, cfg);
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if (ret)
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return log_msg_ret("dtb", cache_ret);
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return cache_ret;
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}
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/*
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* The FSP-M binary appears to break the SPI controller. It can be fixed by
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* writing the BAR again, so do that here
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*/
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int fspm_done(struct udevice *dev)
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{
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struct udevice *spi;
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int ret;
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/* Don't probe the device, since that reads the BAR */
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ret = uclass_find_first_device(UCLASS_SPI, &spi);
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if (ret)
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return log_msg_ret("SPI", ret);
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if (!spi)
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return log_msg_ret("no SPI", -ENODEV);
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dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
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IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
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return 0;
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}
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