mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
20e442ab2d
The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
185 lines
5.2 KiB
C
185 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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/*
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* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
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* peripheral pins. Good to have if hardware is soldered optionally
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* or in case of SPI no slave is selected. Avoid lines to float
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* needlessly. Use a short local PUP define.
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*
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* Due to errata "TXD floats when CTS is inactive" pullups are always
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* on for TXD pins.
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*/
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#ifdef CONFIG_AT91_GPIO_PULLUP
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# define PUP CONFIG_AT91_GPIO_PULLUP
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#else
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# define PUP 0
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#endif
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void at91_serial0_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
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at91_periph_clk_enable(ATMEL_ID_USART0);
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}
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void at91_serial1_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
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at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
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at91_periph_clk_enable(ATMEL_ID_USART1);
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}
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void at91_serial2_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
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at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
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at91_periph_clk_enable(ATMEL_ID_USART2);
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}
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void at91_seriald_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
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at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
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at91_periph_clk_enable(ATMEL_ID_SYS);
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}
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#ifdef CONFIG_ATMEL_SPI
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
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at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
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at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
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at91_periph_clk_enable(ATMEL_ID_SPI0);
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if (cs_mask & (1 << 0)) {
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at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
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}
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}
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void at91_spi1_hw_init(unsigned long cs_mask)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
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at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
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at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
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at91_periph_clk_enable(ATMEL_ID_SPI1);
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if (cs_mask & (1 << 0)) {
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at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
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}
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}
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#endif
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#ifdef CONFIG_MACB
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void at91_macb_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */
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at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */
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at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */
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at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */
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at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */
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at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */
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at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */
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at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */
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at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */
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at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */
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at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */
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at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */
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at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */
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at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */
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at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */
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#endif
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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void at91_mci_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
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at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
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at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
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at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */
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at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
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at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
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at91_periph_clk_enable(ATMEL_ID_MCI0);
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}
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#endif
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/* Platform data for the GPIOs */
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static const struct at91_port_plat at91sam9260_plat[] = {
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{ ATMEL_BASE_PIOA, "PA" },
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{ ATMEL_BASE_PIOB, "PB" },
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{ ATMEL_BASE_PIOC, "PC" },
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{ ATMEL_BASE_PIOD, "PD" },
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{ ATMEL_BASE_PIOE, "PE" },
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};
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U_BOOT_DRVINFOS(at91sam9260_gpios) = {
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{ "atmel_at91rm9200_gpio", &at91sam9260_plat[0] },
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{ "atmel_at91rm9200_gpio", &at91sam9260_plat[1] },
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{ "atmel_at91rm9200_gpio", &at91sam9260_plat[2] },
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{ "atmel_at91rm9200_gpio", &at91sam9260_plat[3] },
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{ "atmel_at91rm9200_gpio", &at91sam9260_plat[4] },
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};
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