mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
20e442ab2d
The current macro is a misnomer since it does not declare a device directly. Instead, it declares driver_info record which U-Boot uses at runtime to create a device. The distinction seems somewhat minor most of the time, but is becomes quite confusing when we actually want to declare a device, with of-platdata. We are left trying to distinguish between a device which isn't actually device, and a device that is (perhaps an 'instance'?) It seems better to rename this macro to describe what it actually is. The macros is not widely used, since boards should use devicetree to declare devices. Rename it to U_BOOT_DRVINFO(), which indicates clearly that this is declaring a new driver_info record, not a device. Signed-off-by: Simon Glass <sjg@chromium.org>
279 lines
6.4 KiB
C
279 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010-2015
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <ns16550.h>
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#include <spl.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#if IS_ENABLED(CONFIG_TEGRA_CLKRST)
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#include <asm/arch/clock.h>
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
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#include <asm/arch/funcmux.h>
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_MC)
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#include <asm/arch/mc.h>
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#endif
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/board.h>
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#include <asm/arch-tegra/cboot.h>
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#include <asm/arch-tegra/pmc.h>
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#include <asm/arch-tegra/sys_proto.h>
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#include <asm/arch-tegra/warmboot.h>
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void save_boot_params_ret(void);
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* UARTs which we can enable */
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UARTA = 1 << 0,
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UARTB = 1 << 1,
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UARTC = 1 << 2,
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UARTD = 1 << 3,
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UARTE = 1 << 4,
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UART_COUNT = 5,
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};
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static bool from_spl __attribute__ ((section(".data")));
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#ifndef CONFIG_SPL_BUILD
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void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
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unsigned long r3)
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{
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from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
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/*
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* The logic for this is somewhat indirect. The purpose of the marker
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* (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
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* was loaded from a read-only instance of itself, which is something
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* that can happen in secure boot setups. So basically the presence
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* of the marker is an indication that U-Boot was loaded by one such
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* special variant of U-Boot. Conversely, the absence of the marker
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* indicates that this instance of U-Boot was loaded by something
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* other than a special U-Boot. This could be SPL, but it could just
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* as well be one of any number of other first stage bootloaders.
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*/
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if (from_spl)
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cboot_save_boot_params(r0, r1, r2, r3);
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save_boot_params_ret();
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}
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#endif
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bool spl_was_boot_source(void)
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{
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return from_spl;
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}
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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#if !defined(CONFIG_TEGRA124)
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#error tegra_cpu_is_non_secure has only been validated on Tegra124
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#endif
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bool tegra_cpu_is_non_secure(void)
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{
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/*
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* This register reads 0xffffffff in non-secure mode. This register
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* only implements bits 31:20, so the lower bits will always read 0 in
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* secure mode. Thus, the lower bits are an indicator for secure vs.
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* non-secure mode.
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*/
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struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
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uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
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return (mc_s_cfg0 & 1) == 1;
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}
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_MC)
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/* Read the RAM size directly from the memory controller */
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static phys_size_t query_sdram_size(void)
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{
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struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
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u32 emem_cfg;
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phys_size_t size_bytes;
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emem_cfg = readl(&mc->mc_emem_cfg);
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#if defined(CONFIG_TEGRA20)
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debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
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size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
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#else
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debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
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#ifndef CONFIG_PHYS_64BIT
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/*
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* If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
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* and will wrap. Clip the reported size to the maximum that a 32-bit
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* variable can represent (rounded to a page).
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*/
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if (emem_cfg >= 4096) {
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size_bytes = U32_MAX & ~(0x1000 - 1);
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} else
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#endif
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{
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/* RAM size EMC is programmed to. */
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size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
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#ifndef CONFIG_ARM64
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/*
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* If all RAM fits within 32-bits, it can be accessed without
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* LPAE, so go test the RAM size. Otherwise, we can't access
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* all the RAM, and get_ram_size() would get confused, so
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* avoid using it. There's no reason we should need this
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* validation step anyway.
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*/
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if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
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size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
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size_bytes);
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#endif
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}
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#endif
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#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
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/* External memory limited to 2047 MB due to IROM/HI-VEC */
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if (size_bytes == SZ_2G)
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size_bytes -= SZ_1M;
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#endif
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return size_bytes;
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}
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#endif
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int dram_init(void)
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{
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int err;
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/* try to initialize DRAM from cboot DTB first */
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err = cboot_dram_init();
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if (err == 0)
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return 0;
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#if IS_ENABLED(CONFIG_TEGRA_MC)
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/* We do not initialise DRAM here. We just query the size */
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gd->ram_size = query_sdram_size();
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#endif
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return 0;
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}
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#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
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static int uart_configs[] = {
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#if defined(CONFIG_TEGRA20)
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#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
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FUNCMUX_UART1_UAA_UAB,
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#elif defined(CONFIG_TEGRA_UARTA_GPU)
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FUNCMUX_UART1_GPU,
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#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
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FUNCMUX_UART1_SDIO1,
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#else
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FUNCMUX_UART1_IRRX_IRTX,
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#endif
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FUNCMUX_UART2_UAD,
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-1,
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FUNCMUX_UART4_GMC,
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-1,
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#elif defined(CONFIG_TEGRA30)
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FUNCMUX_UART1_ULPI, /* UARTA */
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-1,
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-1,
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-1,
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-1,
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#elif defined(CONFIG_TEGRA114)
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-1,
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-1,
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-1,
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FUNCMUX_UART4_GMI, /* UARTD */
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-1,
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#elif defined(CONFIG_TEGRA124)
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FUNCMUX_UART1_KBC, /* UARTA */
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-1,
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-1,
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FUNCMUX_UART4_GPIO, /* UARTD */
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-1,
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#else /* Tegra210 */
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FUNCMUX_UART1_UART1, /* UARTA */
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-1,
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-1,
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FUNCMUX_UART4_UART4, /* UARTD */
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-1,
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#endif
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};
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/**
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* Set up the specified uarts
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*
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* @param uarts_ids Mask containing UARTs to init (UARTx)
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*/
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static void setup_uarts(int uart_ids)
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{
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static enum periph_id id_for_uart[] = {
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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PERIPH_ID_UART3,
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PERIPH_ID_UART4,
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PERIPH_ID_UART5,
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};
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size_t i;
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for (i = 0; i < UART_COUNT; i++) {
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if (uart_ids & (1 << i)) {
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enum periph_id id = id_for_uart[i];
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funcmux_select(id, uart_configs[i]);
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clock_ll_start_uart(id);
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}
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}
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}
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#endif
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void board_init_uart_f(void)
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{
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#if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
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int uart_ids = 0; /* bit mask of which UART ids to enable */
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#ifdef CONFIG_TEGRA_ENABLE_UARTA
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uart_ids |= UARTA;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTB
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uart_ids |= UARTB;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTC
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uart_ids |= UARTC;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTD
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uart_ids |= UARTD;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTE
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uart_ids |= UARTE;
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#endif
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setup_uarts(uart_ids);
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#endif
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}
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static struct ns16550_plat ns16550_com1_pdata = {
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.base = CONFIG_SYS_NS16550_COM1,
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.reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK,
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.fcr = UART_FCR_DEFVAL,
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};
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U_BOOT_DRVINFO(ns16550_com1) = {
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"ns16550_serial", &ns16550_com1_pdata
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};
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#endif
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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