huang lin be1d5e0388 rockchip: rk3036: Add core Soc start-up code ... rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288		2015-12-01 08:07:22 -07:00
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rk3036	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
rk3288	rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig	2015-12-01 08:07:22 -07:00
board.c	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
common.c	rockchip: Add core SoC start-up code	2015-09-02 21:28:24 -06:00
Kconfig	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
Makefile	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
rk3036-board-spl.c	rockchip: rk3036: Add core Soc start-up code	2015-12-01 08:07:22 -07:00
rk3288-board-spl.c	rockchip: rename board-spl.c to rk3288-board-spl.c	2015-12-01 08:07:22 -07:00
rk_early_print.c	rockchip: add early uart driver	2015-12-01 08:07:22 -07:00
rk_timer.c	rockchip: add timer driver	2015-12-01 08:07:22 -07:00